View SH7760_4784711.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Cautions
Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
Hitachi SuperH
TM
RISC engine
SH7760
HD6417760BP200D
Hardware Manual
ADE-602-291 Rev. 1.0 02/28/03 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Rev. 1.0, 02/03, page ii of xlviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 1.0, 02/03, page iii of xlviii
Configuration of This Manual
This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual.
Rev. 1.0, 02/03, page iv of xlviii
Preface
The SH7760 RISC (Reduced Instruction Set Computer) microcomputer includes a Hitachioriginal RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users.
Notes on reading this manual: * Product names The following products are covered in this manual.
Product Classifications and Abbreviations Basic Classification SH7760 (256-pin LBGA) Product Code HD6417760BP200D
* In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, and peripheral functions. Rules: Bit order: Signal notation: Related Manuals: The MSB is on the left and the LSB is on the right. An overbar is added to a low-active signal: xxxx
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com
Rev. 1.0, 02/03, page v of xlviii
Contents
Section 1 Overview ...........................................................................................1
1.1 1.2 1.3 1.4 1.5 Features............................................................................................................................. 2 Block Diagram .................................................................................................................. 10 Pin Arrangement ............................................................................................................... 11 Pin Description.................................................................................................................. 12 Pin Function ...................................................................................................................... 21
Section 2 Programming Model..........................................................................29
2.1 2.2 Data Formats..................................................................................................................... 29 Register Descriptions ........................................................................................................ 30 2.2.1 Privileged Mode and Banks ................................................................................. 30 2.2.2 General Registers ................................................................................................. 33 2.2.3 Control Registers ................................................................................................. 34 2.2.4 System Registers.................................................................................................. 36 2.2.5 FPU Registers ...................................................................................................... 36 Memory-Mapped Registers............................................................................................... 36 Data Formats..................................................................................................................... 37 2.4.1 Data Format in Registers ..................................................................................... 37 2.4.2 Data Formats in Memory ..................................................................................... 37 Processing States............................................................................................................... 38 Processing Modes ............................................................................................................. 40
2.3 2.4
2.5 2.6
Section 3 Floating-Point Unit (FPU).................................................................41
3.1 3.2 Features............................................................................................................................. 41 Data Formats..................................................................................................................... 41 3.2.1 Floating-Point Format.......................................................................................... 41 3.2.2 Non-Numbers (NaN) ........................................................................................... 43 3.2.3 Denormalized Numbers ....................................................................................... 44 Register Descriptions ........................................................................................................ 45 3.3.1 Floating-Point Registers....................................................................................... 45 3.3.2 Floating-Point Status/Control Register (FPSCR)................................................. 47 3.3.3 Floating-Point Communication Register (FPUL) ................................................ 48 Rounding........................................................................................................................... 49 Floating-Point Exceptions................................................................................................. 49 3.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions................... 49 3.5.2 FPU Exception Sources ....................................................................................... 49 3.5.3 FPU Exception Handling ..................................................................................... 50 Graphics Support Functions.............................................................................................. 52 3.6.1 Geometric Operation Instructions........................................................................ 52
3.3
3.4 3.5
3.6
Rev. 1.0, 02/03, page vi of xlviii
3.7
3.6.2 Pair Single-Precision Data Transfer.....................................................................53 Notes on programming......................................................................................................53
Section 4 Instruction Set ................................................................................... 55
4.1 4.2 4.3 Execution Environment.....................................................................................................55 Addressing Modes.............................................................................................................57 Instruction Set ...................................................................................................................61
Section 5 Pipelining .......................................................................................... 73
5.1 5.2 5.3 Pipelines............................................................................................................................73 Parallel-Executability........................................................................................................80 Execution Cycles and Pipeline Stalling ............................................................................83
Section 6 Memory Management Unit (MMU) ................................................. 99
6.1 6.2 Overview of the MMU......................................................................................................99 6.1.1 Address Spaces ....................................................................................................101 Register Descriptions ........................................................................................................108 6.2.1 Page Table Entry High Register (PTEH) .............................................................109 6.2.2 Page Table Entry Low Register (PTEL) ..............................................................110 6.2.3 Page Table Entry Assistance Register (PTEA) ....................................................111 6.2.4 Translation Table Base Register (TTB) ...............................................................111 6.2.5 TLB Exception Address Register (TEA) .............................................................112 6.2.6 MMU Control Register (MMUCR) .....................................................................112 TLB Functions ..................................................................................................................115 6.3.1 Unified TLB (UTLB) Configuration ...................................................................115 6.3.2 Instruction TLB (ITLB) Configuration................................................................118 6.3.3 Address Translation Method................................................................................119 MMU Functions................................................................................................................121 6.4.1 MMU Hardware Management .............................................................................121 6.4.2 MMU Software Management ..............................................................................121 6.4.3 MMU Instruction (LDTLB).................................................................................121 6.4.4 Hardware ITLB Miss Handling ...........................................................................122 6.4.5 Avoiding Synonym Problems ..............................................................................123 MMU Exceptions..............................................................................................................124 6.5.1 Instruction TLB Multiple Hit Exception..............................................................124 6.5.2 Instruction TLB Miss Exception..........................................................................125 6.5.3 Instruction TLB Protection Violation Exception .................................................126 6.5.4 Data TLB Multiple Hit Exception........................................................................127 6.5.5 Data TLB Miss Exception....................................................................................127 6.5.6 Data TLB Protection Violation Exception ...........................................................128 6.5.7 Initial Page Write Exception ................................................................................129 Memory-Mapped TLB Configuration...............................................................................130
Rev. 1.0, 02/03, page vii of xlviii
6.3
6.4
6.5
6.6
6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6
ITLB Address Array ............................................................................................ 131 ITLB Data Array 1............................................................................................... 132 ITLB Data Array 2............................................................................................... 133 UTLB Address Array........................................................................................... 133 UTLB Data Array 1 ............................................................................................. 135 UTLB Data Array 2 ............................................................................................. 136
Section 7 Caches................................................................................................137
7.1 7.2 Features............................................................................................................................. 137 Register Descriptions ........................................................................................................ 141 7.2.1 Cache Control Register (CCR) ............................................................................ 142 7.2.2 Queue Address Control Register 0 (QACR0) ...................................................... 144 7.2.3 Queue Address Control Register 1 (QACR1) ...................................................... 145 Operand Cache Operation................................................................................................. 145 7.3.1 Read Operation .................................................................................................... 145 7.3.2 Write Operation ................................................................................................... 146 7.3.3 Write-Back Buffer ............................................................................................... 148 7.3.4 Write-Through Buffer.......................................................................................... 148 7.3.5 RAM Mode .......................................................................................................... 148 7.3.6 OC Index Mode ................................................................................................... 149 7.3.7 Coherency between Cache and External Memory ............................................... 149 7.3.8 Prefetch Operation ............................................................................................... 149 Instruction Cache Operation ............................................................................................. 150 7.4.1 Read Operation .................................................................................................... 150 7.4.2 IC Index Mode ..................................................................................................... 150 Memory-Mapped Cache Configuration (Cache Direct Mapping Mode) .......................... 151 7.5.1 IC Address Array ................................................................................................. 151 7.5.2 IC Data Array....................................................................................................... 152 7.5.3 OC Address Array ............................................................................................... 153 7.5.4 OC Data Array ..................................................................................................... 155 Memory-Mapped Cache Configuration (Double-Size Cache Mode)................................ 156 7.6.1 IC Address Array ................................................................................................. 156 7.6.2 IC Data Array....................................................................................................... 157 7.6.3 OC Address Array ............................................................................................... 158 7.6.4 OC Data Array ..................................................................................................... 160 7.6.5 Summary of Memory-Mapping of OC ................................................................ 161 Store Queues ..................................................................................................................... 161 7.7.1 SQ Configuration................................................................................................. 161 7.7.2 Writing to SQ....................................................................................................... 162 7.7.3 Transfer to External Memory............................................................................... 162 7.7.4 Determination of SQ Access Exception............................................................... 163 7.7.5 Reading from SQ ................................................................................................. 164
7.3
7.4
7.5
7.6
7.7
Rev. 1.0, 02/03, page viii of xlviii
Section 8 Exceptions......................................................................................... 165
8.1 Exception Handling Functions..........................................................................................165 8.1.1 Exception Handling Flow ....................................................................................165 8.1.2 Exception Handling Vector Addresses ................................................................166 Exception Types and Priorities .........................................................................................167 Exception Flow .................................................................................................................171 8.3.1 Exception Flow ....................................................................................................171 8.3.2 Exception Source Acceptance..............................................................................172 8.3.3 Exception Requests and BL Bit ...........................................................................173 8.3.4 Return from Exception Handling .........................................................................173 Register Descriptions ........................................................................................................174 8.4.1 Exception Event Register (EXPEVT) ..................................................................175 8.4.2 Interrupt Event Register (INTEVT) .....................................................................175 8.4.3 TRAPA Exception Register (TRA) .....................................................................176 Operation...........................................................................................................................177 8.5.1 Resets ...................................................................................................................177 8.5.2 General Exceptions ..............................................................................................182 8.5.3 Interrupts..............................................................................................................196 8.5.4 Priority Order with Multiple Exceptions..............................................................200 Usage Notes ......................................................................................................................201 Restrictions .......................................................................................................................202 8.7.1 Restrictions on First Instruction in Exception Handling Routine ........................202
8.2 8.3
8.4
8.5
8.6 8.7
Section 9 Interrupt Controller (INTC) .............................................................. 203
9.1 9.2 9.3 Features .............................................................................................................................203 Input/Output Pins ..............................................................................................................205 Register Descriptions ........................................................................................................205 9.3.1 Interrupt Priority Level Setting Registers A to D (IPRA to IPRD)......................207 9.3.2 Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C)...208 9.3.3 Interrupt Control Register (ICR)..........................................................................209 9.3.4 Interrupt Source Registers 00, 04 (INTREQ00, INTREQ04) ..............................211 9.3.5 Interrupt Mask Registers 00, 04 (INTMSK00, INTMSK04) ...............................213 9.3.6 Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04) ......216 Interrupt Sources ...............................................................................................................217 9.4.1 NMI Interrupt.......................................................................................................217 9.4.2 IRQ Interrupts ......................................................................................................217 9.4.3 IRL Interrupts.......................................................................................................217 9.4.4 Peripheral Module Interrupts ...............................................................................219 9.4.5 Interrupt Exception Handling and Priority...........................................................220 Operation...........................................................................................................................225 9.5.1 Interrupt Operation Sequence ..............................................................................225 9.5.2 Multiple Interrupts ...............................................................................................227
Rev. 1.0, 02/03, page ix of xlviii
9.4
9.5
9.6
9.5.3 Interrupt Masking with MAI Bit.......................................................................... 227 Interrupt Response Time................................................................................................... 228
Section 10 Bus State Controller (BSC) .............................................................229
10.1 10.2 10.3 10.4 10.5 Features............................................................................................................................. 229 Input/Output Pins .............................................................................................................. 232 Overview of Areas ............................................................................................................ 233 PCMCIA Support.............................................................................................................. 237 Register Descriptions ........................................................................................................ 241 10.5.1 Bus Control Register 1 (BCR1) ........................................................................... 243 10.5.2 Bus Control Register 2 (BCR2) ........................................................................... 249 10.5.3 Bus Control Register 3 (BCR3) ........................................................................... 250 10.5.4 Bus Control Register 4 (BCR4) ........................................................................... 252 10.5.5 Wait Control Register 1 (WCR1)......................................................................... 254 10.5.6 Wait Control Register 2 (WCR2)......................................................................... 257 10.5.7 Wait Control Register 3 (WCR3)......................................................................... 264 10.5.8 Wait Control Register 4 (WCR4)......................................................................... 265 10.5.9 Memory Control Register (MCR)........................................................................ 266 10.5.10 PCMCIA Control Register (PCR)........................................................................ 271 10.5.11 Synchronous DRAM Mode Register (SDMR) .................................................... 274 10.5.12 Refresh Timer Control/Status Register (RTCSR) ................................................ 276 10.5.13 Refresh Timer Counter (RTCNT)........................................................................ 278 10.5.14 Refresh Time Constant Register (RTCOR) ......................................................... 278 10.5.15 Refresh Count Register (RFCR) .......................................................................... 278 10.5.16 Accessing Refresh Control Related Registers...................................................... 279 10.6 Operation .......................................................................................................................... 280 10.6.1 Endian/Access Size and Data Alignment............................................................. 280 10.6.2 Areas .................................................................................................................... 287 10.6.3 SRAM Interface................................................................................................... 291 10.6.4 Synchronous DRAM Interface............................................................................. 300 10.6.5 Burst ROM Interface............................................................................................ 327 10.6.6 PCMCIA Interface............................................................................................... 330 10.6.7 MPX Interface...................................................................................................... 341 10.6.8 Byte Control SRAM Interface ............................................................................. 351 10.6.9 Waits between Access Cycles.............................................................................. 356 10.6.10 Bus Arbitration .................................................................................................... 357 10.6.11 Bus Release and Acquire Sequences ................................................................... 359 10.7 Usage Notes ...................................................................................................................... 360 10.7.1 Refresh ................................................................................................................. 360 10.7.2 Bus Arbitration .................................................................................................... 360
Rev. 1.0, 02/03, page x of xlviii
Section 11 Direct Memory Access Controller (DMAC) .................................. 361
11.1 Features .............................................................................................................................361 11.2 Input/Output Pins ..............................................................................................................364 11.3 Register Descriptions ........................................................................................................365 11.3.1 DMA Source Address Register (SAR).................................................................371 11.3.2 DMA Destination Address Register (DAR).........................................................371 11.3.3 DMA Transfer Count Register (DMATCR) ........................................................372 11.3.4 DMA Channel Control Register (CHCR) ............................................................373 11.3.5 DMA Operation Register (DMAOR)...................................................................382 11.3.6 DMA Request Resource Selection Registers (DMARSRA, DMARSRB) ..........384 11.3.7 DMA Pin Control Register (DMAPCR) ..............................................................388 11.3.8 DMA Request Control Register (DMARCR) ......................................................388 11.3.9 DMA BRG Control Register (DMABRGCR) .....................................................391 11.3.10 DMA Audio Source Address Register (DMAATXSAR) ....................................395 11.3.11 DMA Audio Destination Address Register (DMAARXDAR) ............................395 11.3.12 DMA Audio Transmit Transfer Count Register (DMAATXTCR)......................396 11.3.13 DMA Audio Receive Transfer Count Register (DMAARXTCR) .......................396 11.3.14 DMA Audio Control Register (DMAACR).........................................................397 11.3.15 DMA Audio Transmit Transfer Counter (DMAATXTCNT) ..............................400 11.3.16 DMA Audio Receive Transfer Counter (DMAARXTCNT)................................400 11.3.17 DMA USB Source Address Register (DMAUSAR)............................................401 11.3.18 DMA USB Destination Address Register (DMAUDAR)....................................401 11.3.19 DMA USB R/W Size Register (DMAURWSZ) ..................................................402 11.3.20 DMA USB Control Register (DMAUCR) ...........................................................403 11.4 Operation...........................................................................................................................404 11.4.1 DMA Transfer Procedure.....................................................................................404 11.4.2 DMA Transfer Requests ......................................................................................406 11.4.3 Channel Priorities.................................................................................................408 11.4.4 Types of DMA Transfer.......................................................................................411 11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing ...................................420 11.4.6 Ending DMA Transfer .........................................................................................441 11.4.7 Interrupt-Request Codes ......................................................................................444 11.5 Examples of Use ...............................................................................................................445 11.5.1 Examples of Transfer between External Memory and an External Device with DACK ..........................................................................................................445 11.6 DMABRG Operation ........................................................................................................447 11.6.1 DMABRG Request ..............................................................................................447 11.6.2 DMABRG Reset ..................................................................................................447 11.6.3 DMA Transfer Operating Mode for HAC and SSI ..............................................448 11.6.4 DMA Audio Receive Operation...........................................................................450 11.6.5 DMA Audio Transmit Operation .........................................................................450 11.6.6 Auto Reload Function ..........................................................................................453
Rev. 1.0, 02/03, page xi of xlviii
11.6.7 Forced Termination of DMA Audio Transfer...................................................... 453 11.6.8 Double Buffer Control for Audio Data ................................................................ 456 11.6.9 HAC/SSI Endian Conversion Function ............................................................... 456 11.6.10 Switching Data for Left and Right Channels ....................................................... 457 11.6.11 LCDC DMA Transfer .......................................................................................... 458 11.6.12 USB DMA Transfer............................................................................................. 458 11.6.13 USB Endian Conversion Function....................................................................... 460 11.6.14 DMABRG Interrupts ........................................................................................... 462 11.7 Usage Notes ...................................................................................................................... 464
Section 12 Clock Pulse Generator (CPG) .........................................................465
12.1 12.2 12.3 12.4 Features............................................................................................................................. 465 Input/Output Pins .............................................................................................................. 468 Clock Operating Modes .................................................................................................... 469 Register Descriptions ........................................................................................................ 471 12.4.1 Frequency Control Register (FRQCR) ................................................................ 472 12.4.2 Clock Division Register (DCKDR) ..................................................................... 474 12.4.3 Module Clock Control Register (MCKCR) ......................................................... 475 12.5 Frequency Changing Method............................................................................................ 476 12.5.1 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is Off) ............. 476 12.5.2 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is On).............. 476 12.5.3 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is On)..... 477 12.5.4 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is Off).... 477 12.5.5 Changing Frequency Division Ratio of CPU Clock or Peripheral Clock ............ 477 12.5.6 Switching between PLL Circuit 3 On/Off ........................................................... 477 12.5.7 Changing DCK Output Clock Division Ratio...................................................... 478 12.5.8 Controlling DCK Output Clock ........................................................................... 478 12.5.9 Controlling CKIO Output Clock.......................................................................... 479 12.6 Usage Notes ...................................................................................................................... 479
Section 13 Watchdog Timer (WDT) .................................................................481
13.1 Features............................................................................................................................. 481 13.2 Register Descriptions ........................................................................................................ 482 13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 483 13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 483 13.2.3 Notes on Register Access..................................................................................... 485 13.3 Operation .......................................................................................................................... 486 13.3.1 Standby Clearing Procedure ................................................................................ 486 13.3.2 Frequency Changing Procedure ........................................................................... 486 13.3.3 Using Watchdog Timer Mode.............................................................................. 487 13.3.4 Using Interval Timer Mode ................................................................................. 487
Rev. 1.0, 02/03, page xii of xlviii
Section 14 Power-Down Modes ....................................................................... 489
14.1 Input/Output Pins ..............................................................................................................491 14.2 Register Descriptions ........................................................................................................491 14.2.1 Standby Control Register (STBCR).....................................................................492 14.2.2 Standby Control Register 2 (STBCR2)................................................................493 14.2.3 Clock Stop Register 00 (CLKSTP00) ..................................................................495 14.2.4 Clock Stop Clear Register 00 (CLKSTPCLR00).................................................496 14.3 Operation...........................................................................................................................496 14.3.1 Sleep Mode ..........................................................................................................496 14.3.2 Deep Sleep Mode.................................................................................................497 14.3.3 Software Standby Mode.......................................................................................497 14.3.4 Module Standby Function....................................................................................498 14.3.5 Hardware Standby Mode .....................................................................................499 14.3.6 STATUS Pin Change Timing ..............................................................................499 14.3.7 Hardware Standby Mode Timing.........................................................................506
Section 15 Timer Unit (TMU) .......................................................................... 509
15.1 Features .............................................................................................................................509 15.2 Input/Output Pins ..............................................................................................................510 15.3 Register Descriptions ........................................................................................................511 15.3.1 Timer Start Register (TSTR)................................................................................512 15.3.2 Timer Constant Register (TCORn) (n = 0 to 2) ...................................................513 15.3.3 Timer Counter (TCNTn) (n = 0 to 2) ...................................................................513 15.3.4 Timer Control Registers (TCRn) (n = 0 to 2).......................................................514 15.3.5 Input Capture Register 2 (TCPR2).......................................................................516 15.4 Operation...........................................................................................................................517 15.4.1 Counter Operation................................................................................................517 15.4.2 Input Capture Function ........................................................................................519 15.5 Interrupts ...........................................................................................................................520 15.6 Usage Notes ......................................................................................................................521 15.6.1 Register Writes.....................................................................................................521 15.6.2 Reading from TCNT ............................................................................................521 15.6.3 External Clock Frequency....................................................................................521
Section 16 Timer/Counter (CMT) .................................................................... 523
16.1 Features .............................................................................................................................523 16.2 Input/Output Pins ..............................................................................................................524 16.3 Register Descriptions ........................................................................................................524 16.3.1 Configuration Register (CMTCFG) .....................................................................526 16.3.2 Free-Running Timer (CMTFRT) .........................................................................530 16.3.3 Control Register (CMTCTL) ...............................................................................530 16.3.4 IRQ Status Register (CMTIRQS) ........................................................................533
Rev. 1.0, 02/03, page xiii of xlviii
16.3.5 Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T).............................. 534 16.3.6 Channels 0 to 3 Stop Time Registers (CMTCH0ST to CMTCH3ST)................. 534 16.3.7 Channels 0 to 3 Counters (CMTCH0C to CMTCH3C) ....................................... 534 16.4 Operation .......................................................................................................................... 535 16.4.1 Edge Detection..................................................................................................... 535 16.4.2 32-Bit Timer: Input Capture ................................................................................ 536 16.4.3 32-Bit Timer: Output Compare............................................................................ 537 16.4.4 16-Bit Timer: Input Capture ................................................................................ 538 16.4.5 16-Bit Timer: Output Compare............................................................................ 539 16.4.6 Counter: Up-/Updown-Counter ........................................................................... 540 16.4.7 Counter: Up-Counter with Capture...................................................................... 541 16.4.8 Interrupts.............................................................................................................. 541 16.4.9 Rotary Mode ........................................................................................................ 542 16.4.10 Timer Frequency.................................................................................................. 542 16.4.11 Standby Mode ...................................................................................................... 542
Section 17 Serial Communication Interface with FIFO (SCIF)........................543
17.1 Features............................................................................................................................. 543 17.2 Input/Output Pins .............................................................................................................. 548 17.3 Register Descriptions ........................................................................................................ 549 17.3.1 Receive Shift Register (SCRSR).......................................................................... 552 17.3.2 Receive FIFO Data Register (SCFRDR) ............................................................. 552 17.3.3 Transmit Shift Register (SCTSR) ........................................................................ 553 17.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 553 17.3.5 Serial Mode Register (SCSMR)........................................................................... 554 17.3.6 Serial Control Register (SCSCR)......................................................................... 557 17.3.7 Serial Status Register (SCFSR)............................................................................ 560 17.3.8 Bit Rate Register (SCBRR) ................................................................................. 567 17.3.9 FIFO Control Register (SCFCR) ......................................................................... 568 17.3.10 Transmit FIFO Data Count Register (SCTFDR) ................................................. 570 17.3.11 Receive FIFO Data Count Register (SCRFDR)................................................... 570 17.3.12 Serial Port Register (SCSPTR) ............................................................................ 571 17.3.13 Line Status Register (SCLSR) ............................................................................. 574 17.3.14 Serial Error Register (SCRER) ............................................................................ 575 17.4 Operation .......................................................................................................................... 576 17.4.1 Overview.............................................................................................................. 576 17.4.2 Operation in Asynchronous Mode ....................................................................... 578 17.4.3 Operation in Synchronous Mode ......................................................................... 588 17.5 SCIF Interrupt Sources and the DMAC ............................................................................ 596 17.6 Usage Notes ...................................................................................................................... 597
Rev. 1.0, 02/03, page xiv of xlviii
Section 18 SIM Card Module (SIM) ................................................................ 601
18.1 Features .............................................................................................................................601 18.2 Input/Output Pins ..............................................................................................................602 18.3 Register Descriptions ........................................................................................................603 18.3.1 Serial Mode Register (SISMR) ............................................................................605 18.3.2 Bit Rate Register (SIBRR) ...................................................................................606 18.3.3 Serial Control Register (SISCR) ..........................................................................606 18.3.4 Transmit Shift Register (SITSR)..........................................................................609 18.3.5 Transmit Data Register (SITDR) .........................................................................609 18.3.6 Serial Status Register (SISSR) .............................................................................610 18.3.7 Receive Shift Register (SIRSR) ...........................................................................616 18.3.8 Receive Data Register (SIRDR)...........................................................................616 18.3.9 Smart Card Mode Register (SISCMR).................................................................617 18.3.10 Serial Control 2 Register (SISC2R) .....................................................................619 18.3.11 Guard Extension Register (SIGRD).....................................................................619 18.3.12 Wait Time Register (SIWAIT) ............................................................................620 18.3.13 Sampling Register (SISMPL) ..............................................................................621 18.4 Operation...........................................................................................................................621 18.4.1 Data Format .........................................................................................................621 18.4.2 Register Settings ..................................................................................................623 18.4.3 Clocks ..................................................................................................................625 18.4.4 Data Transmission/Reception Operation .............................................................626 18.5 Usage Notes ......................................................................................................................630 18.5.1 Receive data Timing ............................................................................................630 18.5.2 Repetition when the Smart Card Interface is in Receiver Mode (T = 0)..............631 18.5.3 Repetition when the Smart Card Interface is in Transmitter Mode (T = 0) .........631 18.5.4 Transmit End Interrupt.........................................................................................633 18.5.5 Standby Mode Switching .....................................................................................633 18.5.6 Power-On and Clock Output................................................................................634 18.5.7 Pin Connections ...................................................................................................634
Section 19 Hitachi I2C Interface........................................................................ 637
19.1 Features .............................................................................................................................637 19.2 Input/Output Pins ..............................................................................................................638 19.3 Register Descriptions ........................................................................................................638 19.3.1 Slave Control Register (ICSCR) ..........................................................................641 19.3.2 Slave Status Register (ICSSR) .............................................................................642 19.3.3 Slave Interrupt Enable Register (ICSIER) ...........................................................645 19.3.4 Slave Address Register (ICSAR) .........................................................................646 19.3.5 Master Control Register (ICMCR).......................................................................646 19.3.6 Master Status Register (ICMSR) .........................................................................649 19.3.7 Master Interrupt Enable Register (ICMIER)........................................................651
Rev. 1.0, 02/03, page xv of xlviii
19.4
19.5
19.6
19.7
19.3.8 Master Address Register (ICMAR) ..................................................................... 652 19.3.9 Clock Control Register (ICCCR) ......................................................................... 652 19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD)............................................ 654 19.3.11 FIFO Control Register (ICFCR) .......................................................................... 655 19.3.12 FIFO Status Register (ICFSR) ............................................................................. 657 19.3.13 FIFO Interrupt Enable Register (ICFIER) ........................................................... 659 19.3.14 Receive FIFO Data Count Register (ICRFDR) ................................................... 660 19.3.15 Transmit FIFO Data Count Register (ICTFDR) .................................................. 661 Operation .......................................................................................................................... 661 19.4.1 Data and Clock Filters ......................................................................................... 661 19.4.2 Clock Generator................................................................................................... 661 19.4.3 Master and Slave Interfaces ................................................................................. 661 19.4.4 Software Status Interlocking................................................................................ 662 2 19.4.5 I C Bus Data Format ............................................................................................ 663 19.4.6 7-Bit Address Format........................................................................................... 664 19.4.7 10-Bit Address Format......................................................................................... 665 19.4.8 Master Transmit Operation (Single Buffer Mode)............................................... 666 19.4.9 Master Receiver Operation (Single Buffer Mode)............................................... 668 19.4.10 Standby Mode ...................................................................................................... 669 FIFO Mode Operation....................................................................................................... 670 19.5.1 Master Transmitter Operation (FIFO Buffer Mode) ............................................ 670 19.5.2 Master Receiver Operation (FIFO Buffer Mode) ................................................ 670 Programming Examples.................................................................................................... 671 19.6.1 Master Transmitter (Single Buffer Mode) ........................................................... 671 19.6.2 Master Receiver (Single Buffer Mode)................................................................ 672 19.6.3 Master Transmitter--Restart--Master Receiver (Single Buffer Mode) .............. 673 19.6.4 Master Transmitter (FIFO Buffer Mode)............................................................. 674 19.6.5 Master Receiver (FIFO Buffer Mode) ................................................................. 674 Usage Notes ...................................................................................................................... 675 19.7.1 Restriction 1......................................................................................................... 675 19.7.2 Restriction 2......................................................................................................... 678
Section 20 Serial Sound Interface (SSI) Module ..............................................681
20.1 Features............................................................................................................................. 681 20.2 Input/Output Pins .............................................................................................................. 682 20.3 Register Descriptions ........................................................................................................ 683 20.3.1 Control Register (SSICR) .................................................................................... 684 20.3.2 Status Register (SSISR) ....................................................................................... 690 20.3.3 Transmit Data Register (SSITDR) ....................................................................... 695 20.3.4 Receive Data Register (SSIRDR) ........................................................................ 695 20.4 Operation .......................................................................................................................... 696 20.4.1 Bus Format........................................................................................................... 696
Rev. 1.0, 02/03, page xvi of xlviii
20.4.2 Non-Compressed Modes......................................................................................696 20.4.3 Compressed Modes..............................................................................................705 20.4.4 Operation Modes..................................................................................................707 20.4.5 Transmit Operation ..............................................................................................708 20.4.6 Receive Operation................................................................................................711 20.4.7 Serial Clock Control ............................................................................................714 20.5 Usage Note........................................................................................................................714 20.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ...........714
Section 21 USB Host Module (USB) ............................................................... 715
21.1 Features .............................................................................................................................715 21.2 Input/Output Pins ..............................................................................................................717 21.3 Register Descriptions ........................................................................................................717 21.3.1 Host Controller Interface Revision Register (HcRevision)..................................720 21.3.2 Control Register (HcControl)...............................................................................720 21.3.3 Command Status Register (HcCommandStatus) .................................................724 21.3.4 Interrupt Status Register (HcInterruptStatus).......................................................726 21.3.5 Interrupt Enable Register (HcInterruptEnable) ....................................................728 21.3.6 Interrupt Disable Register (HcInterruptDisable)..................................................730 21.3.7 Host Controller Communication Area Pointer Register (HcHCCA) ...................732 21.3.8 Period Current ED Pointer Register (HcPeriodCurrentED).................................732 21.3.9 Control Head ED Pointer Register (HcControlHeadED).....................................733 21.3.10 Control Current ED Pointer Register (HcControlCurrentED) .............................733 21.3.11 Bulk Head ED Pointer Register (HcBulkHeadED)..............................................734 21.3.12 Bulk Current ED Pointer Register (HcBulkCurrentED) ......................................734 21.3.13 Done Queue Head Pointer Register (HcDoneHead) ............................................735 21.3.14 Frame Interval Register (HcFmInterval)..............................................................736 21.3.15 Frame Remaining Register (HcFmRemaining)....................................................737 21.3.16 Frame Number Register (HcFmNumber) ............................................................737 21.3.17 Periodic Start Register (HcPeriodicStart) ............................................................738 21.3.18 Low Speed Threshold Register (HcLSThreshold) ...............................................739 21.3.19 Root Hub Descriptor A Register (HcRhDescriptorA) .........................................740 21.3.20 Root Hub Descriptor B Register (HcRhDescriptorB) ..........................................742 21.3.21 Root Hub Status Register (HcRhStatus) ..............................................................744 21.3.22 Root Hub Port Status 1 Register (HcRhPortStatus1) ...........................................746 21.4 Memory.............................................................................................................................754 21.5 Data Storage Format for USB Host Controller .................................................................755 21.5.1 Storage Format of Transfer Data..........................................................................755 21.5.2 Storage Format of the Descriptor.........................................................................756 21.6 Restrictions on HcRhDescriptorA.....................................................................................756
Rev. 1.0, 02/03, page xvii of xlviii
Section 22 Hitachi Controller Area Network 2 (HCAN2) ................................757
22.1 Features............................................................................................................................. 757 22.2 Architecture ...................................................................................................................... 757 22.2.1 Block diagram...................................................................................................... 757 22.2.2 Block Function..................................................................................................... 759 22.3 Input/Output Pins .............................................................................................................. 760 22.4 Programming model - overview....................................................................................... 760 22.4.1 Memory map........................................................................................................ 760 22.4.2 Mail box............................................................................................................... 761 22.5 HCAN2 Control Registers ................................................................................................ 770 22.5.1 Master Control Register (CANMCR) .................................................................. 778 22.5.2 General Status Register (CANGSR) .................................................................... 784 22.5.3 Bit Configuration Registers 1 and 0 (CANBCR1, CANBCR0) .......................... 786 22.5.4 Interrupt Request Register (CANIRR)................................................................. 790 22.5.5 Interrupt Mask Register (CANIMR).................................................................... 795 22.5.6 Transmit Error Counter and Receive Error Counter (CANTECREC) ................. 796 22.5.7 Transmit Pending Request Registers 1 and 0 (CANTXPR1, CANTXPR0) ........ 797 22.5.8 Transmit Cancel Registers 1 and 0 (CANTXCR1, CANTXCR0) ....................... 799 22.5.9 Transmit Acknowledge Registers 0 and 1 (CANTXACK1, CANTXACK0)...... 801 22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0) .......... 802 22.5.11 Receive Data Frame Pending Registers 1 and 0 (CANRXPR1, CANRXPR0) ... 804 22.5.12 Remote Frame Request Pending Registers 1 and 0 (CANRFPR1, CANRFPR0) ................................................................................ 805 22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0) ..... 806 22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0)........... 807 22.5.15 Timer Counter Register (CANTCNTR)............................................................... 808 22.5.16 Timer Control Register (CANTCR) .................................................................... 809 22.5.17 Timer Compare Match Registers (CANTCMR).................................................. 810 22.6 Operation .......................................................................................................................... 812 22.6.1 Test Mode Settings .............................................................................................. 812 22.6.2 HCAN2 Settings .................................................................................................. 813 22.6.3 Message Transmission Sequence......................................................................... 814 22.6.4 Message Reception Sequence .............................................................................. 817 22.6.5 Reconfiguration of Mailbox................................................................................. 818 22.6.6 Standby Mode ...................................................................................................... 821
Section 23 Hitachi Serial Protocol Interface (HSPI).........................................823
23.1 Features............................................................................................................................. 823 23.2 Input/Output Pins .............................................................................................................. 824 23.3 Register Descriptions ........................................................................................................ 825 23.3.1 Control Register (SPCR)...................................................................................... 826
Rev. 1.0, 02/03, page xviii of xlviii
23.3.2 Status Register (SPSR).........................................................................................828 23.3.3 System Control Register (SPSCR).......................................................................831 23.3.4 Transmit Buffer Register (SPTBR)......................................................................834 23.3.5 Receive Buffer Register (SPRBR) .......................................................................835 23.4 Operation...........................................................................................................................836 23.4.1 Operation Overview without DMA (FIFO Mode Disabled)................................836 23.4.2 Operation Overview with DMA...........................................................................837 23.4.3 Operation with FIFO Mode Enabled....................................................................837 23.4.4 Timing Diagrams .................................................................................................838 23.4.5 HSPI Software Reset............................................................................................839 23.4.6 Clock Polarity and Transmit Control ...................................................................839 23.4.7 Transmit and Receive Routines ...........................................................................839 23.5 Power Saving and Clocking Strategy................................................................................840
Section 24 Pin Function Controller (PFC)........................................................ 841
24.1 Features .............................................................................................................................841 24.2 Register Descriptions ........................................................................................................844 24.2.1 Port A Control Register (PACR)..........................................................................847 24.2.2 Port B Control Register (PBCR) ..........................................................................848 24.2.3 Port C Control Register (PCCR) ..........................................................................849 24.2.4 Port D Control Register (PDCR)..........................................................................850 24.2.5 Port E Control Register (PECR) ..........................................................................852 24.2.6 Port F Control Register (PFCR)...........................................................................853 24.2.7 Port G Control Register (PGCR)..........................................................................854 24.2.8 Port H Control Register (PHCR)..........................................................................855 24.2.9 Port J Control Register (PJCR) ............................................................................857 24.2.10 Port K Control Register (PKCR)..........................................................................858 24.2.11 Port A Data Register (PADR) ..............................................................................859 24.2.12 Port B Data Register (PBDR) ..............................................................................860 24.2.13 Port C Data Register (PCDR) ..............................................................................861 24.2.14 Port D Data Register (PDDR) ..............................................................................861 24.2.15 Port E Data Register (PEDR)...............................................................................862 24.2.16 Port F Data Register (PFDR) ...............................................................................862 24.2.17 Port G Data Register (PGDR) ..............................................................................863 24.2.18 Port H Data Register (PHDR) ..............................................................................863 24.2.19 Port J Data Register (PJDR).................................................................................864 24.2.20 Port K Data Register (PKDR) ..............................................................................864 24.2.21 GPIO Interrupt Control Register (GPIOIC) .........................................................865 24.2.22 Port A Pull-Up Control Register (PAPUPR) .......................................................867 24.2.23 Port B Pull-Up Control Register (PBPUPR)........................................................867 24.2.24 Port C Pull-Up Control Register (PCPUPR)........................................................868 24.2.25 Port D Pull-Up Control Register (PDPUPR) .......................................................869
Rev. 1.0, 02/03, page xix of xlviii
24.2.26 Port E Pull-Up Control Register (PEPUPR) ........................................................ 869 24.2.27 Port F Pull-Up Control Register (PFPUPR)......................................................... 870 24.2.28 Port G Pull-Up Control Register (PGPUPR) ....................................................... 871 24.2.29 Port H Pull-Up Control Register (PHPUPR) ....................................................... 871 24.2.30 Port J Pull-Up Control Register (PJPUPR) .......................................................... 872 24.2.31 Port K Pull-Up Control Register (PKPUPR) ....................................................... 872 24.2.32 Mode-Pin Pull-Up Control Register (MDPUPR)................................................. 873 24.2.33 Input-Pin Pull-Up Control Register (INPUPA) ................................................... 874 24.2.34 DMA Pin Control Register (DMAPCR) .............................................................. 875 24.2.35 Peripheral Module Select Register (IPSELR)...................................................... 877 24.2.36 SCIF.Hi-z Control Register (SCIHZR)................................................................ 878 24.2.37 Mode Select Register (MODSELR) .................................................................... 879
Section 25 Hitachi Audio Codec Interface (HAC)............................................881
25.1 Features............................................................................................................................. 881 25.2 Input/Output Pins .............................................................................................................. 882 25.3 Register Descriptions ........................................................................................................ 883 25.3.1 Control and Status Register (HACCR) ................................................................ 885 25.3.2 Command/Status Address Register (HACCSAR) ............................................... 886 25.3.3 Command/Status Data Register (HACCSDR)..................................................... 888 25.3.4 PCM Left Channel Register (HACPCML) .......................................................... 889 25.3.5 PCM Right Channel Register (HACPCMR)........................................................ 890 25.3.6 TX Interrupt Enable Register (HACTIER) .......................................................... 891 25.3.7 TX Status Register (HACTSR)............................................................................ 892 25.3.8 RX Interrupt Enable Register (HACRIER).......................................................... 893 25.3.9 RX Status Register (HACRSR) ........................................................................... 895 25.3.10 HAC Control Register (HACACR) ..................................................................... 896 25.4 AC 97 Frame Slot Structure.............................................................................................. 898 25.5 Operation .......................................................................................................................... 899 25.5.1 Receiver ............................................................................................................... 899 25.5.2 Transmitter........................................................................................................... 900 25.5.3 DMA .................................................................................................................... 900 25.5.4 Interrupts.............................................................................................................. 900 25.5.5 Restrictions Related to HACTCR.CMDAMT ..................................................... 900 25.5.6 Initialization Sequence......................................................................................... 902 25.5.7 Power-Down Mode.............................................................................................. 907 25.5.8 Notes .................................................................................................................... 907 25.5.9 Reference ............................................................................................................. 907
Section 26 Multimedia Card Interface (MMCIF) .............................................909
26.1 Features............................................................................................................................. 909 26.2 Input/Output Pins .............................................................................................................. 910
Rev. 1.0, 02/03, page xx of xlviii
26.3 Register Descriptions ........................................................................................................911 26.3.1 Mode Register (MODER) ....................................................................................914 26.3.2 Command Type Register (CMDTYR).................................................................915 26.3.3 Response Type Register (RSPTYR) ....................................................................916 26.3.4 Transfer Byte Number Count Register (TBCR) ..................................................919 26.3.5 Command Registers 0 to 5 (CMDR0 to CMDR5) ...............................................920 26.3.6 Response Registers 0 to 16 (RSPR0 to RSPR16) ................................................921 26.3.7 Command Start Register (CMDSTRT)................................................................923 26.3.8 Operation Control Register (OPCR) ....................................................................924 26.3.9 Command Timeout Control Register (CTOCR) ..................................................926 26.3.10 Data Timeout Register (DTOUTR) .....................................................................927 26.3.11 Card Status Register (CSTR) ...............................................................................928 26.3.12 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2) ....................................930 26.3.13 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2)...................................932 26.3.14 Transfer Clock Control Register (CLKON).........................................................937 26.3.15 Data Register (DR) ..............................................................................................938 26.3.16 FIFO Pointer Clear Register (FIFOCLR).............................................................939 26.3.17 DMA Control Register (DMACR).......................................................................940 26.3.18 Receive Data Timing Select Register (RDTIMSEL) ...........................................941 26.4 Operation...........................................................................................................................941 26.4.1 Operations in MMC Mode...................................................................................941 26.5 MMCIF Interrupt Sources.................................................................................................964 26.6 Operations when Using DMA...........................................................................................965 26.6.1 Operation in Read Sequence ................................................................................965 26.6.2 Operation in Write Sequence ...............................................................................965 26.7 Register Accesses with Little Endian Specification..........................................................968
Section 27 Multifunctional Interface (MFI) ..................................................... 969
27.1 Features .............................................................................................................................969 27.2 Input/Output Pins ..............................................................................................................971 27.3 Register Descriptions ........................................................................................................972 27.3.1 MFI Index Register (MFIIDX) ............................................................................974 27.3.2 MFI General Status Register (MFIGSR) .............................................................975 27.3.3 MFI Status/Control Register (MFISCR) ..............................................................976 27.3.4 MFI Memory Control Register (MFIMCR).........................................................978 27.3.5 MFI Internal Interrupt Control Register (MFIIICR) ............................................980 27.3.6 MFI External Interrupt Control Register (MFIEICR) ..........................................981 27.3.7 MFI Address Register (MFIADR) .......................................................................982 27.3.8 MFI Data Register (MFIDATA)..........................................................................983 27.4 Operation...........................................................................................................................984 27.4.1 Overview..............................................................................................................984 27.4.2 Connections .........................................................................................................985
Rev. 1.0, 02/03, page xxi of xlviii
27.4.3 Memory Map ....................................................................................................... 985 27.5 Interface (Basic)................................................................................................................ 986 27.5.1 68-Series 8-Bit Parallel Interface......................................................................... 986 27.5.2 80-Series 8-Bit Parallel Interface......................................................................... 987 27.6 Interface (Details) ............................................................................................................. 988 27.6.1 Writing to MFIIDX/Reading from MFIGSR....................................................... 988 27.6.2 Reading from/Writing to MFI Register ............................................................... 988 27.6.3 Continuous Data Writing to MFRAM via MFI ................................................... 989 27.6.4 Continuous Reading from MFRAM via MFI ...................................................... 989
Section 28 Hitachi User Debug Interface (H-UDI) ...........................................991
28.1 Input/Output Pins .............................................................................................................. 993 28.2 Boundary Scan TAP Controllers (EXTEST, SAMPLE/PRELOAD, and BYPASS)........ 995 28.2.1 Boundary Scan Register (SDBSR) ...................................................................... 996 28.3 Register Descriptions ...................................................................................................... 1005 28.3.1 Instruction Register (SDIR) ............................................................................... 1007 28.3.2 Data Register H and L (SDDRH, SDDRL) ....................................................... 1007 28.3.3 Interrupt Source Register (SDINT).................................................................... 1008 28.4 Operation ........................................................................................................................ 1009 28.4.1 TAP Control....................................................................................................... 1009 28.4.2 H-UDI Reset ...................................................................................................... 1010 28.4.3 H-UDI Interrupt ................................................................................................. 1010 28.5 Usage Notes .................................................................................................................... 1011
Section 29 A/D Converter (ADC) ..................................................................1013
29.1 Features........................................................................................................................... 1013 29.2 Input/Output Pins ............................................................................................................ 1015 29.3 Register Descriptions ...................................................................................................... 1016 29.3.1 A/D Conversion Data Registers A to D (ADDRA to ADDRD) ........................ 1017 29.3.2 A/D Control/Status Register (ADCSR) ............................................................. 1018 29.4 Operation ........................................................................................................................ 1021 29.4.1 Single Mode....................................................................................................... 1021 29.4.2 Multi Mode ........................................................................................................ 1023 29.4.3 Scan Mode ......................................................................................................... 1025 29.4.4 A/D Conversion Time........................................................................................ 1028 29.4.5 External Trigger Input Timing........................................................................... 1029 29.5 Interrupts......................................................................................................................... 1030 29.6 Definitions of A/D Conversion Accuracy....................................................................... 1030 29.7 Usage Notes .................................................................................................................... 1031 29.7.1 Setting Analog Input Voltage ............................................................................ 1031 29.7.2 Processing of Analog Input Pins........................................................................ 1032 29.7.3 Pck and Clock Division Ratio Settings .............................................................. 1033
Rev. 1.0, 02/03, page xxii of xlviii
29.7.4 Notes on Standby Modes ................................................................................... 1033
Section 30 LCD Controller (LCDC).............................................................. 1035
30.1 Features ........................................................................................................................... 1035 30.2 Input/Output Pins ............................................................................................................ 1036 30.3 Register Configuration .................................................................................................... 1037 30.3.1 LCDC Input Clock Register (LDICKR) ............................................................ 1039 30.3.2 LCDC Module Type Register (LDMTR)........................................................... 1040 30.3.3 LCDC Data Format Register (LDDFR) ............................................................. 1043 30.3.4 LCDC Scan Mode Register (LDSMR) .............................................................. 1045 30.3.5 LCDC Display Start Address Register - Upper (LDSARU) .............................. 1046 30.3.6 LCDC Display Start Address Register - Lower (LDSARL) ............................. 1047 30.3.7 LCDC Display Line Address Offset Register (LDLAOR) ................................ 1048 30.3.8 LCDC Palette Control Register (LDPALCR) .................................................... 1049 30.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) .................................... 1050 30.3.10 LCDC Horizontal Character Number Register (LDHCNR) .............................. 1051 30.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ...................................... 1051 30.3.12 LCDC Vertical Display Line Number Register (LDVDLNR)........................... 1053 30.3.13 LCDC Vertical Total Line Number Register (LDVTLNR) ............................... 1054 30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) .......................................... 1055 30.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR)..... 1056 30.3.16 LCDC Interrupt Control Register (LDINTR) .................................................... 1056 30.3.17 LCDC Power Management Mode Register (LDPMMR)................................... 1058 30.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) ............................. 1060 30.3.19 LCDC Control Register (LDCNTR) .................................................................. 1061 30.4 Operation......................................................................................................................... 1063 30.4.1 Size of LCD Modules Which Can Be Displayed with this LCDC..................... 1063 30.4.2 Limits on the Resolution of Rotated Displays ................................................... 1064 30.4.3 Color Palette Specification................................................................................. 1064 30.4.4 Data Format ....................................................................................................... 1066 30.4.5 Setting the Display Resolution........................................................................... 1069 30.4.6 Power Supply Control Sequence Processing ..................................................... 1069 30.4.7 Operation for Hardware Rotation....................................................................... 1074 30.5 Clock and LCD Data Signal Examples ........................................................................... 1077
Section 31 User Break Controller (UBC) ...................................................... 1089
31.1 Features ........................................................................................................................... 1089 31.2 Register Descriptions ...................................................................................................... 1091 31.2.1 Break Address Register A, B (BARA, BARB).................................................. 1093 31.2.2 Break ASID Register A, B (BASRA, BASRB) ................................................. 1094 31.2.3 Break Address Mask Register A (BAMRA)...................................................... 1095 31.2.4 Break Address Mask Register B (BAMRB) ...................................................... 1096
Rev. 1.0, 02/03, page xxiii of xlviii
31.3
31.4 31.5 31.6 31.7
31.2.5 Break Bus Cycle Register A (BBRA)................................................................ 1097 31.2.6 Break Bus Cycle Register B (BBRB) ................................................................ 1098 31.2.7 Break Data Register B (BDRB) ......................................................................... 1099 31.2.8 Break Data Mask Register B (BDMRB)............................................................ 1099 31.2.9 Break Control Register (BRCR) ........................................................................ 1100 Operation ........................................................................................................................ 1102 31.3.1 Explanation of Terms Relating to Access.......................................................... 1102 31.3.2 Explanation of Terms Instruction Intervals........................................................ 1103 31.3.3 User Break Operation Sequence ........................................................................ 1103 31.3.4 Instruction Access Cycle Break ......................................................................... 1104 31.3.5 Operand Access Cycle Break............................................................................. 1105 31.3.6 Condition Match Flag Setting ............................................................................ 1106 31.3.7 Program Counter (PC) Value Saved .................................................................. 1106 31.3.8 Contiguous A and B Settings for Sequential Conditions ................................... 1107 Usage Notes .................................................................................................................... 1108 User Break Debug Support Function .............................................................................. 1109 Examples of Use ............................................................................................................. 1111 User Break Controller Stop Function.............................................................................. 1113 31.7.1 Transition to User Break Controller Stopped State............................................ 1113 31.7.2 Cancelling the User Break Controller Stopped State ......................................... 1113 31.7.3 Examples of Stopping and Restarting the User Break Controller...................... 1114
Section 32 List of Registers............................................................................1115
32.1 Register Addresses (by functional module, in order of the corresponding section numbers)......................... 1116 32.2 Register Bits.................................................................................................................... 1133 32.3 Register States in Each Operating Mode......................................................................... 1177
Section 33 Electrical Characteristics ..............................................................1195
33.1 Absolute Maximum Ratings ........................................................................................... 1195 33.2 DC Characteristics .......................................................................................................... 1196 33.3 AC Characteristics .......................................................................................................... 1198 33.3.1 Clock and Control Signal Timing ...................................................................... 1199 33.3.2 Control Signal Timing ....................................................................................... 1206 33.3.3 Bus Timing ........................................................................................................ 1208 33.3.4 INTC Module Signal Timing............................................................................. 1241 33.3.5 DMAC Module Signal Timing .......................................................................... 1241 33.3.6 TMU Module Signal Timing ............................................................................. 1242 33.3.7 SCIF Module Signal Timing.............................................................................. 1243 33.3.8 H-UDI Module Signal Timing........................................................................... 1244 33.3.9 CMT Module Signal Timing ............................................................................. 1246 33.3.10 HCAN2 Module Signal Timing......................................................................... 1247
Rev. 1.0, 02/03, page xxiv of xlviii
33.3.11 GPIO Signal Timing .......................................................................................... 1247 2 33.3.12 I C Electrical Characteristics.............................................................................. 1248 33.3.13 HSPI Module Signal Timing.............................................................................. 1251 33.3.14 USB Electrical Characteristics........................................................................... 1252 33.3.15 MFI Electrical Characteristics............................................................................ 1254 33.3.16 SIM Module Signal Timing ............................................................................... 1258 33.3.17 MMCIF Module Signal Timing ......................................................................... 1258 33.3.18 LCDC Module Signal Timing............................................................................ 1260 33.3.19 HAC Interface Module Signal Timing............................................................... 1261 33.3.20 SSI Interface Module Signal Timing ................................................................. 1262 33.4 A/D Converter Characteristics ........................................................................................ 1264 33.5 AC Characteristic Test Conditions.................................................................................. 1265 33.6 Change in Delay Time Based on Load Capacitance ....................................................... 1266
Appendix
A. B. C.
...................................................................................................... 1267
D. E. F. G.
Package Dimensions ....................................................................................................... 1267 Mode Pin Settings ........................................................................................................... 1268 Pin Functions .................................................................................................................. 1270 C.1 Pin States................................................................................................................ 1270 C.2 Handling of Unused Pins ....................................................................................... 1279 Synchronous DRAM Address Multiplexing Tables........................................................ 1280 Instruction Prefetching and Its Side Effects .................................................................... 1291 Power-On and Power-Off Procedures............................................................................. 1292 Version registers ............................................................................................................. 1293
Rev. 1.0, 02/03, page xxv of xlviii
Rev. 1.0, 02/03, page xxvi of xlviii
Figures
Section 1 Overview Figure 1.1 SH7760 Block Diagram ..............................................................................................10 Figure 1.2 SH7760 Pin Arrangement............................................................................................11 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Programming Model Data Formats ...............................................................................................................29 CPU Register Configuration in Each Processing Mode ..............................................32 General Registers ........................................................................................................33 Data Formats in Memory.............................................................................................38 Processing State Transitions........................................................................................39 Floating-Point Unit (FPU) Format of Single-Precision Floating-Point Number....................................................41 Format of Double-Precision Floating-Point Number ..................................................42 Single-Precision NaN Bit Pattern ................................................................................43 Floating-Point Registers ..............................................................................................46 Pipelining Basic Pipelines ............................................................................................................74 Instruction Execution Patterns.....................................................................................75 Examples of Pipelined Execution................................................................................86
Section 6 Memory Management Unit (MMU) Figure 6.1 Role of the MMU ......................................................................................................101 Figure 6.2 Physical Address Space (AT = 0 in MMUCR) .........................................................102 Figure 6.3 P4 Area......................................................................................................................103 Figure 6.4 External Memory Space ............................................................................................104 Figure 6.5 Virtual Address Space (AT = 1 in MMUCR)............................................................106 Figure 6.6 UTLB Configuration .................................................................................................115 Figure 6.7 Relationship between Page Size and Address Format...............................................116 Figure 6.8 ITLB Configuration...................................................................................................118 Figure 6.9 Flowchart of Memory Access Using UTLB..............................................................119 Figure 6.10 Flowchart of Memory Access Using ITLB .............................................................120 Figure 6.11 Operation of LDTLB Instruction.............................................................................122 Figure 6.12 Memory-Mapped ITLB Address Array...................................................................131 Figure 6.13 Memory-Mapped ITLB Data Array 1 .....................................................................132 Figure 6.14 Memory-Mapped ITLB Data Array 2 .....................................................................133 Figure 6.15 Memory-Mapped UTLB Address Array .................................................................134 Figure 6.16 Memory-Mapped UTLB Data Array 1....................................................................135 Figure 6.17 Memory-Mapped UTLB Data Array 2....................................................................136 Section 7 Caches Figure 7.1 Configuration of Operand Cache...............................................................................139
Rev. 1.0, 02/03, page xxvii of xlviii
Figure 7.2 Configuration of Instruction Cache ...........................................................................140 Figure 7.3 Configuration of Write-Back Buffer .........................................................................148 Figure 7.4 Configuration of Write-Through Buffer .................................................................... 148 Figure 7.5 Memory-Mapped IC Address Array..........................................................................152 Figure 7.6 Memory-Mapped IC Data Array ...............................................................................153 Figure 7.7 Memory-Mapped OC Address Array ........................................................................154 Figure 7.8 Memory-Mapped OC Data Array..............................................................................155 Figure 7.9 Memory-Mapped IC Address Array..........................................................................157 Figure 7.10 Memory-Mapped IC Data Array .............................................................................158 Figure 7.11 Memory-Mapped OC Address Array ......................................................................159 Figure 7.12 Memory-Mapped OC Data Array............................................................................160 Figure 7.13 Store Queue Configuration......................................................................................161 Section 8 Exceptions Figure 8.1 Instruction Execution and Exception Handling .........................................................171 Figure 8.2 Example of General Exception Acceptance Order ....................................................172 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Interrupt Controller (INTC) Block Diagram of INTC............................................................................................204 Example of IRL Interrupt Connection.......................................................................218 Interrupt Operation Flowchart ...................................................................................226
Section 10 Bus State Controller (BSC) Figure 10.1 Block Diagram of BSC............................................................................................231 Figure 10.2 Correspondence between Virtual Address Space and Off-chip Memory Space......234 Figure 10.3 Off-chip Memory Space Allocation ........................................................................236 Figure 10.4 Example of RDY Sampling Timing ........................................................................253 Figure 10.5 Write to RTCSR, RTCNT, RTCOR, or RFCR........................................................279 Figure 10.6 Basic Timing of SRAM Interface............................................................................292 Figure 10.7 Example of 32-Bit Data Width SRAM Connection ................................................293 Figure 10.8 Example of 16-Bit Data Width SRAM Connection ................................................294 Figure 10.9 Example of 8-Bit Data Width SRAM Connection ..................................................294 Figure 10.10 SRAM Interface Wait Timing (Software Wait Only)............................................295 Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal) .................296 Figure 10.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting; AnS = 1, AnW = 011, AnH = 10)..........................................................................297 Figure 10.13 DCK, BS2, and CS1 Timing when Reading SRAM Interface (DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3, CSH[1:0] in WCR4 = 10, Three Wait Cycles) ......................................................298 Figure 10.14 DCK, BS2, and CS1 Timing when Writing to SRAM Interface (DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3, CSH[1:0] in WCR4 = 10, Three Wait Cycles) ......................................................299 Figure 10.15 Connection Example of Synchronous DRAM with 32-Bit Data Width (Area 3).................................................................................................................301
Rev. 1.0, 02/03, page xxviii of xlviii
Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26
Basic Timing for Synchronous DRAM Burst Read ..............................................304 Basic Timing for Synchronous DRAM Single Read.............................................305 Basic Timing for Synchronous DRAM Burst Write .............................................306 Basic Timing for Synchronous DRAM Single Write ............................................308 Burst Read Timing ................................................................................................310 Burst Read Timing (RAS Down, Same Row Address) .........................................311 Burst Read Timing (RAS Down, Different Row Addresses) ................................312 Burst Write Timing................................................................................................313 Burst Write Timing (Same Row Address).............................................................314 Burst Write Timing (Different Row Addresses)....................................................315 Burst Read Cycle for Different Bank and Row Address From Preceding Burst Read Cycle ...................................................................................................316 Figure 10.27 Auto-Refresh Operation ........................................................................................318 Figure 10.28 Synchronous DRAM Auto-Refresh Timing ..........................................................318 Figure 10.29 Synchronous DRAM Self-Refresh Timing ...........................................................320 Figure 10.30(1) Synchronous DRAM Mode Write Timing (PALL) ..........................................322 Figure 10.30(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ................323 Figure 10.31 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)......325 Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM ........................................326 Figure 10.33 Burst ROM Basic Access Timing .........................................................................328 Figure 10.34 Burst ROM Wait Access Timing...........................................................................329 Figure 10.35 Burst ROM Wait Access Timing...........................................................................330 Figure 10.36 Example of PCMCIA Interface .............................................................................334 Figure 10.37 Basic Timing for PCMCIA Memory Card Interface .............................................335 Figure 10.38 Wait Timing for PCMCIA Memory Card Interface ..............................................336 Figure 10.39 PCMCIA Space Allocation ...................................................................................337 Figure 10.40 Basic Timing for PCMCIA I/O Card Interface .....................................................338 Figure 10.41 Wait Timing for PCMCIA I/O Card Interface.......................................................339 Figure 10.42 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................340 Figure 10.43 Example of 32-Bit Data Width MPX Connection .................................................341 Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)........342 Figure 10.45 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted) ..343 Figure 10.46 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait).......344 Figure 10.47 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted) 345 Figure 10.48 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)............................................................346 Figure 10.49 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)............................................................346 Figure 10.50 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)............................................................347 Figure 10.51 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)............................................................347
Rev. 1.0, 02/03, page xxix of xlviii
Figure 10.52 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 64-Bit Data Transfer) ..............................................................348 Figure 10.53 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer).................349 Figure 10.54 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 64-Bit Data Transfer) ..............................................................350 Figure 10.55 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer)................351 Figure 10.56 Example of 32-Bit Data Width Byte Control SRAM 352 Figure 10.57 Byte Control SRAM Basic Read Cycle (No Wait)................................................353 Figure 10.58 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ......................354 Figure 10.59 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait)..............................................................355 Figure 10.60 Wait Cycles between Access Cycles .....................................................................357 Figure 10.61 Arbitration Sequence .............................................................................................359 Section 11 Direct Memory Access Controller (DMAC) Figure 11.1 DMAC Block Diagram............................................................................................362 Figure 11.2 DMABRG Block Diagram ......................................................................................363 Figure 11.3 DMAC Transfer Flowchart .....................................................................................405 Figure 11.4 Round Robin Mode .................................................................................................409 Figure 11.5 Example of Changes in Priority Order in Round Robin Mode................................411 Figure 11.6 Data Flow in Single Address Mode.........................................................................412 Figure 11.7 DMA Transfer Timing in Single Address Mode .....................................................413 Figure 11.8 Operation in Dual Address Mode ............................................................................414 Figure 11.9 Example of Transfer Timing in Dual Address Mode ..............................................415 Figure 11.10 Example of DMA Transfer in Cycle Steal Mode ..................................................416 Figure 11.11 Example of DMA Transfer in Burst Mode............................................................416 Figure 11.12 Bus Handling with Two DMAC Channels Operating ...........................................420 Figure 11.13 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Level Detection), DACK (Read Cycle)....423 Figure 11.14 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Bus/DREQ (Level Detection), DACK (Read Cycle)....424 Figure 11.15 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle)..............................................................................................425 Figure 11.16 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....426 Figure 11.17 Dual Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/DREQ (Level Detection), DACK (Read Cycle)..............................................................................................427 Figure 11.18 Dual Address Mode/Burst Modes in DMABRG Mode External Bus External Bus/ DREQ (Level Detection), DACK (Read Cycle)...428
Rev. 1.0, 02/03, page xxx of xlviii
Figure 11.19 Dual Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....429 Figure 11.20 Dual Address Mode/Burst Modes in DMABRG Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....430 Figure 11.21 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection).................................431 Figure 11.22 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection).................................432 Figure 11.23 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Edge Detection)..................................433 Figure 11.24 Single Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Device/ DREQ (Edge Detection)..................................434 Figure 11.25 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection).................................435 Figure 11.26 Single Address Mode/Burst Mode in DMABRG Mode External Bus External Device/ DREQ (Level Detection) ...........................................................436 Figure 11.27 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Edge Detection)..................................437 Figure 11.28 Single Address Mode/Burst Mode in DMABRG Mode External Bus External Device/ DREQ (Edge Detection)..................................438 Figure 11.29 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: 32 bits, SDRAM: row hit write) ...............................439 Figure 11.30 Single Address Mode/Burst Mode in DMABRG Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: 32 bits, SDRAM: row hit write) ...............................440 Figure 11.31 Configuration of DMA for HAC/SSI ....................................................................449 Figure 11.32 Example of HAC DMA Transfer Operation Flow ................................................451 Figure 11.33 Example of SSI DMA Transfer Operation Flow ...................................................452 Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer ...............454 Figure 11.35 HAC/SSI DMA Transfer Operation Flow Using an Interrupt...............................455 Figure 11.36 8-Bit Data Transfer for SSI ...................................................................................457 Figure 11.37 16-Bit Data Transfer for HAC/SSI ........................................................................457 Figure 11.38 Example of LCDC Data Transfer Flow.................................................................458 Figure 11.39 DMA Transfer Flow Shared Memory Synchronous DRAM............................459 Figure 11.40 Bus Arrangement for Data Alignment....................................................................460 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Clock Pulse Generator (CPG) Block Diagram of CPG ...........................................................................................466 Points for Attention when Using Crystal Resonator................................................479 Points for Attention when Using PLL Oscillation Circuit.......................................480
Section 13 Watchdog Timer (WDT) Figure 13.1 Block Diagram of WDT ..........................................................................................481
Rev. 1.0, 02/03, page xxxi of xlviii
Figure 13.2 Writing to WTCNT and WTCSR............................................................................485 Section 14 Power-Down Modes Figure 14.1 STATUS Output in Power-On Reset.......................................................................500 Figure 14.2 STATUS Output in Manual Reset...........................................................................500 Figure 14.3 STATUS Output in Sequence of Software Standby Interrupt ............................501 Figure 14.4 STATUS Output in Sequence of Software Standby Power-On Reset ................501 Figure 14.5 STATUS Output in Sequence of Software Standby Manual Reset ....................502 Figure 14.6 STATUS Output in Sequence of Sleep Interrupt................................................502 Figure 14.7 STATUS Output in Sequence of Sleep Power-On Reset ...................................503 Figure 14.8 STATUS Output in Sequence of Sleep Manual Reset........................................503 Figure 14.9 STATUS Output in Sequence of Deep Sleep Interrupt ......................................504 Figure 14.10 STATUS Output in Sequence of Deep Sleep Power-On Reset ........................504 Figure 14.11 STATUS Output in Sequence of Deep Sleep Manual Reset ............................505 Figure 14.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation) .........506 Figure 14.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation) ............507 Figure 14.14 Timing when Power is Off ....................................................................................507 Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Timer Unit (TMU) Block Diagram of TMU ..........................................................................................510 Example of Count Operation Setting Procedure......................................................517 TCNT Auto-Reload Operation ................................................................................518 Count Timing when Operating on Internal Clock ...................................................518 Count Timing when Operating on External Clock ..................................................519 Operation Timing when Using Input Capture Function ..........................................520
Section 16 Timer/Counter (CMT) Figure 16.1 Block Diagram of CMT...........................................................................................523 Figure 16.2 Edge Detection ........................................................................................................536 Figure 16.3 32-Bit Timer Mode: Input Capture..........................................................................536 Figure 16.4 Output Pin Assertion Period ....................................................................................537 Figure 16.5 32-Bit Timer Mode: Output Compare .....................................................................537 Figure 16.6 16-Bit Timer Mode: Input Capture..........................................................................538 Figure 16.7 16-Bit Timer Mode: Output Compare .....................................................................539 Figure 16.8 Updown-Counter Mode...........................................................................................540 Figure 16.9 Up-Counter Mode....................................................................................................540 Figure 16.10 Up-Counter with Capture Mode ............................................................................541 Figure 16.11 Rotary Mode..........................................................................................................542 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Serial Communication Interface with FIFO (SCIF) Block Diagram of SCIF...........................................................................................545 SCIF_RTS Pin (Only in Channels 1 and 2).............................................................546 SCIF_CTS Pin (Only in Channels 1 and 2).............................................................546 SCIF_CLK Pin ........................................................................................................547 SCIF_TXD Pin ........................................................................................................547
Rev. 1.0, 02/03, page xxxii of xlviii
Figure 17.6 SCIF_RXD Pin........................................................................................................548 Figure 17.7 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits) ...........................................578 Figure 17.8 Sample SCIF Initialization Flowchart .....................................................................581 Figure 17.9 Sample Serial Transmission Flowchart ...................................................................582 Figure 17.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit) ..................................................583 Figure 17.11 Sample Operation Using Modem Control (SCIF_CTS) (Only in Channels 1 and 2)....................................................................................584 Figure 17.12 Sample Serial Reception Flowchart (1) .................................................................585 Figure 17.12 Sample Serial Reception Flowchart (2) .................................................................586 Figure 17.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ..................................................587 Figure 17.14 Sample Operation Using Modem Control (SCIF_RTS) (Only in Channels 1 and 2)...............................................................588 Figure 17.15 Data Format in Clocked Synchronous Communication ........................................588 Figure 17.16 Sample SCIF Initialization Flowchart ...................................................................590 Figure 17.17 Sample Serial Transmission Flowchart .................................................................591 Figure 17.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode ................592 Figure 17.19 Sample Serial Reception Flowchart (1) .................................................................593 Figure 17.19 Sample Serial Reception Flowchart (2) .................................................................594 Figure 17.20 Sample SCIF Reception Operation in Clocked Synchronous Mode .....................594 Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart...................595 Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode ......................................599 Figure 17.23 Example of Synchronization Clock Transfer by DMAC.......................................600 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 Figure 18.5 Figure 18.6 Figure 18.7 Figure 18.8 Figure 18.9 SIM Card Module (SIM) Block Diagram of SIM ............................................................................................602 Data Format Used by the Smart Card Interface.......................................................622 Examples of Initial Character Waveforms ..............................................................624 Example of Initialization Flow ................................................................................626 Example of Transmission Processing......................................................................627 Example of Reception Processing ...........................................................................628 Received Data Sampling Timing in Smart Card Mode ...........................................631 Retransmission in the Smart Card Interface Reception Mode.................................632 Retransmission Standby Mode (clock stopped) when the Smart Card Interface is in Transmission Mode........................................632 Figure 18.10 TEIE Set Timing ...................................................................................................633 Figure 18.11 Procedure for Stopping the Clock and Restarting..................................................634 Figure 18.12 Example of Smart Card Interface Pin Connections ...............................................635 Section 19 Hitachi I2C Interface Figure 19.1 I2C Bus Interface Block Diagram ............................................................................638 Figure 19.2 I2C Bus Timing........................................................................................................663
Rev. 1.0, 02/03, page xxxiii of xlviii
Figure 19.3 Master Data Transmit format ..................................................................................664 Figure 19.4 Master Data Receive format ....................................................................................664 Figure 19.5 Combination Transfer Format of Master Transfer ..................................................665 Figure 19.6 10-Bit Address Data Transfer Format .....................................................................665 Figure 19.7 10-Bit Address Data Receive Format ......................................................................666 Figure 19.8 10-Bit Address Transmit/Receive Combination Format .........................................666 Figure 19.9 Data Transfer Mode Timing Chart ..........................................................................668 Figure 19.10 Data Receive Mode Timing Chart.........................................................................669 Figure 19.11 Operational Example of One-byte Data Transmission ..........................................676 Figure 19.12 Operational Example of Two-byte Data Transmission .........................................677 Figure 19.13 Operational Example of Three-byte Data Transmission .......................................678 Figure 19.14 Operation Example of Four or More Byte Data Transmission..............................678 Section 20 Figure 20.1 Figure 20.2 Figure 20.3 Figure 20.4 Figure 20.5 Figure 20.6 Figure 20.7 Figure 20.8 Serial Sound Interface (SSI) Module Block Diagram of SSI Module ................................................................................682 Philips Format (with no Padding)............................................................................697 Philips Format (with Padding).................................................................................698 Sony Format (with Serial Data First, Followed by Padding Bits) ...........................698 Matsushita Format (with Padding Bits First, Followed by Serial Data) ..................699 Multichannel Format (4 Channels, No Padding) .....................................................701 Multichannel Format (6 Channels with High Padding)...........................................701 Multichannel Format (8 Channels, with Padding Bits First, Followed by Serial Data, with Padding) ......702 Figure 20.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length)...................................702 Figure 20.10 Inverted Clock .......................................................................................................703 Figure 20.11 Inverted Word Select.............................................................................................703 Figure 20.12 Inverted Padding Polarity ......................................................................................703 Figure 20.13 Padding Bits First, Followed by Serial Data, with Delay ......................................704 Figure 20.14 Padding Bits First, Followed by Serial Data, without Delay .................................704 Figure 20.15 Serial Data First, Followed by Padding Bits, without Delay.................................704 Figure 20.16 Parallel Right Aligned with Delay.........................................................................705 Figure 20.17 Mute Enabled ........................................................................................................705 Figure 20.18 Compressed Data Format, Slave Transmitter, Burst Mode Disabled ....................706 Figure 20.19 Compressed Data Format, Slave Transmitter, and Burst Mode Enabled ..............706 Figure 20.20 Transition Diagram between Operation Modes.....................................................708 Figure 20.21 Transmission Using DMA Controller ...................................................................709 Figure 20.22 Transmission using Interrupt Data Flow Control ..................................................710 Figure 20.23 Reception using DMA Controller..........................................................................712 Figure 20.24 Reception using Interrupt Data Flow Control........................................................713 Section 21 USB Host Module (USB) Figure 21.1 Block Diagram of USB Host Module......................................................................716 Figure 21.2 Memory Map of Shared Memory ............................................................................754
Rev. 1.0, 02/03, page xxxiv of xlviii
Figure 21.3 USB Read Operation ...............................................................................................755 Figure 21.4 Example of Transfer Failure....................................................................................755 Figure 21.5 Example of RHSC interrupt handling......................................................................756 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Figure 22.8 Figure 22.9 Section 23 Figure 23.1 Figure 23.2 Figure 23.3 Figure 23.4 Section 25 Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 Figure 25.6 Figure 25.7 Section 26 Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Figure 26.5 Figure 26.6 Figure 26.7 Figure 26.8 Hitachi Controller Area Network 2 (HCAN2) Block Diagram of HCAN2 Module.........................................................................758 HCAN2 Memory Map.............................................................................................761 Mailbox N Structure ................................................................................................764 Acceptance Filter.....................................................................................................769 Reset Sequence........................................................................................................813 Transmission Request..............................................................................................814 Internal Arbitration for Transmission......................................................................815 Message Receive Sequence .....................................................................................817 Changing ID of Receive Box or Changing Receive Box to Transmit Box .............820 Hitachi Serial Protocol Interface (HSPI) Block Diagram of HSPI...........................................................................................824 Operational Flowchart .............................................................................................836 Timing Conditions when FBS = 0...........................................................................838 Timing Conditions when FBS = 1...........................................................................839 Hitachi Audio Codec Interface (HAC) Block Diagram ........................................................................................................882 AC97 Frame Slot Structure .....................................................................................898 Initialization Sequence ............................................................................................902 Sample Flowchart for Off-Chip Codec Register Write ...........................................903 Sample Flowchart for Off-Chip Codec Register Read ............................................904 Sample Flowchart for Off-Chip Codec Register Read (cont)..................................905 Sample Flowchart for Off-Chip Codec Register Read (cont)..................................906 Multimedia Card Interface (MMCIF) Block Diagram of MMCIF ......................................................................................910 DR Access Example ................................................................................................939 Example of Command Sequence for Commands Not Requiring Command Response..................................................................................................................943 Example of Operational Flow for Commands Not Requiring Command Response..................................................................................................................944 Example of Command Sequence for Commands without Data Transfer (No Data Busy State)...............................................................................................945 Example of Command Sequence for Commands without Data Transfer (with Data Busy State) ............................................................................................946 Example of Operational Flow for Commands without Data Transfer.....................947 Example of Command Sequence for Commands with Read Data (Block Size FIFO Size) ........................................................................................949
Rev. 1.0, 02/03, page xxxv of xlviii
Figure 26.9 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size) ......................................................................................950 Figure 26.10 Example of Command Sequence for Commands with Read Data (Multiblock Transfer) ............................................................................................951 Figure 26.11 Example of Command Sequence for Commands with Read Data (Stream Transfer)...................................................................................................952 Figure 26.12 Example of Operational Flow for Commands with Read Data (Single Block Transfer) .........................................................................................953 Figure 26.13 Example of Operational Flow for Commands with Read Data (Multiblock Transfer) ............................................................................................954 Figure 26.14 Example of Operational Flow for Commands with Read Data (Stream Transfer)...................................................................................................955 Figure 26.15 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size) ......................................................................................957 Figure 26.16 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size) ......................................................................................958 Figure 26.17 Example of Command Sequence for Commands with Write Data (Multiblock Transfer) ............................................................................................959 Figure 26.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)...................................................................................................960 Figure 26.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) .........................................................................................961 Figure 26.20 Example of Operational Flow for Commands with Write Data (Multiblock Transfer) ............................................................................................962 Figure 26.21 Example of Operational Flow for Commands with Write Data (Stream Transfer)...................................................................................................963 Figure 26.22 Example of Read Sequence Flow ..........................................................................966 Figure 26.23 Example of Write Sequence Flow .........................................................................967 Section 27 Multifunctional Interface (MFI) Figure 27.1 MFI block diagram ..................................................................................................970 Figure 27.2 Differences in EDN Bit Settings ...............................................................................977 Figure 27.3 Example of MFI Connections..................................................................................985 Figure 27.4 Basic Timing for the MFI 68-Series Interface.........................................................986 Figure 27.5 Basic Timing of the MFI 80-Series Interface ..........................................................987 Figure 27.6 Writing to MFIIDX and Reading from MFIGSR....................................................988 Figure 27.7 MFI Register Settings..............................................................................................988 Figure 27.8 Continuous Data Writing to MFRAM (8-Bit Bus Width, MFISCR.SCRMD2 = 0) ............................................................989 Figure 27.9 Continuous Data Reading from MFRAM (8-Bit Bus Width, MFISCR.SCRMD2 = 0) ............................................................989 Section 28 Hitachi User Debug Interface (H-UDI) Figure 28.1 H-UDI Block Diagram ............................................................................................992
Rev. 1.0, 02/03, page xxxvi of xlviii
Figure 28.2 TAP Controller State Transitions ..........................................................................1009 Figure 28.3 H-UDI Reset..........................................................................................................1010 Section 29 Figure 29.1 Figure 29.2 Figure 29.3 Figure 29.4 Figure 29.5 Figure 29.6 Figure 29.7 Figure 29.8 Figure 29.9 A/D Converter (ADC) A/D Converter Block Diagram..............................................................................1014 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ..........1022 Example of A/D Converter Operation (Multi Mode, Three Channels AN0 to AN2 Selected) .........................................1024 Example of A/D Converter Operation (Scan Mode, Three Channels AN0 to AN2 Selected) ...........................................1026 Timing for Data Write when Four Channels are Selected in Multi Mode.............1027 External Trigger Input Timing ..............................................................................1029 Definitions of A/D Conversion Accuracy .............................................................1031 Example of Analog Input Pin Protection Circuit...................................................1032 Analog Input Pin Equivalent Circuit .....................................................................1032
Section 30 LCD Controller (LCDC) Figure 30.1 LCDC Block Diagram...........................................................................................1036 Figure 30.2 Valid Display and the Retrace Period....................................................................1063 Figure 30.3 Color-Palette Data Format.....................................................................................1065 Figure 30.4 Power-Supply Control Sequence and States of the LCD Module .........................1070 Figure 30.5 Power-Supply Control Sequence and States of the LCD Module .........................1070 Figure 30.6 Power-Supply Control Sequence and States of the LCD Module .........................1071 Figure 30.7 Power-Supply Control Sequence and States of the LCD Module .........................1071 Figure 30.8 Clock and LCD Data Signal Example ...................................................................1077 Figure 30.9 Clock and LCD Data Signal Example ...................................................................1077 Figure 30.10 Clock and LCD Data Signal Example .................................................................1078 Figure 30.11 Clock and LCD Data Signal Example .................................................................1078 Figure 30.12 Clock and LCD Data Signal Example .................................................................1079 Figure 30.13 Clock and LCD Data Signal Example .................................................................1080 Figure 30.14 Clock and LCD Data Signal Example .................................................................1080 Figure 30.15 Clock and LCD Data Signal Example .................................................................1081 Figure 30.16 Clock and LCD Data Signal Example .................................................................1081 Figure 30.17 Clock and LCD Data Signal Example .................................................................1082 Figure 30.18 Clock and LCD Data Signal Example .................................................................1083 Figure 30.19 Clock and LCD Data Signal Example .................................................................1084 Figure 30.20 Clock and LCD Data Signal Example .................................................................1085 Figure 30.21 Clock and LCD Data Signal Example .................................................................1086 Figure 30.22 Clock and LCD Data Signal Example .................................................................1087 Section 31 User Break Controller (UBC) Figure 31.1 Block Diagram of UBC .........................................................................................1090 Figure 31.2 User Break Debug Support Function Flowchart....................................................1110
Rev. 1.0, 02/03, page xxxvii of xlviii
Section 33 Electrical Characteristics Figure 33.1 EXTAL Clock Input Timing .................................................................................1200 Figure 33.2 CKIO Clock Output Timing (1) ............................................................................1201 Figure 33.3 CKIO Clock Output Timing (2) ............................................................................1201 Figure 33.4 DCK Clock Output Timing (1)..............................................................................1201 Figure 33.5 DCK Clock Output Timing (2)..............................................................................1201 Figure 33.6 Power-On Oscillation Settling Time (1)................................................................1202 Figure 33.7 Standby Return Oscillation Settling Time (Return by RESET or MRESET) (1)..1202 Figure 33.8 Power-On Oscillation Settling Time (2)................................................................1203 Figure 33.9 Standby Return Oscillation Settling Time (Return by RESET or MRESET) (2)..1203 Figure 33.10 Standby Return Oscillation Settling Time (Return by NMI)...............................1204 Figure 33.11 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0).................1204 Figure 33.12 PLL Synchronization Settling Time in Case of RESET, MRESET or NMI Interrupt ...............................................................................................................1204 Figure 33.13 PLL Synchronization Settling Time in Case of IRL Interrupt.............................1205 Figure 33.14 MD pins Setup/Hold Timing ...............................................................................1205 Figure 33.15 Control Signal Timing .........................................................................................1206 Figure 33.16 Pin Drive Timing for Standby Mode ...................................................................1207 Figure 33.17 SRAM Bus Cycle: Basic Bus Cycle (No Wait)...................................................1209 Figure 33.18 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)....................................1210 Figure 33.19 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)..1211 Figure 33.20 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1212 Figure 33.21 Burst ROM Bus Cycle (No Wait)........................................................................1213 Figure 33.22 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait ; 2nd/3rd/4th Data: One Internal Wait)..................................................................1214 Figure 33.23 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1215 Figure 33.24 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ......................1216 Figure 33.25 Synchronous DRAN Auto-Precharge Read Bus Cycle: Single (RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011) ...............................................1217 Figure 33.26 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011) ...............................................1218 Figure 33.27 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0]=01, CAS Latency=3) ...............................................................1219 Figure 33.28 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, CAS Latency=3) ...............................................1220 Figure 33.29 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency=3).................................................................................................1221 Figure 33.30 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1222
Rev. 1.0, 02/03, page xxxviii of xlviii
Figure 33.31 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1223 Figure 33.32 Synchronous DRAM Normal Write Bus Cycle: ACT+WRITE Commands, Burst (RCD[1:0]=01, TRWL[2:0]=010)..................1224 Figure 33.33 Synchronous DRAM Normal Write Bus Cycle: PRE+ACT+WRITE Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010) ..............................................1225 Figure 33.34 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0]=010)......................................................1226 Figure 33.35 Synchronous DRAM Bus Cycle: Precharge Command (TPC[2:0]=001) ...........1227 Figure 33.36 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS=1, TRC[2:0]=001) ......1228 Figure 33.37 Synchronous DRAM Bus Cycle: Self-Refresh (TRC[2:0]=001) ........................1229 Figure 33.38 Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) ......................1230 Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET) .........................1231 Figure 33.40 PCMCIA Memory Bus Cycle..............................................................................1232 Figure 33.41 PCMCIA I/O Bus Cycle ......................................................................................1233 Figure 33.42 PCMCIA I/O Bus Cycle (TED=1, TEH=1, One Internal Wait, Bus Sizing).......1234 Figure 33.43 MPX Basic Bus Cycle: Read...............................................................................1235 Figure 33.44 MPX Basic Bus Cycle: Write..............................................................................1236 Figure 33.45 MPX Bus Cycle: Burst Read ...............................................................................1237 Figure 33.46 MPX Bus Cycle: Burst Write ..............................................................................1238 Figure 33.47 Memory Byte Control SRAM Bus Cycle ............................................................1239 Figure 33.48 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1) .......................1240 Figure 33.49 NMI Input Timing ...............................................................................................1241 Figure 33.50 DREQ/DRAK Timing .........................................................................................1242 Figure 33.51 TCLK Input Timing ............................................................................................1242 Figure 33.52 SCIFn_CLK Input Clock Timing ........................................................................1243 Figure 33.53 SCIF I/O Synchronous Mode Clock Timing .......................................................1243 Figure 33.54 TCK Input Timing...............................................................................................1244 Figure 33.55 RESET Hold Timing ...........................................................................................1244 Figure 33.56 H-UDI Data Transfer Timing ..............................................................................1245 Figure 33.57 Pin Break Timing ................................................................................................1245 Figure 33.58 CMT Timing (1) ..................................................................................................1246 Figure 33.59 CMT Timing (2) ..................................................................................................1246 Figure 33.60 HCAN2 Timing ...................................................................................................1247 Figure 33.61 GPIO Timing .......................................................................................................1247 Figure 33.62 Block Diagram of I2C I/O Buffer ........................................................................1248 Figure 33.63 I2C Bus Interface Module Signal Timing ............................................................1250 Figure 33.64 HSPI Data Output/Input Timing..........................................................................1251 Figure 33.65 Input Voltage (VIH, VIL) ......................................................................................1252 Figure 33.66 Output (VOH, VOL) ...............................................................................................1252
Rev. 1.0, 02/03, page xxxix of xlviii
Figure 33.67 Differential Input Sensitivity (VDI), Differential common mode range (VCM) .................................................................................................................1252 Figure 33.68 Load Condition of AC Characteristics (Full speed) ............................................1253 Figure 33.69 Load Condition of AC Characteristics (Low speed) ...........................................1254 Figure 33.70 tr, tf .......................................................................................................................1254 Figure 33.71 VCRS .....................................................................................................................1254 Figure 33.72 AC Characteristics of 68 Series Bus....................................................................1255 Figure 33.73 AC Characteristics of 80 Series Bus (Read)........................................................1256 Figure 33.74 AC Characteristics of 80 Series Bus (Write) .......................................................1257 Figure 33.75 SIM Module Signal Timing.................................................................................1258 Figure 33.76 MMCIF Transmit Timing....................................................................................1259 Figure 33.77 MMCIF Receive Timing (rising edge sampling) ................................................1259 Figure 33.78 MMCIF Receive Timing (falling edge sampling) ...............................................1259 Figure 33.79 LCDC Module Signal Timing .............................................................................1260 Figure 33.80 HAC Cold Reset Timing .....................................................................................1261 Figure 33.81 HAC Cold Reset Timing .....................................................................................1261 Figure 33.82 HAC Clock Input Timing ....................................................................................1261 Figure 33.83 HAC Interface Module Signal Timing ................................................................1262 Figure 33.84 SSI Clock Input/Output Timing ..........................................................................1262 Figure 33.85 SSI Transmit Timing (1)......................................................................................1263 Figure 33.86 SSI Transmit Timing ...........................................................................................1263 Figure 33.87 SSI Receive Timing (1) .......................................................................................1263 Figure 33.88 SSI Receive Timing (2) .......................................................................................1263 Figure 33.89 Output Load Circuit.............................................................................................1265 Figure 33.90 Load Capacitance-Delay Time ............................................................................1266 Appendix Figure E.1 Instruction Prefetch .................................................................................................1261 Figure F.1 Power-On and Power-Off Procedures .....................................................................1262
Rev. 1.0, 02/03, page xl of xlviii
Tables
Section 1 Overview Table 1.1 Pin Configuration........................................................................................................12 Table 1.2 Pin Functions ..............................................................................................................21 Table 1.3 Pin Functions (1).........................................................................................................22 Table 1.3 Pin Functions (2).........................................................................................................23 Table 1.3 Pin Functions (3).........................................................................................................24 Table 1.4 Pin Functions ..............................................................................................................25 Section 2 Programming Model Table 2.1 Initial Register Values.................................................................................................31 Section 3 Floating-Point Unit (FPU) Table 3.1 Floating-Point Number Formats and Parameters ........................................................42 Table 3.2 Floating-Point Ranges.................................................................................................43 Table 3.3 Bit Allocation for FPU Exception Handling ...............................................................48 Section 4 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7 Table 4.8 Table 4.9 Table 4.10 Table 4.11 Table 4.12 Instruction Set Addressing Modes and Effective Addresses ...............................................................57 Notation Used in Instruction List ................................................................................61 Fixed-Point Transfer Instructions ...............................................................................62 Arithmetic Operation Instructions...............................................................................63 Logic Operation Instructions.......................................................................................65 Shift Instructions .........................................................................................................66 Branch Instructions .....................................................................................................67 System Control Instructions........................................................................................68 Floating-Point Single-Precision Instructions ..............................................................70 Floating-Point Double-Precision Instructions .............................................................71 Floating-Point Control Instructions.............................................................................71 Floating-Point Graphics Acceleration Instructions .....................................................72
Section 5 Pipelining Table 5.1 Instruction Groups.......................................................................................................80 Table 5.2 Parallel-Executability..................................................................................................83 Table 5.3 Execution Cycles ........................................................................................................90 Section 6 Memory Management Unit (MMU) Table 6.1 Register Configuration (1) ........................................................................................108 Table 6.1 Register Configuration (2) ........................................................................................109 Section 7 Caches Table 7.1 Cache Features (EMODE = 0) ..................................................................................137 Table 7.2 Cache Features (EMODE = 1) ..................................................................................137 Table 7.3 Store Queue Features ................................................................................................138
Rev. 1.0, 02/03, page xli of xlviii
Table 7.4 Table 7.4
Register Configuration (1) ........................................................................................141 Register Configuration (2) ........................................................................................141
Section 8 Exceptions Table 8.1 Exception Sources and Priorities ..............................................................................167 Table 8.2 Register Configuration (1) ........................................................................................174 Table 8.2 Register Configuration (2) ........................................................................................174 Section 9 Interrupt Controller (INTC) Table 9.1 Pin Configuration......................................................................................................205 Table 9.2 Register Configuration (1) ........................................................................................205 Table 9.2 Register Configuration (2) ........................................................................................206 Table 9.3 Interrupt Request Sources and IPRA to IPRD ..........................................................208 Table 9.4 Interrupt Request Sources and INTPRI00 to INTPRI0C*1 .......................................209 Table 9.5 Interrupt Request Sources and Bit Assignments in Each Register (1) ......................212 Table 9.5 Interrupt Request Sources and Bit Assignments in Each Register (2) ......................213 Table 9.6 IRL3 to IRL0 Pins and Interrupt Levels....................................................................218 Table 9.7 Interrupt Exception Handling Sources and Priority Order ........................................221 Table 9.8 Interrupt Response Time ...........................................................................................228 Section 10 Bus State Controller (BSC) Table 10.1 Pin Configuration..................................................................................................232 Table 10.2 Off-chip Memory Space Map ...............................................................................235 Table 10.3 Correspondence between Off-chip Pins (MD4 and MD3) and Bus Width ...........236 Table 10.4 PCMCIA Interface Features..................................................................................237 Table 10.5 PCMCIA Support Interfaces .................................................................................238 Table 10.6 Register Configuration (1) ....................................................................................241 Table 10.6 Register Configuration (2) ....................................................................................242 Table 10.7 Idle Insertion between Accesses ...........................................................................256 Table 10.8 MPX Interface Setting ..........................................................................................263 Table 10.9 32-Bit Off-chip Device/Big-Endian Access and Data Alignment.........................281 Table 10.10 16-Bit Off-chip Device/Big-Endian Access and Data Alignment.........................282 Table 10.11 8-Bit Off-chip Device/Big-Endian Access and Data Alignment...........................283 Table 10.12 32-Bit Off-Chip Device/Little-Endian Access and Data Alignment.....................284 Table 10.13 16-Bit Off-Chip Device/Little-Endian Access and Data Alignment.....................285 Table 10.14 8-Bit Off-Chip Device/Little-Endian Access and Data Alignment.......................286 Table 10.15 Example of Correspondence between This LSI and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0).........302 Table 10.16 Availability of Pipelined Access for Cycles .........................................................317 Table 10.17 Relationship between Address and CE When Using PCMCIA Interface .............332 Section 11 Direct Memory Access Controller (DMAC) Table 11.1 Pin Configuration..................................................................................................364 Table 11.2 Register Configuration (1) ....................................................................................365
Rev. 1.0, 02/03, page xlii of xlviii
Table 11.2 Register Configuration (2) ....................................................................................368 Table 11.3 External Request 2-Channel Mode (DMS[1:0] in DMAOR = 00) .......................380 Table 11.4 DMABRG Mode (DMS[1:0] in DMAOR = 11)...................................................381 Table 11.5 (1) Data Alignment for Receive Slot Data and External Bus .................................400 Table 11.5 (2) Data Alignment for Transmit Slot Data and External Bus................................400 Table 11.6 Selecting External Request Mode with RS Bits....................................................406 Table 11.7 Supported DMA Transfers....................................................................................412 Table 11.8 Relationship between DMA Transfer Type, Request Mode, and Bus Mode ........417 Table 11.9 (1) External Request Transfer Sources and Destinations in External Request 2-Channel Mode ...................................................................418 Table 11.9 (2) External Request Transfer Sources and Destinations in DMABRG Mode.......419 Table 11.10 DMAC Interrupt-Request Codes...........................................................................444 Table 11.11 (1) Conditions for Transfer between External Memory and External Device with DACK, and Corresponding Register Settings ................445 Table 11.11 (2) Conditions for Transfer between External Memory and External Device with DACK, and Corresponding Register Settings ...............446 Table 11.12 Data Alignment between Peripheral Bus and USB Bridge Bus............................461 Table 11.13 Data Alignment between External Bus and USB Bridge Bus...............................462 Section 12 Clock Pulse Generator (CPG) Table 12.1 Pin Configuration and Function of an Oscillation Circuit.....................................468 Table 12.2 Clock Operating Modes ........................................................................................469 Table 12.3 FRQCR Settings and CPU Clock Frequencies......................................................470 Table 12.4 Register Configuration (1) ....................................................................................471 Table 12.4 Register Configuration (2) ....................................................................................471 Section 13 Watchdog Timer (WDT) Table 13.1 Register Configuration (1) ....................................................................................482 Table 13.1 Register Configuration (2) ....................................................................................482 Section 14 Power-Down Modes Table 14.1 Status in Power-Down Modes...............................................................................490 Table 14.2 Pin Configuration..................................................................................................491 Table 14.3 Register Configuration (1) ....................................................................................491 Table 14.3 Register Configuration (2) ....................................................................................492 Table 14.4 Bit Assignment of CLKSTP00 and CLKSTPCLR00 ...........................................495 Section 15 Timer Unit (TMU) Table 15.1 Pin Configuration..................................................................................................510 Table 15.2 Register Configuration (1) ....................................................................................511 Table 15.2 Register Configuration (2) ....................................................................................512 Table 15.3 TMU Interrupt Sources .........................................................................................520 Section 16 Timer/Counter (CMT) Table 16.1 Pin Configuration..................................................................................................524
Rev. 1.0, 02/03, page xliii of xlviii
Table 16.2 Table 16.2
Register Configuration (1) ....................................................................................524 Register Configuration (2) ....................................................................................525
Section 17 Serial Communication Interface with FIFO (SCIF) Table 17.1 Pin Configuration..................................................................................................548 Table 17.2 Register Configuration (1) ....................................................................................549 Table 17.2 Register Configuration (2) ....................................................................................550 Table 17.3 SCSMR Settings ...................................................................................................567 Table 17.4 SCSMR Settings for Serial Transfer Format Selection.........................................577 Table 17.5 SCSMR and SCSCR Settings for SCIF Clock Source Selection ..........................577 Table 17.6 Serial Transfer Formats (Asynchronous Mode)....................................................579 Table 17.7 SCIF Interrupt Sources..........................................................................................597 Section 18 SIM Card Module (SIM) Table 18.1 Pin Configuration..................................................................................................602 Table 18.2 Register Configuration (1) ....................................................................................603 Table 18.2 Register Configuration (2) ....................................................................................604 Table 18.3 Register Settings for the Smart Card Interface......................................................623 Table 18.4 Example of Bit Rates (bits/s) for SIBRR Settings (Pck = 33.3 MHz, SISMPL = 371)........................................................................625 Table 18.5 Smart Card Interface Interrupt Sources.................................................................629 Section 19 Hitachi I2C Interface Table 19.1 I2C Bus Interface...................................................................................................638 Table 19.2 Register Configuration (1) ....................................................................................639 Table 19.2 Register Configuration (2) ....................................................................................640 Table 19.3 CDF and SCGD Recommended Values................................................................653 Table 19.4 Legend in I2C Bus Data Format ............................................................................664 Section 20 Serial Sound Interface (SSI) Module Table 20.1 Pin Configuration..................................................................................................682 Table 20.2 Register Configuration (1) ....................................................................................683 Table 20.2 Register Configuration (2) ....................................................................................683 Table 20.3 Bus Formats of SSI Module..................................................................................696 Table 20.4 Number of Padding Bits for Each Valid Configuration ........................................700 Section 21 USB Host Module (USB) Table 21.1 Pin Configuration..................................................................................................717 Table 21.2 Register Configuration (1) ....................................................................................718 Table 21.2 Register Configuration (2) ....................................................................................719 Section 22 Hitachi Controller Area Network 2 (HCAN2) Table 22.1 Pin Configuration..................................................................................................760 Table 22.2 Address map..........................................................................................................763 Table 22.3 Settings of Mailbox Functions ..............................................................................768
Rev. 1.0, 02/03, page xliv of xlviii
Table 22.4 Table 22.4 Table 22.5
Register Configuration (1) ....................................................................................770 Register Configuration (2) ....................................................................................774 TSEG1 and TSEG2 Settings .................................................................................789
Section 23 Hitachi Serial Protocol Interface (HSPI) Table 23.1 Pin Configuration..................................................................................................824 Table 23.2 Register Configuration (1) ....................................................................................825 Table 23.2 Register Configuration (2) ....................................................................................825 Section 24 Pin Function Controller (PFC) Table 24.1 Multiplexed Pins Controlled by Port Control Registers........................................841 Table 24.2 Register Configuration (1) ....................................................................................844 Table 24.2 Register Configuration (2) ....................................................................................845 Section 25 Hitachi Audio Codec Interface (HAC) Table 25.1 Pin Configuration..................................................................................................882 Table 25.2 Register Configuration (1) ....................................................................................883 Table 25.2 Register Configuration (2) ....................................................................................884 Table 25.3 AC97 Transmit Frame Structure...........................................................................898 Table 25.4 AC97 Receive Frame Structure ............................................................................899 Section 26 Multimedia Card Interface (MMCIF) Table 26.1 Pin Configuration..................................................................................................910 Table 26.2 Register Configuration (1) ....................................................................................911 Table 26.2 Register Configuration (2) ....................................................................................912 Table 26.3 Correspondence between Commands and Settings of CMDTYR and RSPTYR..917 Table 26.4 CMDR Configuration ...........................................................................................920 Table 26.5 Correspondence between Command Response Byte Number and RSPR.............922 Table 26.6 Card States in which Command Sequence is Halted.............................................925 Table 26.7 MMCIF Interrupt Sources.....................................................................................964 Section 27 Multifunctional Interface (MFI) Table 27.1 Pin Configuration..................................................................................................971 Table 27.2 Register Configuration (1) ....................................................................................972 Table 27.2 Register Configuration (2) ....................................................................................973 Table 27.3 MFI Operations .....................................................................................................984 Table 27.4 Access to MFIIDX and MFIGSR .........................................................................984 Table 27.5 Memory Map ........................................................................................................985 Section 28 Hitachi User Debug Interface (H-UDI) Table 28.1 Pin Configuration..................................................................................................993 Table 28.2 Commands Supported by Boundary-Scan TAP Controller...................................996 Table 28.3 (1) SDBSR Configuration.......................................................................................997 Table 28.3 (2) SDBSR Configuration.......................................................................................998 Table 28.3 (3) SDBSR Configuration.......................................................................................999
Rev. 1.0, 02/03, page xlv of xlviii
Table 28.3 (4) SDBSR Configuration.....................................................................................1000 Table 28.3 (5) SDBSR Configuration.....................................................................................1001 Table 28.3 (6) SDBSR Configuration.....................................................................................1002 Table 28.3 (7) SDBSR Configuration.....................................................................................1003 Table 28.3 (8) SDBSR Configuration.....................................................................................1004 Table 28.3 (9) SDBSR Configuration.....................................................................................1005 Table 28.4 Register Configuration (1) ..................................................................................1005 Table 28.4 Register Configuration (2) ..................................................................................1006 Table 28.4 Register Configuration (3) ..................................................................................1006 Section 29 A/D Converter (ADC) Table 29.1 Pin Configuration................................................................................................1015 Table 29.2 Register Configuration (1) ..................................................................................1016 Table 29.2 Register Configuration (2) ..................................................................................1016 Table 29.3 Analog Input Channels and Corresponding A/D Data Registers ........................1017 Table 29.4 A/D Conversion Time .........................................................................................1028 Table 29.5 Relationship between Clock Division Ratio and Usable Input Clock Frequency............................................................................1033 Section 30 LCD Controller (LCDC) Table 30.1 Pin Configuration................................................................................................1036 Table 30.2 Register Configuration (1) ..................................................................................1037 Table 30.2 Register Configuration (2) ..................................................................................1038 Table 30.3 I/O Clock Frequency and Clock Division Ratio .................................................1040 Table 30.4 Display Resolutions when Using Display Rotation ............................................1064 Table 30.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates.....1072 Table 30.6 LCDC Operating Modes .....................................................................................1073 Table 30.7 LCD Module Power-Supply States .....................................................................1073 Section 31 User Break Controller (UBC) Table 31.1 Register Configuration (1) ..................................................................................1091 Table 31.1 Register Configuration (2) ..................................................................................1092 Section 33 Electrical Characteristics Table 33.1 Absolute Maximum Ratings ...............................................................................1195 Table 33.2 DC Characteristics (Ta=-40 to 85C) .................................................................1196 Table 33.3 Permissible Output Currents ...............................................................................1198 Table 33.4 Clock Timing ......................................................................................................1198 Table 33.5 Clock and Control Signal Timing .......................................................................1199 Table 33.6 Control Signal Timing ........................................................................................1206 Table 33.7 Bus Timing..........................................................................................................1208 Table 33.8 INTC Module Signal Timing ..............................................................................1241 Table 33.9 DMAC Module Signal Timing ...........................................................................1241 Table 33.10 TMU Module Signal Timing ..............................................................................1242
Rev. 1.0, 02/03, page xlvi of xlviii
Table 33.11 Table 33.12 Table 33.13 Table 33.14 Table 33.15 Table 33.16 Table 33.17 Table 33.18 Table 33.19 Table 33.20 Table 33.21 Table 33.22 Table 33.23 Table 33.24 Table 33.25 Table 33.26 Table 33.27 Table 33.28 Table 33.29 Table 33.30 Appendix Table B.1 Table B.2 Table B.3 Table B.4 Table B.5 Table C.1 Table G.1
SCIF Module Signal Timing...............................................................................1243 H-UDI Module Signal Timing ............................................................................1244 CMT Module Signal Timing...............................................................................1246 HCAN2 Module Signal Timing ..........................................................................1247 GPIO Signal Timing ...........................................................................................1247 Truth Table of I2C I/O Buffer .............................................................................1248 I2C DC Characteristics ........................................................................................1248 I2C Bus Interface Module Signal Timing............................................................1249 I2C Schmitt characteristics ..................................................................................1249 HSPI Module Signal Timing...............................................................................1251 USB DC characteristics ......................................................................................1252 USB AC characteristics ......................................................................................1253 AC Characteristics of 68 Series Bus ...................................................................1255 AC Characteristics of 80 Series Bus ...................................................................1256 SIM Module Signal Timing ................................................................................1258 MMCIF Module Signal Timing ..........................................................................1258 LCDC Module Signal Timing.............................................................................1260 HAC Interface Module Signal Timing................................................................1261 SSI Interface Module Signal Timing ..................................................................1262 A/D Converter Characteristics ............................................................................1264 Clock Operating Modes (SH7760)..........................................................................1238 Area 0 Memory Map and Bus Width ......................................................................1238 Endian .....................................................................................................................1239 MFI Mode/LCD Mode............................................................................................1239 Clock Input..............................................................................................................1239 Pin States in Reset, Power-Down State, and Bus-Released State ...........................1240 Register Configuration ............................................................................................1263
Rev. 1.0, 02/03, page xlvii of xlviii
Rev. 1.0, 02/03, page xlviii of xlviii
Section 1 Overview
This LSI is a microcomputer, featuring an LCD controller, USB host, and other peripheral functions. The SuperH RISC engine is a Hitachi-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16-bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set. This LSI features the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. This LSI has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full-associative instruction TLB (translation look aside buffer), and MMU (memory management unit) with 64entry full-associative shared TLB. The sizes of the instruction cache and operand cache are 16 kbytes and 32 kbytes. This LSI also features the bus state controller (BSC) that can connect to synchronous DRAM. Also, because of its on-chip functions, such as an LCD controller, a USB host, timers, and serial communication functions, required for multimedia and OA equipment, this LSI enables a dramatic reduction in system costs. Note: SuperH
TM
is a trademark of Hitachi, Ltd.
Rev. 1.0, 02/03, page 1 of 1294
1.1
Item LSI
Features
Features * * * * * * Operating frequency: 200 MHz Performance: 360MIPS, 1.4 GFLOPS Voltage: 1.5 V (internal), 3.3 V (I/O) Superscalar architecture: Parallel execution of two instructions Packages: 256-pin BGA (Size: 21 x 21 mm, pin pitch: 1.0 mm) External buses: Separate 26-bit address and 32-bit data buses External bus frequency: 67MHz * Choice of MFI mode or LCD mode: MFI mode: 8-/16-bit parallel interface (supports 68-/80-family interface) LCD mode: LCD controller/data output
CPU
* * *
Original Hitachi SuperH architecture 32-bit internal data bus General register file: Sixteen 32-bit general registers (and eight 32-bit shadow registers) Seven 32-bit control registers Four 32-bit system registers
*
RISC-type instruction set (upward-compatible with SuperH Series) Fixed 16-bit instruction length for improved code efficiency Load-store architecture Delayed branch instructions Conditional execution C-based instruction set
* * * * * *
Superscalar architecture (providing simultaneous execution of two instructions) including FPU Instruction execution time: Maximum 2 instructions/cycle Virtual address space: 4 Gbytes (448-Mbyte external memory space) Space identifier ASIDs: 8 bits, 256 virtual address spaces On-chip multiplier 5-stage pipeline
Rev. 1.0, 02/03, page 2 of 1294
Item FPU
Features * * * * * * * * * * * On-chip floating-point coprocessor Supports single-precision (32 bits) and double-precision (64 bits) Supports IEEE754-compliant data types and exceptions Two rounding modes: Round to Nearest and Round to Zero Handling of denormalized numbers: Truncation to zero or interrupt generation for compliance with IEEE754 Floating-point registers: 32 bits x 16 words x 2 banks 32-bit CPU-FPU floating-point communication register (FPUL) Supports FMAC (multiply-and-accumulate) instruction Supports FDIV (divide) and FSQRT (square root) instructions Supports FLDI0/FLDI1 (load constant 0/1) instructions Instruction execution times: Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles (double-precision) Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles (double-precision) Note: FMAC is supported for single-precision only. * 3-D graphics instructions (single-precision only): 4-dimensional vector conversion and matrix operations (FTRV): 4 cycles (pitch), 7 cycles (latency) 4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency) * 5-stage pipeline
Rev. 1.0, 02/03, page 3 of 1294
Item Clock pulse generator (CPG)
Features * * Choice of main clock: 1, 6, or 12 times EXTAL Clock modes: CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock * Power-down modes: Sleep mode Deep sleep mode Standby mode Hardware standby mode Module standby mode * Single-channel watchdog timer 4-Gbyte address space, 256 address space identifiers (8-bit ASIDs) Single virtual mode and multiple virtual memory mode Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte 4-entry fully-associative TLB for instructions 64-entry fully-associative TLB for instructions and operands Supports software-controlled replacement and random-counter replacement algorithm TLB contents can be accessed directly by address mapping * * * * * * *
Memory management unit (MMU)
Rev. 1.0, 02/03, page 4 of 1294
Item Cache memory
Features * Instruction cache (IC) 16-kbyte, 2-way set associative (LRU) 256 entries, 32-byte block length Cache-double-mode (16-kbyte cache) Index mode * Operand cache (OC) 32-kbyte, 2-way set associative (LRU) 512 entries, 32-byte block length Cache-double-mode (32-kbyte cache) Index mode RAM mode (16-kbyte cache + 16-kbyte RAM) Choice of write method (copy-back or write-through) * * * Single-stage copy-back buffer, single-stage write-through buffer Cache memory contents can be accessed directly by address mapping (usable as on-chip memory) Store queue (32 bytes x 2 entries) Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to IRQ4 15-level signed external interrupts: IRL3 to IRL0 On-chip peripheral module interrupts: Priority level can be set for each module Supports debugging by means of user break interrupts Two break channels Address, data value, access type, and data size can all be set as break conditions Supports sequential break function
Interrupt controller (INTC)
* * *
User break controller (UBC)
* * * *
Rev. 1.0, 02/03, page 5 of 1294
Item Bus state controller (BSC)
Features * * Supports external memory access External memory space divided into seven areas, each of up to 64 Mbytes, with the following parameters settable for each area: Bus size (8, 16, or 32 bits) Number of wait cycles (hardware wait function also supported) SRAM, synchronous DRAM, or burst ROM Supports PCMCIA interface (only in little endian mode) * Synchronous DRAM refresh functions: Programmable refresh interval Supports auto refresh mode and self-refresh mode * * Synchronous DRAM burst access function Big endian or little endian mode can be set 8-channel physical address DMA controller Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes Address modes: 1-bus-cycle single address mode 2-bus-cycle dual address mode * * * * Transfer requests: External, peripheral module, or auto-requests Choice of DACK or DRAK (four external pins) Bus modes: Cycle-steal or burst mode Supports on-chip FIFO bridge (16-stage x 32-bit FIFO x 7) to achieve high-speed transfer for HAC/SSI, USB and LCDC 3-channel auto-reload 32-bit timer Input-capture function (only channel 2) Choice of six types counter input clocks (external and peripheral clocks) 4-channel auto-reload 32-bit timers Choice of 16 or 32 bits Choice of 1-shot or free-running operation Choice of an interrupt source or DMA transfer request from compare match or overflow
Direct memory access controller (DMAC)
* * *
Timer unit (TMU)
* * *
Compare match timer (CMT)
* * * *
Rev. 1.0, 02/03, page 6 of 1294
Item Serial communication interface (SCIF)
Features * * * * * Three full-duplex communications channels On-chip 128-byte FIFOs for all channels Choice of asynchronous mode or synchronous mode Can select any bit rate generated by on-chip baud-rate generator On-chip modem control function (SCIF_RTS and SCIF_CTS) for channel 1 and 2 Digital interface for audio codec Supports transfer for slot 1 to slot 4 Choice of 16- or 20-bit DMA transfer Supports various sampling rates by adjusting slot data Generates interrupt: data ready, data request, overflow, and underrun 2-channel bi-directional transfer (maximum) Support multi-channel and compressed-data transfer Selectable frame size 2 channels (maximum) Master/slave 16-byte FIFO Supports high-speed mode (400 kbits/sec) Supports version 1.0 Supports MMC mode A maximum bit rate of 20 Mbps at 20 MHz of peripheral clock Interface with MCCLK output for transfer clock output, MCCMD I/O for command output/response input, MCDAT I/O (data I/O) Four interrupt sources Supports ISO/IEC7816-3 (Identification card) Asynchronous half-duplex transfer (8 bits) Can select any bit rate generated by on-chip baud-rate generator Generates and checks parity bit Four interrupt sources
Hitachi audio codec * interface (HAC) * * * * Serial sound interface (SSI) * * * I C bus interface 2 (I C)
2
* * * * *
Multimedia card interface (MMCIF)
* * * *
Smart card interface * (SIM) * * * *
Rev. 1.0, 02/03, page 7 of 1294
Item Hitachi controller area network 2 (HCAN2)
Features * * 2 channels (maximum) Supports CAN specification 2.0A and 2.0B Standard data and remote frame (11-bit ID) Extended data and remote frame (29-bit ID) * * * * 32 independent message buffers using standard (11-bit) and extended (29-bit) ID format 31 Mailboxes can be used for transmission or reception One Mailbox can be used for only reception Message reception filtering by IDs: Standard message ID Extended message ID * * * * * Local reception filter for reception-only Mailbox (standard and extended message ID) can be specified Power-down sleep mode A maximum of 1-Mbit/s CAN data transfer rate can be specified Transmit message queue having internal priority sorting mechanism which handle priority-inversion issue of real time applications Data buffer access without hand-shaking 1 channel Master/slave mode Selectable bit rate generated by on-chip baud-rate generator 2-kbyte internal memory can be read from or written to via the MFI pin in 32-bit units or by the CPU in 8-/16-/32-bit units. Choice of 8- or 16-bit parallel interface Supports 68-/80-family interface (can be switched during reset) Endians can be switched 1 channel Supports USB version 1.1 and OHCI 1.0 Supports data transfer rate of 1.5 Mbps and 12Mbps On-chip 8-kbyte SRAM as shared memory defined in OHCI specification
Serial peripheral interface (HSPI)
* * * * * * *
Multifunctional interface (MFI)
USB host
* * * *
Rev. 1.0, 02/03, page 8 of 1294
Item LCD controller (LCDC)
Features * * * * * * * Supports 16 x 1 to 1024 x 1024 dots (8 bpp: a maximum of 640 x480 dots, 16 bpp: a maximum of 400 x 240 dots) Supports 4, 8, 15, and 16 bpp color modes Supports 1, 2, 4, and 6 bpp grayscale modes. Supports TFT/DSTN/STN display Selectable signal polarities 24-bit color palette memory (16 bits of 24 bits are valid: R: 5/G: 6/B: 5) Unified graphics memory architecture 10-bit resolution 4-channel input Three types of conversion modes Single mode: 1-channel A/D conversion Multi mode: 1- to 4-channel A/D conversion Scan mode: 1- to 4-channel A/D conversion * * Conversion time: 8 s for are channel (maximum) Absolute error 4LSB 70 general I/O port (69 for I/O and one for output)
A/D converter (ADC) * * *
General I/O (GPIO) *
Rev. 1.0, 02/03, page 9 of 1294
1.2
Block Diagram
CPU
32-bit address (instruction) 32-bit address (instruction)
UBC
FPU
32-bit address (store)
32-bit address (road)
32-bit address (data)
Lower 32-bit data
64-bit data (store) Upper 32-bit data
I cache
ITLB
Cache & TLB controller
UTLB
O cache
HCAN2 SCIF
29-bit address
I2C
32-bit data
CPG
Peripheral data bus
HSPI/SIM/ MMCIF
Peripheral address bus Peripheral data bus
INTC
CMT ADC GPIO MFI MFRAM(2kB) USB
Peripheral address bus
BSC
DMAC
TMU
External (SH) bus interface
26-bit SH bus address 32-bit SH bus data
Address
H-UDI
32-bit data
RAM(8kB) HAC/SSI LCDC
Legend: BSC DMAC FPU UBC ITLB UTLB CPG INTC TMU H-UDI CMT SCIF : Bus state controller : Direct memory access controller : Floating-point unit : User break controller : Instruction translation lookaside buffer : Unit translation lookaside buffer : Clock pulse generator : Interrupt controller : Timer unit : Hitachi user debug interface : Compare match timer : Serial communication interface with FIFO HAC SSI I2C HSPI SIM MMCIF HCAN2 MFI USB LCDC ADC GPIO : Hitachi audio codec interface : Serial sound interface : I2C bus interface : Hitachi serial peripheral interface : Smart card interface : Multimedia card interface : Hitachi controller area network 2 : Multifunctional interface : USB host : LCD controller : A/D converter : General port I/O
Figure 1.1 SH7760 Block Diagram
Rev. 1.0, 02/03, page 10 of 1294
1.3
1 A EXTAL B RESET C RDY D DCK
VCPWC/ E IRQ4 XTAL
Pin Arrangement
2 3 4 5
SSI0_SCK/ HAC_SD_IN0/ BS2
6
7
8
9
10
11
12
13
14
15
16
17
DACK0
18
19
VDD-PLL3 UCLK
20 A B C
VDD-CPG VDD-PLL1
HSPI_TX/ HSPI_CLK/ SIM_CLK/ SIM_D/ MD4/ MCCLK CMT_CTR1 CMT_CTR3 SCIF2_CLK SCIF2_TXD SCIF2_RXD SCIF2_CTS SCIF2_RTS SCIF0_CLK SCIF0_TXD CE2B MCDAT
HSPI_CS/ SIM_RST/ CMT_CTR0/
TCLK
VSS-CPG VDD-PLL2 VSS-PLL1 HAC_ BIT_CLK0 VSS-PLL2 HAC_RES
SSI1_SCK/ SSI1_WS/ HAC_ HAC_ SD_IN1 SYNC1
SSI0_WS/ HAC_SYNC0
HSPI_RX MCCMD
CMT_CTR2 NMI
SCIF1_CLK SCIF1_TXD SCIF1_RXD SCIF1_CTS SCIF1_RTS SCIF0_RXD CE2A
MD3/
VSS-PLL3 USB_DM
VDDQ
SSI0_SDATA/ SSI1_SDATA/ HAC_ HAC_ SD_OUT0 SD_OUT1
VDD
ASEBRK/ BRKACK VDDQ
TMS
VDDQ
TDO
VDDQ
VDD
TCK
MD2
DRAK0
USB_PENC VSSQ
USB_DP
HAC_ BIT_CLK1 MRESET STATUS0 VSS BREQ BACK
STATUS1 VSSQ
TRST
VSSQ
TDI
VSSQ
VSS
VSSQ
MD0
MD1
DRAK1
DACK1
USB_OVC D
VEPWC/ IRQ5
CA
VSSQ
VDDQ
DREQ0
DREQ1
E
F G H J K L M N
MFI-D8/ MFI-D0/ LCD_DATA8 LCD_DATA0 CS0 MFI-D1/ MFI-D9/ LCD_DATA9 LCD_DATA1 VDD
MFI-D2/ MFI-D10/ LCD_DATA2/ LCD_DATA10 IRQ6 MFI-D3/ MFI-D11/ LCD_DATA3/ LCD_DATA11 IRQ7 MFI-D4/ MFI-D12/ LCD_DATA4/ LCD_DATA12 DREQ2 MFI-D5/ MFI-D13/ LCD_DATA5/ LCD_DATA13 DRAK2/DACK2 MFI-D6/ MFI-D14/ LCD_DATA6/ LCD_DATA14 DREQ3
I2C1_SCL I2C1_SDA I2C0_SCL I2C0_SDA F MD6/ IOIS16
Reserved/ AUDCK Reserved/ AUDATA[2]
VSS
VSS
VDD
MD5
Reserved/ AUDSYNC Reserved/ AUDATA[3] Reserved/ AUDATA[1]
G H J K L M N P R T U V W Y 20
VDDQ
VSSQ
MD7
MD8
CS1
CS2
VSSQ
VDDQ
VDDQ
VSSQ
TOP P-LBGA 2121-256
ADTRG/ AVss_ADC AVcc_ADC AUDATA[0]
CS4
A20
AN3
AN2
AN1
AN0
VDDQ
VSSQ
VSSQ
VDDQ
IRL3 IRL1
CAN0_ NERR/ AUDCK
IRL2 IRL0
CAN1_ NERR/ AUDSYNC
MFI-D7/ MFI-D15/ LCD_DATA7/ LCD_DATA15 DRAK3/DACK3 CS5
A21
VSSQ
VDDQ
MFI-INT/ MFI-CS/ P LCD_CLK LCD_DON VDD MFI-E/ MFI-MD/
VSS
VSS
VDD
R LCD_CL1 LCD_CL2 CS6 T
MFI-RW/ MFI-RS/ LCD_M_DISP LCD_FLM BS
A0
A24
A25
CAN0_RX/ CAN1_RX/ AUDATA[2] AUDATA[3] CAN0_TX/ CAN1_TX/ AUDATA[0] AUDATA[1]
A1
A22
A23
U D0 V D1 W D2 Y D13 1
D15
D3
D11
VSSQ
CKE
VSS
VSSQ
A17
VSSQ
VSSQ
VSSQ
A18
VSS
A19
VSSQ
D20
D28
D16
D31
D14
VDDQ
D10
VDDQ
A2
VSSQ
D4
D6
D7
D12
D5
D9
D8
RD/WR RD/ CASS/ FRAME
VDD WE0/ DQM0/ REG WE1/ DQM1
VDDQ
A7
VDDQ
VDDQ
VDDQ
A15
A4
A6
A8
A10
A12
A14
A3
A5
CKIO
A9
A11
A13
VDD WE2/ DQM2/ ICIORD WE3/ DQM3/ ICIOWR
A16
VDDQ
D21
VDDQ
D17
D30
RAS CS3
D24
D25
D27
VSSQ
D29
D23
D22
D26
D19
D18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 1.2 SH7760 Pin Arrangement
Rev. 1.0, 02/03, page 11 of 1294
1.4
Pin Description
Table 1.1 lists the pin configuration of this LSI. In the I/O column, I, O, and IO indicate input, output, and input/output, respectively. In the GPIO column, O indicates a pin which also functions as a general I/O port. Table 1.1
Pin No.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5
Pin Configuration
Pin Name
EXTAL XTAL VDD-CPG VDD-PLL1 SSI0_SCK/HAC_SD_IN0/BS2 HSPI_TX/SIM_D/MCDAT HSPI_CLK/SIM_CLK/MCCLK CMT_CTR1 CMT_CTR3 SCIF2_CLK SCIF2_TXD SCIF2_RXD SCIF2_CTS SCIF2_RTS SCIF0_CLK SCIF0_TXD MD4/CE2B DACK0 VDD-PLL3 UCLK RESET VSS-CPG VDD-PLL2 VSS-PLL1 SSI0_WS/HAC_SYNC0
I/O
I O IO/I/O O/IO/IO IO/O/O IO IO IO O I IO IO IO O IO O I I IO/O
Function
External input clock/crystal resonator Crystal resonator CPG VDD PLL1 VDD SSI serial clock input/HAC serial data/bus start 2 HSPI transmit data/SIM data transfer/MMCIF data HSPI serial clock/SIM clock/MMCIF clock CMT counter CMT counter SCIF serial clock SCIF transmit data SCIF receive data SCIF modem control SCIF modem control SCIF serial clock SCIF transmit data Mode control 4/PCMCIA-CE DMAC0 bus acknowledge PLL3 VDD USB operation clock Reset CPG GND PLL2 VDD PLL1 VSS SSI word selection/HAC from sync output
GPIO
*1 *2
Rev. 1.0, 02/03, page 12 of 1294
Pin No.
B6 B7
Pin Name
HSPI_RX HSPI_CS/SIM_RST/MCCMD
I/O
I IO/O/IO
Function
HSPI receive data input HSPI chip selection/SIM reset/MMCIF command/response
GPIO
B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18
CMT_CTR0/TCLK CMT_CTR2 NMI SCIF1_CLK SCIF1_TXD SCIF1_RXD SCIF1_CTS SCIF1_RTS SCIF0_RXD MD3/CE2A VSS-PLL3 USB_DM VDDQ RDY HAC_BIT_CLK0 VSS-PLL2 HAC_RES SSI0_SDATA/HAC_SD_OUT0 SSI1_SDATA/HAC-SD_OUT1 VDD ASEBRK/BRKACK VDDQ TMS VDDQ TDO VDDQ VDD TCK MD2 DRAK0 USB_PENC
IO/I IO I IO O I IO IO I IO IO I I O IO/O IO/O I/O I O I I O O
CMT counter/TMU clock CMT counter Non-maskerable interrupt SCIF serial clock SCIF transmit data SCIF receive data SCIF modem control SCIF modem control SCIF receive data Mode control 3/PCMCIA-CE PLL3 GND USB D-transceiver USB analog VDD Bus ready HAC serial data clock/SSI divider input clock PLL2 GND HAC reset SSI serial data/HAC serial data SSI serial data/HAC serial data Internal VDD H-UDI emulator I/O VDD H-UDI mode I/O VDD H_UDI data I/O VDD Internal VDD H-UDI clock Mode control 2 DMAC 1 request acknowledgement USB power-on enable control

*2
Rev. 1.0, 02/03, page 13 of 1294
Pin No.
C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1
Pin Name
VSSQ USB_DP DCK SSI1_SCK/HAC_SD_IN1 SSI1_WS/HAC_SYNC1 HAC_BIT_CLK1 MRESET STATUS0 VSS STATUS1 VSSQ TRST VSSQ TDI VSSQ VSS VSSQ MD0 MD1 DRAK1 DACK1 USB_OVC VCPWC/IRQ4
I/O
IO O IO/I IO/O I O O I I I I O O I O/I
Function
USB analog VSS USB D+ transceiver Clock SSI clock/HAC serial data SSI word selection/HAC frame sync output HAC serial data clock/SSI divider input clock Manual reset Status 0 Internal GND Status 1 I/O GND H-UDI reset I/O GND H-UDI data I/O GND Internal GND I/O GND Mode control 0 Mode control 1 DMAC 1 request acknowledgement DMAC 1 bus acknowledgement USB overcurrent detection LCDC panel power supply control (VCC)/external interrupt request 4
GPIO
*3

E2
VEPWC/IRQ5
O/I
LCDC panel power supply control (VEE)/external interrupt request 5
E3 E4 E17 E18 E19 E20 F1 F2
CA BREQ VSSQ VDDQ DREQ0 DREQ1 MFI-D8/LCD_DATA8 MFI-D0/LCD_DATA0
I I I I IO/O IO/O
Chip active Bus request I/O GND I/O VDD DMAC 0 request DMAC 1 request MFI data/LCDC panel data MFI data/LCDC panel data

Rev. 1.0, 02/03, page 14 of 1294
Pin No.
F3 F4 F17 F18 F19 F20 G1 G2 G3 G4 G17 G18 G19 G20 H1 H2
Pin Name
CS0 BACK I2C1_SCL I2C1_SDA I2C0_SCL I2C0_SDA MFI-D9/LCD_DATA9 MFI-D1/LCD_DATA1 VDD VSS VSS VDD MD6/IOIS16 MD5 MFI-D10/LCD_DATA10 MFI-D2/LCD_DATA2/IRQ6
I/O
O O IO IO IO IO IO/O IO/O I/I I IO/O IO/O/I
Function
Chip select 1 Bus acknowledgement I2C serial clock I2C serial data I2C serial clock I2C serial data MFI data/LCDC panel data MFI data/LCDC panel data Internal VDD Internal GND Internal GND Internal VDD Mode control 6/IOIS16 (PCMCIA) Mode control 5 MFI data/LCDC panel data MFI data/LCDC panel data/external interrupt request 6
GPIO

H3 H4 H17 H18 H19 H20 J1 J2
VDDQ VSSQ MD7 MD8 Reserved/AUDCK Reserved/AUDSYNC MFI-D11/LCD_DATA11 MFI-D3/LCD_DATA3/IRQ7
I I O O IO/O IO/O/I
IO VDD IO GND Mode control 7 Mode control 8 Reserved/H-UDI emulator Reserved/H-UDI emulator MFI data/LCDC panel data MFI data/LCDC panel data/external interrupt request 7

J3 J4 J17 J18 J19 J20 K1 K2
CS1 CS2 VSSQ VDDQ Reserved/AUDATA[2] Reserved/AUDATA[3] MFI-D12/LCD_DATA12 MFI-D4/LCD_DATA4/DREQ2
O O O O IO/O IO/O/I
Chip select 1 Chip select 2 IO GND IO VDD Reserved/H-UDI emulator Reserved/H-UDI emulator MFI data/LCDC panel data MFI data/LCDC panel data/DMAC2 request
*2
Rev. 1.0, 02/03, page 15 of 1294
Pin No.
K3 K4 K17 K18 K19 K20 L1 L2
Pin Name
VDDQ VSSQ AVss_ADC AVcc_ADC ADTRG/AUDATA[0] Reserved/AUDATA[1] MFI-D13/LCD_DATA13 MFI-D5/LCD_DATA5/DRAK2/DACK2
I/O
I/O O IO/O
Function
IO VDD IO GND ADC analog GND ADC analog VCC A/D external trigger/H-UDI emulator Reserved/H-UDI emulator MFI data/LCDC panel data
GPIO

IO/O/O/O MFI data/LCDC panel data/DMAC2 request acknowledgement/DMAC2 bus acknowledgement
L3 L4 L17 L18 L19 L20 M1 M2 M3 M4 M17 M18 M19 M20 N1 N2
CS4 A20 AN3 AN2 AN1 AN0 MFI-D14/LCD_DATA14 MFI-D6/LCD_DATA6/DREQ3 VDDQ VSSQ VSSQ VDDQ IRL3 IRL2 MFI-D15/LCD_DATA15 MFI-D7/LCD_DATA7/DRAK3/DACK3
O I I I I IO/O IO/O/I I I IO/O
Chip select 4 Address bus ADC analog input ADC analog input ADC analog input ADC analog input MFI data/LCDC panel data MFI data/LCDC panel data/DMAC3 request IO VDD IO GND IO GND IO VDD IRL interrupt request 3 IRL interrupt request 2 MFI data/LCDC panel data

IO/O/O/O MFI data/LCDC panel data/DMAC3 request acknowledgement/DMAC3 bus acknowledgement
N3 N4 N17 N18 N19 N20 P1 P2
CS5 A21 VSSQ VDDQ IRL1 IRL0 MFI-INT/LCD_CLK MFI-CS/LCD_DON
O O I I O/I I/O
Chip select 5 Address bus IO GND IO VDD IRL interrupt request 1 IRL interrupt request 0 MFI interrupt/LCDC clock MFI chip selection/LCDC display-on signal
*1 *1
Rev. 1.0, 02/03, page 16 of 1294
Pin No.
P3 P4 P17 P18 P19 P20 R1 R2 R3 R4 R17 R18 R19 R20 T1
Pin Name
VDD VSS VSS VDD CAN0_NERR/AUDCK CAN1_NERR/AUDSYNC MFI-E/LCD_CL1 MFI-MD/LCD_CL2 CS6 A0 A24 A25 CAN0_RX/AUDATA[2] CAN1_RX/AUDATA[3] MFI-RS/LCD_M_DISP
I/O
I/O I/O I/O I/O O O O O I/O I/O I/O
Function
Internal VDD Internal GND Internal GND Internal VDD HCAN0 bus error signal/H-UDI emulator HCAN1 bus error signal/H-UDI emulator MFI enable/ LCDC shift clock 1 MFI mode/LCDC shift clock 2 Chip select 6 Address bus Address bus Address bus HCAN0 bus data receive signal/H-UDI emulator HCAN1 bus data receive signal/H-UDI emulator MFI register select/LCDC current-alternating signal/DISP signal
GPIO
*1 *1
*1 *1
T2 T3 T4 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10
MFI-RW/LCD_FLM BS A1 A22 A23 CAN0_TX/AUDATA[0] CAN1_TX/AUDATA[1] D0 D15 D3 D11 VSSQ CKE VSS VSSQ A17 VSSQ
I/O O O O O O/O O/O IO IO IO IO O O
MFI read-write/read/LCDC first line marker Bus start Address bus Address bus Address bus HCAN0 bus data transmit signal/H-UDI emulator HCAN1 bus data transmit signal/H-UDI emulator Data bus Data bus Data bus Data bus IO GND Clock output enable Internal GND IO GND Address bus IO GND

Rev. 1.0, 02/03, page 17 of 1294
Pin No.
U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3
Pin Name
VSSQ VSSQ A18 VSS A19 VSSQ D20 D28 D16 D31 D1 D14 VDDQ D10 VDDQ A2 VDD VDDQ A7 VDDQ VDDQ VDDQ A15 VDD A16 VDDQ D21 VDDQ D17 D30 D2 VSSQ D4
I/O
O O IO IO IO IO IO IO IO O O O O IO IO IO IO IO
Function
IO GND IO GND Address bus Internal GND Address bus IO GND Data bus Data bus Data bus Data bus Data bus Data bus IO VDD Data bus IO VDD Address bus Internal VDD IO VDD Address bus IO VDD IO VDD IO VDD Address bus Internal VDD Address bus IO VDD Data bus IO VDD Data bus Data bus Data bus IO GND Data bus
GPIO
Rev. 1.0, 02/03, page 18 of 1294
Pin No.
W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
Pin Name
D6 D7 RD/WR WE0/DQM0/REG A4 A6 A8 A10 A12 A14 WE2/DQM2/ICIORD RAS D24 D25 D27 VSSQ D29 D13 D12 D5 D9 D8 RD/CASS/FRAME WE1/DQM1 A3 A5 CKIO A9 A11 A13 WE3/DQM3/ICIOWR CS3
I/O
IO IO O O/O O O O O O O O/O O IO IO IO IO IO IO IO IO IO O/O/O O O O O O O O/O O
Function
Data bus Data bus Read/write Selection signal for D7 to D0/REG Address bus Address bus Address bus Address bus Address bus Address bus Selection signal for D23 to D16/ICIORD RAS Data bus Data bus Data bus IO GND Data bus Data bus Data bus Data bus Data bus Data bus Read/CAS/FRAME Selection signal for D15 to D8 Address bus Address bus Clock output Address bus Address bus Address bus Selection signal for D31 to D24/ICIOWR Chip select 3
GPIO
Rev. 1.0, 02/03, page 19 of 1294
Pin No.
Y16 Y17 Y18 Y19 Y20
Pin Name
D23 D22 D26 D19 D18
I/O
IO IO IO IO IO
Function
Data bus Data bus Data bus Data bus Data bus
GPIO
In the I/O column, I, O, IO, and indicate input, output, input/output, and no direction, respectively. Notes: 1. Can be used as a GPIO interrupt pin. 2. Can be used as a GPIO interrupt pin. When an interrupt occurs, this LSI exits standby mode. 3. Only outputs. Legend:
Rev. 1.0, 02/03, page 20 of 1294
1.5
MFI mode (MD7=0) I/O Function Pin Name I/O Function Pin Name GPIO GPIO Setting IP Selection PTE7 PECR[15:14] PTE6 PECR[13:12] PTE5 PECR[11:10] PTE4 PECR[9:8] PTE3 PECR[7:6] PTE2 PECR[5:4] PTC7 PCCR[15:14] PTC6 PCCR[13:12] INTC IRQ7 I I DMAC DRAK2/ DACK2 IO LCD_DATA6 LCD_DATA7 DACK3 IO LCD_DATA8 LCD_DATA9 LCD_DATA10 O LCD_DATA11 O LCD_DATA12 O LCD_DATA13 O LCD_DATA14 O LCD_DATA15 O VCPWC O O O O IO IO IO IO IO IO IO I PTD7 PDCR[15:14] PTD6 PDCR[13:12] PTD5 PDCR[11:10] PTD4 PDCR[9:8] PTD3 PDCR[7:6] PTD2 PDCR[5:4] PTD1 PDCR[3:2] PTD0 PDCR[1:0] PTE1 PECR[3:2] PTE0 PECR[1:0] O DRAK3/ O IO DREQ3 I PTC1 PCCR[3:2] O/O PTC0 PCCR[1:0] DREQ2 IRQ6 I PTC5 PCCR[11:10] PTC4 PCCR[9:8] PTC3 PCCR[7:6] MODSELR[7] MODSELR[6] MODSELR[5] MODSELR[4] DMARCR[22]*1 MODSELR[3] MODSELR[2] DMARCR[23]*2 IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] IPSELR[9] I O O O O O O O O O O I/O O LCD_CLK LCD_DON LCD_CL1 LCD_CL2 LCD_M_DISP O LCD_FLM LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 I I I I I IO IO IO IO IO IO LCDC
LCDC mode (MD7=1)
Other modes
Register
Pin No. Function
Pin Name
Table 1.2
P1
MFI
MFI-INT
P2
MFI-CS
R1
MFI-E
R2
MFI-MD
T1
MFI-RS
T2
MFI-RW
Pin Function
F2
MFI-D0
Pin Functions
G2
MFI-D1
H2
MFI-D2
J2
MFI-D3
K2
MFI-D4
L2
MFI-D5
O/O PTC2 PCCR[5:4]
M2
MFI-D6
N2
MFI-D7
F1
MFI-D8
G1
MFI-D9
H1
MFI-D10
J1
MFI-D11
K1
MFI-D12
L1
MFI-D13
M1
MFI-D14
N1
MFI-D15
E1
INTC
IRQ4
Rev. 1.0, 02/03, page 21 of 1294
E2 I IRQ5 VEPWC Notes: 1. DRAK2/DACK2 can be selected only in DMABRG mode 2. DRAK3/DACK3 can be selected only in DMABRG mode
Register I/O Function 2 Pin Name Pin Name I/O GPIO GPIO Setting IP Selection I/O Function 3 IO IO IO IO I PTF2 PFCR[5:4] PFCR[7:6] PFCR[3:2] PFCR[1:0] IPSELR[15:14] IPSELR[15:14] IPSELR[15:14] IPSELR[13] IPSELR[13] IPSELR[13] PTA4 PACR[9:8] PTA3 PACR[7:6] PTA2 PACR[5:4] PTK7 PKCR[15:14] PTK6 PKCR[13:12] PTK5 PKCR[11:10] PTK4 PKCR[9:8] PTK3 PKCR[7:6] PTK2 PKCR[5:4] IPSELR[13] IPSELR[13] IPSELR[13] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] IPSELR[12] SIM SIM_D MMCIF MCCLK MCCMD IO PTF0 O PTF1 MCDAT IO PTF3 SIM_CLK SIM_RST AUD AUDCK AUDATA[2] AUDATA[0] AUDSYNC AUDATA[3] AUDATA[1] AUDATA[3] AUDATA[2] AUDATA[1] AUDCK AUDSYNC I AUDATA[0] O I I I I IO IO HAC (0) HAC_SD_IN0 HAC_SYNC0 I O BS*1 BS2 O PTB7 PBCR[15:14] PTB6 PBCR[13:12] PTB5 PBCR[11:10] IPSELR[11:10] IPSELR[11:10] IPSELR[11:10] O O O O O O O O O O O O O IO O IO IO I I O I I O
Pin No. Function 1 Pin Name
Table 1.3
F19
I2C (0)
I2C0_SCL
F20
I2C0_SDA
F17
I2C (1)
I2C1_SCL
F18
I2C1_SDA
B6
HSPI
HSPI_RX
A6
HSPI_TX
A7
HSPI_CLK
Pin Functions (1)
B7
HSPI_CS
Rev. 1.0, 02/03, page 22 of 1294
PTA7 PACR[15:14] PTA6 PACR[13:12] PTA5 PACR[11:10]
P19
HCAN2 (0)
CAN0_NERR
R19
CAN0_RX
T19
CAN0_TX
P20
HCAN2 (1)
CAN1_NERR
R20
CAN1_RX
T20
CAN1_TX
J20
Reserved*2
J19
Reserved*2
K20
Reserved*2
H19
Reserved*2
H20
Reserved*2
K19
ADC
ADTRG
L20
ADC (0)
AN0
L19
ADC (1)
AN1
L18
ADC (2)
AN2
L17
ADC (3)
AN3
A5
SSI (0)
SSI_SCK
B5
SSI0_WS
SSI0_SDATA IO C5 HAC_SD_OUT0 O Notes: 1. For details of the BS settings, see MODSELR[1]. 2. Refer to section 24, Pin Function Controller(PFC) for processing of Reserved terminal.
Register I/O Function 2 Pin Name Pin Name PTJ7 PJCR[15:14] PJCR[13:12] PJCR[11:10] PJCR[9:8] PJCR[7:6] PJCR[5:4] IPSELR[11:10] IPSELR[11:10] IPSELR[11:10] PTJ6 HAC (1) HAC_SYNC1 PTJ5 PTJ4 PTJ3 PTJ2 PTB4 PBCR[9:8] PTB3 PBCR[7:6] PTB2 PBCR[5:4] PTB1 PBCR[3:2] PTG7 PGCR[15:14] PTG6 PGCR[13:12] PTG5 PGCR[11:10] PTG4 PGCR[9:8] PTG3 PGCR[7:6] PTG2 PGCR[5:4] PTG1 PGCR[3:2] PTG0 PGCR[1:0] PTH7 PHCR[15:14] PTH6 PFCR[13:12] PTH5 PHCR[11:10] PTH4 PHCR[9:8] PTH3 PHCR[7:6] PTH2 PHCR[5:4] PTH1 PHCR[3:2] PTH0 PHCR[1:0] HAC_SD_IN1 HAC_SD_OUT HAC_BIT_CLK1 TMU TCLK I I O I O GPIO GPIO Setting IP Selection HAC_BIT_CLK0 I I/O Function 3 HAC (0) O IO IO IO IO IO IO IO IO I O IO IO IO I O IO IO IO I O I O I IO IO I/O
Pin No. Function 1 Pin Name
Table 1.3
C2
SSI (0)
HAC_BIT_CLK0 I
C4
HAC (0/1)
HAC_RES
D3
SSI (1)
SSI1_WS
D2
SSI1_SCK
C6
SSI1_DATA
D4
HAC_BIT_CLK1 I
B8
CMT (0)
CMT_CTR0
A8
CMT (1)
CMT_CTR1
Pin Functions (2)
B9
CMT (2)
CMT_CTR2
A9
CMT (3)
CMT_CTR3
A15
SCIF (0)
SCIF0_CLK
B16
SCIF0_RXD
A16
SCIF0_TXD
B11
SCIF (1)
SCIF1_CLK
B14
SCIF1_CTS
B15
SCIF1_RTS
B13
SCIF1_RXD
B12
SCIF1_TXD
A10
SCIF (2)
SCIF2_CLK
A13
SCIF2_CTS
A14
SCIF2_RTS
A12
SCIF2_RXD
A11
SCIF2_TXD
A20
USB
UCLK
C18
USB_PENC
D20
USB_OVC
C20
USB_DP
Rev. 1.0, 02/03, page 23 of 1294
B19
USB_DM
Register I/O Function 2 Pin Name I/O Function 3 Pin Name GPIO GPIO Setting IP Selection I I I O I I I I I I I O O O O I I O PTJ1 PJCR[3] H-UDI BRKACK O I/O
Pin No. Function 1 Pin Name
Table 1.3
C15
H-UDI
TCK
C10
TMS
D12
TDI
C12
TDO
D10
TRST
C8
ASEBRK
B10
INTC
NMI
Pin Functions (3)
N20
IRL0
Rev. 1.0, 02/03, page 24 of 1294
N19
IRL1
M20
IRL2
M19
IRL3
A18
DMAC
DACK0
D19
DACK1
C17
DRAK0
D18
DRAK1
E19
DREQ0
E20
DREQ1
D1
CPG
DCK
Table 1.4
Pin No.
R4 T4 V6 Y8 W8 Y9 W9 V9 W10 Y11 W11 Y12 W12 Y13 W13 V13 V15 U9 U13 U15 L4 N4 T17 T18 R17 R18 U1 V1 W1 U3 W3 Data
Pin Functions
Memory Interface
Function
Address
Pin Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 D0 D1 D2 D3 D4
I/O
O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O
SRAM
SDRAM
PCMCIA
MPX
Remarks
A0 A1 A2 A3 A4
Rev. 1.0, 02/03, page 25 of 1294
Pin No.
Y3 W4 W5 Y5 Y4 V4 U4 Y2 Y1 V2 U2 U19 V19 Y20 Y19 U17 V17 Y17 Y16 W16 W17 Y18 W18 U18 W20 V20 U20 F3 J3 J4 Y15 L3
Memory Interface Function
Data
Pin Name
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O
SRAM
SDRAM
PCMCIA
MPX
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
Remarks
ACCSIZE0 ACCSIZE1 ACCSIZE2
Chip select
CS0 CS1 CS2 CS3 CS4
CS0 CS1 CS2 CS3 CS4 CS2 CS3
CS0 CS1 CS2 CS3 CS4
Rev. 1.0, 02/03, page 26 of 1294
Pin No.
N3 R3 W6 W15 Y6 W7
Memory Interface Function
Chip select
Pin Name
CS5 CS6
I/O
O O O O
SRAM
CS5 CS6 RD/WR
SDRAM
PCMCIA
CE1A CE1B
MPX
CS5 CS6 RD/WR
Remarks
Read/Write RAS Read/CAS/FRAME Selection signal for D7 to D0/REG
RD/WR RAS
RD/WR RAS
RD/CASS/FRAME O WE0/DQM0/REG O
OE WE0
CAS DQM0
OE REG
FRAME
Y7 W14
Selection signal for D15 to D8 WE1/DQM1 Selection signal for D23 to D16/ICIORD
O
WE1 WE2
DQM1 DQM2
WE1 ICIORD
WE2/DQM2/ICIORD O
Y14
Selection signal for D31 to D24/ICIOWR
WE3/DQM3/ICIOWR O
WE3
DQM3
ICIOWR
Y10 U6 D16 D17 C16 B17 A17 G20 G19 H17 H18 B1 D5 C1 T3 E4 F4 E3 D6 D8
Clock output Clock output enable Mode Mode Mode Mode/PCMCIA-CE Mode/PCMCIA-CE Mode Mode/IOIS16 Mode Mode Reset Manual reset Bus ready Bus start Bus request Bus acknowledgement Chip active Status 0 Status 1
CKIO CKE MD0 MD1 MD2 MD3/CE2A MD4/CE2B MD5 MD6/IOIS16 MD7 MD8 RESET MRESET RDY BS BREQ BACK CA STATUS0 STATUS1
O O I I I I/O I/O I I/I I I I I I O I O I O O RDY (BS)
CKIO CKE
CKIO
Reset; MD0 Reset; MD1 Reset; MD2
CE2A CE2B
Reset; MD3 Reset; MD4 Reset; MD5
IOIS16
Reset; MD6 Reset; MD7 Reset; MD8
RESET
RDY (BS) (BS)
RDY (BS)
Rev. 1.0, 02/03, page 27 of 1294
Pin No.
A1
Memory Interface Function
External input clock/crystal resonator
Pin Name
EXTAL
I/O
I
SRAM
SDRAM
PCMCIA
MPX
Remarks
A2
Crystal resonator
XTAL
O
Rev. 1.0, 02/03, page 28 of 1294
Section 2 Programming Model
2.1 Data Formats
The data formats supported in this LSI are shown in figure 2.1.
7 Byte (8 bits) 15 Word (16 bits) 31 Longword (32 bits) 31 30 22 s exp 63 62 51 s exp 0 fraction 0 fraction 0 0 0
Single-precision floating-point (32 bits)
Double-precision floating-point (64 bits)
Figure 2.1 Data Formats
Rev. 0.1, 02/03, page 29 of 1294
2.2
2.2.1
Register Descriptions
Privileged Mode and Banks
Processor Modes: This LSI has two processor modes, user mode and privileged mode. This LSI normally operates in user mode, and switches to privileged mode when an exception occurs or an interrupt is accepted. There are four kinds of registers--general registers, system registers, control registers, and floating-point registers--and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 are accessed by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR), which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR), which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply-and-accumulate registers (MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). Access to these registers does not depend on the processor mode.
Rev. 1.0, 02/03, page 30 of 1294
Floating-Point Registers: There are thirty-two floating-point registers, FR0-FR15 and XF0- XF15. FR0-FR15 and XF0-XF15 can be assigned to either of two banks (FPR0_BANK0- FPR15_BANK0 or FPR0_BANK1-FPR15_BANK1). FR0-FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floatingpoint registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0- XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix XMTRX. Register values after a reset are shown in table 2.1. Table 2.1
Type
Initial Register Values
Registers Initial Value* Undefined
General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Control registers SR
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, I3 to I0 bits = 1111 (H'F), reserved bits = 0, others = undefined
GBR, SSR, SPC, SGR, DBR Undefined VBR System registers MACH, MACL, PR, FPUL PC FPSCR Floating-point registers Note: * FR0 to FR15, XF0 to XF15 H'0000 0000 Undefined H'A000 0000 H'0004 0001 Undefined
Initialized by a power-on reset and manual reset.
The CPU register configuration in each processing mode is shown in figure 2.2. User mode and privileged mode are switched by the processing mode bit (MD) in the status register.
Rev. 0.1, 02/03, page 31 of 1294
31 R0_BANK0*1,*2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR
0
31 R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR
0
31 R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC SGR DBR
0
GBR MACH MACL PR
PC
(a) Register configuration in user mode
R0_BANK0*1,*4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 (b) Register configuration in privileged mode (RB = 1)
R0_BANK1*1,*3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 (c) Register configuration in privileged mode (RB = 0)
Notes: 1. R0 is used as the index register in indexed register-indirect addressing mode and indexed GBR indirect addressing mode. 2. Banked registers 3. Banked registers Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by LDC/STC instructions when the RB bit is cleared to 0. 4. Banked registers Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processing Mode
Rev. 1.0, 02/03, page 32 of 1294
2.2.2
General Registers
Figure 2.3 shows the relationship between the processing modes and general registers. This LSI has twenty-four 32-bit general registers (R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, and R8 to R15). However, only 16 of these can be accessed as general registers R0 to R15 in one processing mode. This LSI has two processing modes, user mode and privileged mode. * R0_BANK0 to R7_BANK0 Allocated to R0 to R7 in user mode (SR.MD = 0) Allocated to R0 to R7 when SR.RB = 0 in privileged mode (SR.MD = 1). * R0_BANK1 to R7_BANK1 Cannot be accessed in user mode. Allocated to R0 to R7 when SR.RB = 1 in privileged mode.
SR.MD = 0 or (SR.MD = 1, SR.RB = 0) R0 R1 R2 R3 R4 R5 R6 R7 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15
R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R8 R9 R10 R11 R12 R13 R14 R15
(SR.MD = 1, SR.RB = 1) R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Note : As the user's R0-R7 are assigned to R0_BANK0-R7_BANK0, and after an exception or interrupt R0-R7 are assigned to R0_BANK1-R7_BANK1, it is not necessary for the interrupt handler to save and restore the user's R0-R7 (R0_BANK0-R7_BANK0). After a reset, the values of R0_BANK0-R7_BANK0, R0_BANK1-R7_BANK1, and R8-R15 are undefined.
Figure 2.3 General Registers
Rev. 0.1, 02/03, page 33 of 1294
2.2.3
Control Registers
The control registers are 32 bits long. They consist of the status register (SR), global base register (GBR), saved status register (SSR), saved program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug base register (DBR). SR and GBR can be accessed in both processing modes, but SSR, SPC, VBR, SGR, and DBR can only be accessed in privileged mode. Status Register (SR):
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 FD 0 R/W 30 MD 1 R/W 14 0 R 29 RB 1 R/W 13 0 R 28 BL 1 R/W 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 M R/W 24 0 R 8 Q R/W 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 S R/W 16 0 R 0 T R/W
IMASK3 IMASK2 IMASK1 IMASK0
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31
Bit Name Initial Value R/W -- 0 R
Description Reserved This bit is always read as 0. The write value should always be 0. Processing Mode Selects the processing mode. 0: User mode (Some instructions cannot be executed and some resources cannot be accessed.) 1: Privileged mode
30
MD
1
R/W
29
RB
1
R/W
Privileged Mode General Register Bank Soecification Bit This bit is set to 1 by an exception or interrupt. 0: R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC/STC instructions 1: R0_BANK1 to R7_BANK1 are accessed as general r can be accessed using LDC/STC instructions
28
BL
1
R/W
Exception/Interrupt Block Bit This bit is set to 1 by a reset, an exception, or an interrupt. While this bit is set to 1, an interrupt request is masked. In this case, this processor enters the reset state when a general exception other than a user break occurs.
Rev. 1.0, 02/03, page 34 of 1294
Bit
Bit Name Initial Value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0. FPU Disable Bit A reset clears this bit to 0. When this bit is set to 1 and an FPU instruction is not in a delay slot, a general FPU disable exception occurs. When this bit is set to 1 and an FPU instruction is in a delay slot, a slot FPU disable exception occurs. (FPU instructions: H'F*** instructions and LDS (.L)/STS(.L) instructions using FPUL/FPSCR)
27 to 16 --
15
FD
0
R/W
14 to 10 --
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. M Bit Q Bit Used by the DIV0S, DIV0U, and DIV1 instructions. Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked. These bits are not modified by an interrupt. Reserved These bits are always read as 0. The write value should always be 0. S Bit Used by the MAC instruction. T Bit Indicates true/false or carry/borrow.
9 8 7 6 5 4 3, 2
M Q IMASK3 IMASK2 IMASK1 IMASK0 --
-- -- 1 1 1 1 All 0
R/W R/W R/W R/W R/W R/W R
1 0
S T
-- --
R/W R/W
Saved Status Register (SSR): The contents of SR are saved to SSR in the event of an exception or interrupt. Saved Program Counter (SPC): The address of an instruction at which an interrupt or exception occurs is saved to SPC. Global Base Register (GBR): GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector Base Register (VBR): VBR is referenced as the branch destination base address in the event of an exception or interrupt.
Rev. 0.1, 02/03, page 35 of 1294
Saved General Register 15 (SGR): The contents of R15 are saved to SGR in the event of an exception or interrupt. Debug Base Register (DBR): When the user break debugging function is enabled (BRCR.UBDE = 1), DBR is referenced as the branch destination address of the user break handler instead of VBR. 2.2.4 System Registers
The system registers are 32 bits long. They consist of two multiply-and-accumulate registers (MACH and MACL), the procedure register (PR), the program counter (PC), the floating-point status/control register (FPSCR), and the floating-point communication register (FPUL). For details on FPSCR and FPUL, see section 3, Floating-Point Unit (FPU). Multiply-and-Accumulate Registers (MACH and MACL): MACH and MACL are used for the added value in a MAC instruction, and to store the operation result of a MAC or MUL instruction. Procedure Register (PR): The return address is stored in PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine return instruction (RTS). Program Counter (PC): PC indicates the address of the instruction currently being executed. 2.2.5 FPU Registers
See section 3, Floating-Point Unit (FPU).
2.3
Memory-Mapped Registers
For details on the control registers mapped to memory, see section 32, List of Registers. The control registers are double-mapped to the following two memory areas. All registers have two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are used as follows. * H'1C00 0000 to H'1FFF FFFF This area must be accessed using the address translation function of the MMU. Setting the page number of this area to the corresponding field of the TLB enables access to a memory-mapped register. The operation of an access to this area without using the address translation function of the MMU is not guaranteed.
Rev. 1.0, 02/03, page 36 of 1294
* H'FC00 0000 to H'FFFF FFFF Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error. Memory-mapped registers can be referenced in user mode by means of access that involves address translation. Note: Do not access addresses to which registers are not mapped in either area. The operation of an access to an address with no register mapped is undefined. Also, memory-mapped registers must be accessed using a fixed data size. The operation of an access using an invalid data size is undefined.
2.4
2.4.1
Data Formats
Data Format in Registers
Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31 Longword 0
2.4.2
Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in an 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being loaded into a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big endian or little endian byte order can be selected for the data format. The endian should be set with the MD5 external pin after a power-on reset. Big endian is selected when the MD5 pin is low, and little endian when high. The endian cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. The data format in memory is shown in figure 2.4.
Rev. 0.1, 02/03, page 37 of 1294
A
31 7 07
A+1
23 07
A+2
15 7 07
A+3
0 0
A + 11 A + 10 A + 9
31 7 23 07 15 07 7 07
A+8
0 0
Address A Byte 0 Byte 1 Byte 2 Byte 3 Address A + 4 Address A + 8
15 0 15
Byte 3 Byte 2 Byte 1 Byte 0 Address A + 8
0 15 0
0
15
Word 0
31
Word 1
0 31
Word 1
Word 0
0
Address A + 4 Address A
Longword
Longword
Big endian
Little endian
Figure 2.4 Data Formats in Memory Note: This LSI does not support endian conversion for the 64-bit data format. Therefore, if double-precision floating-point format (64-bit) access is performed in little endian mode, the upper and lower 32 bits will be reversed.
2.5
Processing States
This LSI has five processing states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The power-on reset state is entered when the RESET pin goes low. The manual reset state is entered when the RESET pin is high and the MRESET pin is low. For more information on resets, see section 8, Exceptions. In the power-on reset state, the internal state of the CPU and the on-chip peripheral module registers are initialized. In the manual reset state, the internal state of the CPU and registers of onchip peripheral modules other than the BSC are initialized. Since the BSC is not initialized in the manual reset state, refreshing operations continue. For details, see register descriptions for each section. Exception-Handling State: This is a transient state during which the CPU's processing state flow is altered by a reset, general exception, or interrupt exception handling source. In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the PC is saved in the SPC, the SR is saved in the SSR, and the R15 is saved in SGR. The CPU branches to the start address of the user-coded exception handling routine found from the sum of the contents of the vector base address and the vector offset. See section 8, Exceptions, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state, the CPU executes program instructions in sequence.
Rev. 1.0, 02/03, page 38 of 1294
Power-Down State: In a power-down state, CPU halts operation and power consumption is reduced. The power-down state is entered by executing a SLEEP instruction. There are three modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details on power-down states, see section 14, Power-Down Modes. Bus-Released State: In this state, the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.5.
From any state when RESET = 0 From any state* when RESET = 1 and MRESET = 0
Power-on reset state RESET = 0
Manual reset state Reset state
RESET = 1
RESET = 1, MRESET = 1
Exception-handling state
Bus request
Bus request clearance Exception interrupt End of exception transition processing Interrupt
Interrupt Bus-released state
Bus request Bus request Bus request clearance
Bus request clearance
Program execution state SLEEP instruction with STBY bit set
SLEEP instruction with STBY bit cleared
Sleep mode
Standby mode Power-down mode
Note :* In the middle of a bus cycle, it does not change in the manual reset state.
Figure 2.5 Processing State Transitions
Rev. 0.1, 02/03, page 39 of 1294
2.6
Processing Modes
There are two processing modes: user mode and privileged mode. The processing mode is determined by the processing mode bit (MD) in the status register (SR). User mode is selected when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset state or exception state is entered, the MD bit is set to 1. When exception handling ends, the MD bit is cleared to 0 and user mode is entered. There are certain registers and bits which can only be accessed in privileged mode.
Rev. 1.0, 02/03, page 40 of 1294
Section 3 Floating-Point Unit (FPU)
3.1 Features
The FPU has the following features. * Conforms to IEEE754 standard * 32 single-precision floating-point registers (can also be referenced as 16 double-precision registers) * Two rounding modes: Round to Nearest and Round to Zero * Two denormalization modes: Flush to Zero and Treat Denormalized Number * Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow, Underflow, and Inexact * Comprehensive instructions: Single-precision, double-precision, graphics support, and system control When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU instruction will cause an FPU disable exception.
3.2
3.2.1
Data Formats
Floating-Point Format
A floating-point number consists of the following three fields: * Sign (s) * Exponent (e) * Fraction (f) This LSI can handle single-precision and double-precision floating-point numbers, using the formats shown in figures 3.1 and 3.2.
31 30 s e 23 22 f 0
Figure 3.1 Format of Single-Precision Floating-Point Number
Rev. 1.0, 02/03, page 41 of 1294
63 62 s e
52 51 f
0
Figure 3.2 Format of Double-Precision Floating-Point Number The exponent is expressed in biased form, as follows:
e = E + bias
The range of unbiased exponent E is Emin - 1 to Emax + 1. The two values Emin - 1 and Emax + 1 are distinguished as follows. Emin - 1 indicates zero (both positive and negative sign) and a denormalized number, and Emax + 1 indicates positive or negative infinity or a non-number (NaN). Table 3.1 shows Emin and Emax values. Table 3.1
Parameter Total bit width Sign bit Exponent field Fraction field Precision Bias Emax Emin
Floating-Point Number Formats and Parameters
Single-Precision 32 bits 1 bit 8 bits 23 bits 24 bits +127 +127 -126 Double-Precision 64 bits 1 bit 11 bits 52 bits 53 bits +1023 +1023 -1022
Floating-point number value v is determined as follows: If E = Emax + 1 and f 0, v is a non-number (NaN) irrespective of sign s s If E = Emax + 1 and f = 0, v = (-1) (infinity) [positive or negative infinity] sE If Emin E Emax , v = (-1) 2 (1.f) [normalized number] s Emin If E = Emin - 1 and f 0, v = (-1) 2 (0.f) [denormalized number] s If E = Emin - 1 and f = 0, v = (-1) 0 [positive or negative zero] Table 3.2 shows the ranges of the various numbers in hexadecimal notation.
Rev. 1.0, 02/03, page 42 of 1294
Table 3.2
Type
Floating-Point Ranges
Single-Precision H'7FFF FFFF to H'7FC0 0000 H'7FBF FFFF to H'7F80 0001 H'7F80 0000 H'7F7F FFFF to H'0080 0000 H'007F FFFF to H'0000 0001 H'0000 0000 H'8000 0000 H'8000 0001 to H'807F FFFF H'8080 0000 to H'FF7F FFFF H'FF80 0000 H'FF80 0001 to H'FFBF FFFF H'FFC0 0000 to H'FFFF FFFF Double-Precision H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 H'7FF7 FFFF FFFF FFFF to H'7FF0 0000 0000 0001 H'7FF0 0000 0000 0000 H'7FEF FFFF FFFF FFFF to H'0010 0000 0000 0000 H'000F FFFF FFFF FFFF to H'0000 0000 0000 0001 H'0000 0000 0000 0000 H'8000 0000 0000 0000 H'8000 0000 0000 0001 to H'800F FFFF FFFF FFFF H'8010 0000 0000 0000 to H'FFEF FFFF FFFF FFFF H'FFF0 0000 0000 0000 H'FFF0 0000 0000 0001 to H'FFF7 FFFF FFFF FFFF H'FFF8 0000 0000 0000 to H'FFFF FFFF FFFF FFFF
Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized number Negative infinity Quiet non-number Signaling non-number
3.2.2
Non-Numbers (NaN)
Figure 3.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case: * Sign bit: Don't care * Exponent field: All bits are 1 * Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN) if the MSB is 0.
31 30 x 11111111 23 22 Nxxxxxxxxxxxxxxxxxxxxxx 0
N = 1:sNaN N = 0:qNaN
Figure 3.3 Single-Precision NaN Bit Pattern
Rev. 1.0, 02/03, page 43 of 1294
An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. * When the EN.V bit in FPSCR is 0, the operation result (output) is a qNaN. * When the EN.V bit in FPSCR is 1, an invalid operation exception will be generated. In this case, the contents of the operation destination register are unchanged. If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit in FPSCR. An exception will not be generated in this case. The qNAN values as operation results are as follows: * Single-precision qNaN: H'7FBF FFFF * Double-precision qNaN: H'7FF7 FFFF FFFF FFFF See the individual instruction descriptions for details of floating-point operations when a nonnumber (NaN) is input. 3.2.3 Denormalized Numbers
For a denormalized number floating-point value, the exponent field is expressed as 0, and the fraction field as a non-zero value. When the DN bit in FPSCR of the FPU is 1, a denormalized number (source operand or operation result) is always flushed to 0 in a floating-point operation that generates a value (an operation other than copy, FNEG, or FABS). When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is processed as it is. See the individual instruction descriptions for details of floating-point operations when a denormalized number is input.
Rev. 1.0, 02/03, page 44 of 1294
3.3
3.3.1
Register Descriptions
Floating-Point Registers
Figure 3.4 shows the floating-point register configuration. There are thirty-two 32-bit floatingpoint registers, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0 to XF15, XD0/2/4/6/8/10/12/14, or XMTRX. 1. Floating-point registers, FPRi_BANKj (32 registers) FPR0_BANK0 to FPR15_BANK0 FPR0_BANK1 to FPR15_BANK1 2. Single-precision floating-point registers, FRi (16 registers) When FPSCR.FR = 0, FR0 to FR15 indicate FPR0_BANK0 to FPR15_BANK0; when FPSCR.FR = 1, FR0 to FR15 indicate FPR0_BANK1 to FPR15_BANK1. 3. Double-precision floating-point registers, DRi (8 registers): A DR register comprises two FR registers. DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7}, DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15} 4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises four FR registers. FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7}, FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15} 5. Single-precision floating-point extended registers, XFi (16 registers) When FPSCR.FR = 0, XF0 to XF15 indicate FPR0_BANK1 to FPR15_BANK1; when FPSCR.FR = 1, XF0 to XF15 indicate FPR0_BANK0 to FPR15_BANK0. 6. Double-precision floating-point extended registers, XDi (8 registers): An XD register comprises two XF registers. XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7}, XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15} 7. Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16 XF registers. XMTRX = XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15
Rev. 1.0, 02/03, page 45 of 1294
FPSCR.FR = 0 FV0 DR0 DR2 FV4 DR4 DR6 FV8 DR8 DR10 FV12 DR12 DR14 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 XMTRX XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BANK0 FPR8_BANK0 FPR9_BANK0 FPR10_BANK0 FPR11_BANK0 FPR12_BANK0 FPR13_BANK0 FPR14_BANK0 FPR15_BANK0 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9
FPSCR.FR = 1 XD0 XD2 XD4 XD6 XD8 XD10 XD12 XD14 XMTRX
XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15
DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14
FV0
FV4
FV8
FV12
Figure 3.4 Floating-Point Registers
Rev. 1.0, 02/03, page 46 of 1294
3.3.2
Floating-Point Status/Control Register (FPSCR)
FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Do not set the SZ and PR bits to 1 simultaneously; this setting is reserved.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 30 0 R 14 29 0 R 13 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 Enable 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 24 0 R 8 23 0 R 7 22 0 R 6 21 FR 0 R/W 5 20 SZ 0 R/W 4 Flag 0 R/W 0 R/W 0 R/W 19 PR 0 R/W 3 18 DN 1 R/W 2 17 16
Cause 0 R/W 1 RM1 0 R/W 0 R/W 0 RM0 1 R/W
Cause 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Floating-Point Register Bank 0: FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1: FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15
31 to 22 --
21
FR
0
R/W
20
SZ
0
R/W
Transfer Size Mode 0: Data size of FMOV instruction is 32-bits 1: Data size of FMOV instruction is a 32-bit register pair (64 bits)
19
PR
0
R/W
Precision Mode 0: Floating-point instructions are executed as single-precision operations 1: Floating-point instructions are executed as double-precision operations (graphics support instructions are undefined)
18
DN
1
R/W
Denormalization Mode 0: Denormalized number is treated as such 1: Denormalized number is treated as zero
Rev. 1.0, 02/03, page 47 of 1294
Bit
Bit Name
Initial Value All 0 All 0 All 0
R/W R/W R/W R/W
Description FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field When an FPU exception occurs, the bits corresponding to the FPU exception cause field and FPU exception flag field are set to 1. Each time an FPU operation instruction is executed, the FPU exception cause field is cleared to 0. The FPU exception flag field remains set to 1 until it is cleared to 0 by software. For bit allocations of each field, see table 3.3. Rounding Mode These bits select the rounding mode. 00: Round to Nearest 01: Round to Zero 10: Reserved 11: Reserved
17 to 12 Cause 11 to 7 6 to 2 Enable Flag
1 0
RM1 RM0
0 1
R/W R/W
Table 3.3
Field Name Cause Enable Flag
Bit Allocation for FPU Exception Handling
FPU Error (E) Bit 17 None Invalid Division Operation (V) by Zero (Z) Bit 16 Bit 11 Bit 6 Bit 15 Bit 10 Bit 5 Overflow Underflow Inexact (O) (U) (I) Bit 14 Bit 9 Bit 4 Bit 13 Bit 8 Bit 3 Bit 12 Bit 7 Bit 2
FPU exception cause field FPU exception enable field
FPU exception flag None field
3.3.3
Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register that is accessed from the CPU side by means of LDS and STS instructions. For example, to convert the integer stored in general register R1 to a single-precision floating-point number, the processing flow is as follows: R1 (LDS instruction) FPUL (single-precision FLOAT instruction) FR1
Rev. 1.0, 02/03, page 48 of 1294
3.4
Rounding
In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC, FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB, or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL. Which of the two rounding methods is to be used is determined by the RM bits in FPSCR. FPSCR.RM[1:0] = 00: Round to Nearest FPSCR.RM[1:0] = 01: Round to Zero Round to Nearest: The operation result is rounded to the nearest expressible value. If there are two nearest expressible values, the one with an LSB of 0 is selected. If the unrounded value is 2 (2 - 2 ) or more, the result will be infinity with the same sign as the unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and 1023 and 53 for double-precision. Round to Zero: The digits below the round bit of the unrounded value are discarded. If the unrounded value is larger than the maximum expressible absolute value, the value will become the maximum expressible absolute value.
Emax -P
3.5
3.5.1
Floating-Point Exceptions
General FPU Disable Exceptions and Slot FPU Disable Exceptions
FPU-related exceptions include general FPU disable exceptions and slot FPU disable exceptions. These exceptions occur if an FPU instruction is executed when the FD bit of SR is set to 1. 3.5.2 FPU Exception Sources
The exception sources are as follows: * FPU error (E): When FPSCR.DN = 0 and a denormalized number is input * Invalid operation (V): In case of an invalid operation, such as NaN input * Division by zero (Z): Division with a zero divisor * Overflow (O): When the operation result overflows * Underflow (U): When the operation result underflows * Inexact exception (I): When overflow, underflow, or rounding occurs
Rev. 1.0, 02/03, page 49 of 1294
The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V, Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled. When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the corresponding bit in the FPU exception flag field remains unchanged. 3.5.3 FPU Exception Handling
FPU exception handling is initiated in the following cases: * FPU error (E): FPSCR.DN = 0 and a denormalized number is input * Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation) * Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor * Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result overflow * Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result underflow * Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation result
Rev. 1.0, 02/03, page 50 of 1294
These possibilities are shown in the individual instruction descriptions. All exception events that originate in the FPU are assigned as the same exception event. The meaning of an exception is determined by software by reading from FPSCR and interpreting the information it contains. If no bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V (in case of FTRV only) are set in the FPU exception enable field, this indicates that an actual exception source is not generated. Also, the destination register is not changed by any FPU exception handling operation. Except for the above, the FPU disables exception handling. In every processing, the bit corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the operation result. * Invalid operation (V): qNaN is generated as the result. * Division by zero (Z): Infinity with the same sign as the unrounded value is generated. * Overflow (O): When rounding mode = RZ, the maximum normalized number, with the same sign as the unrounded value, is generated. When rounding mode = RN, infinity with the same sign as the unrounded value is generated. * Underflow (U): When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value, or zero with the same sign as the unrounded value, is generated. When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated. * Inexact exception (I): An inexact result is generated.
Rev. 1.0, 02/03, page 51 of 1294
3.6
Graphics Support Functions
This LSI supports two kinds of graphics functions: new instructions for geometric operations, and pair single-precision transfer instructions that enable high-speed data transfer. 3.6.1 Geometric Operation Instructions
Geometric operation instructions perform approximate-value computations. To enable high-speed computation with a minimum of hardware, this LSI ignores comparatively small values in the partial computation results of four multiplications. Consequently, the error shown below is produced in the result of the computation:
Maximum error = MAX (individual multiplication result x -MIN (number of multiplier significant digits-1, number of multiplicand significant digits-1) -23 -149 2 ) + MAX (result value x 2 , 2 )
The number of significant digits is 24 for a normalized number and 23 for a denormalized number (number of leading zeros in the fractional part). In a future version of the SH Series, the above error is guaranteed, but the same result is not guaranteed. FIPR FVm, FVn (m, n: 0, 4, 8, 12): This instruction is basically used for the following purposes: * Inner product (m n): This operation is generally used for surface/rear surface determination for polygon surfaces. * Sum of square of elements (m = n): This operation is generally used to find the length of a vector. Since approximate-value computations are performed to enable high-speed computation, the inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1 when an FIPR instruction is executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling will be executed. FTRV XMTRX, FVn (n: 0, 4, 8, 12): This instruction is basically used for the following purposes: * Matrix (4 x 4) vector (4): This operation is generally used for viewpoint changes, angle changes, or movements called vector transformations (4-dimensional). Since affine transformation processing for angle + parallel movement basically requires a 4 x 4 matrix, this LSI supports 4-dimensional operations. * Matrix (4 x 4) x matrix (4 x 4): This operation requires the execution of four FTRV instructions.
Rev. 1.0, 02/03, page 52 of 1294
Since approximate-value computations are performed to enable high-speed computation, the inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1 when an FTRV instruction is executed. Therefore, if the I bit is set in the FPU exception enable field, FPU exception handling will be executed. It is not possible to check all data types in the registers beforehand when executing an FTRV instruction. If the V bit is set in the FPU exception enable field, FPU exception handling will be executed. FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is executed, matrix elements must be set in an array in the background bank. However, to create the actual elements of a translation matrix, it is easier to use registers in the foreground bank. When the LDS instruction is used on FPSCR, this instruction takes four to five cycles in order to maintain the FPU state. With the FRCHG instruction, the FR bit in FPSCR can be changed in one cycle. 3.6.2 Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, this LSI also supports highspeed data transfer instructions. When the SZ bit is 1, this LSI can perform data transfer by means of pair single-precision data transfer instructions. * FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14) * FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15) These instructions enable two single-precision (2 x 32-bit) data items to be transferred; that is, the transfer performance of these instructions is doubled. * FSCHG This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-precision data transfer.
3.7
Notes on programming
When the SZ bit is 1 and big-endian mode is used, FMOV can be used for a double-precision floating-point load or store. In little-endian mode, a double-precision floating-point load or store requires execution of two 32-bit data size operations with the SZ bit in FPSCR cleared to 0.
Rev. 1.0, 02/03, page 53 of 1294
Rev. 1.0, 02/03, page 54 of 1294
Section 4 Instruction Set
4.1 Execution Environment
PC: At the start of instruction execution, the PC indicates the address of the instruction itself. * Data sizes and data types This LSI's instruction set is implemented with 16-bit fixed-length instructions. This LSI can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to and from memory using longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and from memory using longword size. When a double-precision floating-point operation is specified (PR in FPSCR = 1), the result of an operation using quadword access will be undefined. When this LSI moves byte-size or word-size data from memory to a register, the data is sign-extended. Load-Store Architecture: This LSI has a load-store architecture in which operations are basically executed using registers. Except for bit-manipulation operations such as logical AND that are executed directly in memory, operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers. Delayed Branches: Except for the two branch instructions BF and BT, this LSI's branch instructions and RTE are delayed branches. In a delayed branch, the instruction following the branch is executed before the branch destination instruction. This execution slot following a delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:
Static Sequence BRA TARGET Dynamic Sequence BRA TARGET ADD R1, R0 target_instr ADD in delay slot is executed before branching to TARGET
ADD R1, R0 next_2
Delay Slot: A slot illegal instruction exception may occur when a specific instruction is executed in a delay slot. For details, see section 8, Exceptions. The instruction following BF/S or BT/S for which the branch is not taken is also a delay slot instruction. T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a conditional branch instruction. An example of the use of a conditional branch instruction is shown below. ADD #1, R0 CMP/EQ R1, R0 BT TARGET ; T bit is not changed by ADD operation ; If R0 = R1, T bit is set to 1 ; Branches to TARGET if T bit = 1 (R0 = R1)
Rev. 1.0, 02/03, page 55 of 1294
In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is used before modification, and in data access, the MD bit is accessed after modification. The other bits--S, T, M, Q, FD, BL, and RB--after modification are used for delay slot instruction execution. The STC and STC.L SR instructions access all SR bits after modification. Constant Values: An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in memory, and can be referenced by a PC-relative load instruction. MOV.W @(disp, PC), Rn MOV.L @(disp, PC), Rn There are no PC-relative load instructions for floating-point operations. However, it is possible to set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point register.
Rev. 1.0, 02/03, page 56 of 1294
4.2
Addressing Modes
Addressing modes and effective address calculation methods are shown in table 4.1. When a location in virtual memory space is accessed (AT in MMUCR = 1), the effective address is translated into a physical memory address. If multiple virtual memory space systems are selected (SV in MMUCR = 0), the least significant bit of PTEH is also referenced as the access ASID. For details, see section 6, Memory Management Unit (MMU). Table 4.1 Addressing Modes and Effective Addresses
Effective Address Calculation Method Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Calculation Formula -- Rn EA (EA: effective address) Rn EA After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Quadword: Rn + 8 Rn Register indirect with predecrement @-Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn - 1/2/4/8 1/2/4/8 - Rn - 1/2/4/8 Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn Quadword: Rn - 8 Rn Rn EA (Instruction executed with Rn after calculation)
Addressing Instruction Mode Format Register direct Register indirect Register indirect with postincrement Rn @Rn
Rn
@Rn+
Rn
Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand, 8 for a quadword operand. Rn Rn + 1/2/4/8 1/2/4/8 + Rn
Rev. 1.0, 02/03, page 57 of 1294
Addressing Mode
Instruction Format
Effective Address Calculation Method Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4
Calculation Formula Byte: Rn + disp EA Word: Rn + disp x 2 EA Longword: Rn + disp x 4 EA
@(disp:4, Rn) Register indirect with displacement
Indexed register indirect
@(R0, Rn)
Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0
Rn + R0 EA
GBR indirect @(disp:8, GBR) Effective address is register GBR contents with with 8-bit displacement disp added. After disp is displacement zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size.
GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4
Byte: GBR + disp EA Word: GBR + disp x 2 EA Longword: GBR + disp x 4 EA
Indexed @(R0, GBR) GBR indirect
Effective address is sum of register GBR and R0 GBR + R0 contents. EA GBR + R0 GBR + R0
Rev. 1.0, 02/03, page 58 of 1294
Addressing Mode
Instruction Format
Effective Address Calculation Method
Calculation Formula Word: PC + 4 + disp x 2 EA Longword: PC & H'FFFF FFFC + 4 + disp x 4 EA
@(disp:8, PC) Effective address is PC + 4 with 8-bit displacement PC-relative disp added. After disp is zero-extended, it is with multiplied by 2 (word), or 4 (longword), according displacement to the operand size. With a longword operand, the lower 2 bits of PC are masked.
PC &* H'FFFF FFFC 4 + disp (zero-extended) x 2/4 * With longword operand + PC + 4 + disp x2 or PC & H'FFFF FFFC + 4 + disp x 4
PC-relative
disp:8
Effective address is PC + 4 with 8-bit displacement PC + 4 + disp disp added after being sign-extended and x2 multiplied by 2. BranchTarget PC
+ 4 + disp (sign-extended) x 2 PC + 4 + disp x 2
Rev. 1.0, 02/03, page 59 of 1294
Addressing Instruction Mode Format PC-relative disp:12
Effective Address Calculation Method
Calculation Formula
Effective address is PC + 4 with 12-bit PC + 4 + disp displacement disp added after being sign-extended x 2 Branchand Target multiplied by 2.
PC + 4 + disp (sign-extended) x 2 PC + 4 + disp x 2
Rn
Effective address is sum of PC + 4 and Rn. PC + 4 Rn + PC + 4 + Rn
PC + 4 + Rn BranchTarget
Immediate
#imm:8 #imm:8 #imm:8
8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.
-- -- --
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, GBR) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative
Rev. 1.0, 02/03, page 60 of 1294
4.3
Instruction Set
Table 4.2 shows the notation used in the SH instruction lists shown in tables 4.3 to 4.12. Table 4.2
Item Instruction mnemonic
Notation Used in Instruction List
Format OP.Sz SRC, DEST Description OP: Sz: SRC: DEST: , (xx) M/Q/T & | Operation code Size Source operand Source and/or destination operand
Summary of operation
Transfer direction Memory operand SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive-OR of individual bits ~ Logical NOT of individual bits <>n n-bit shift Register number (Rm, FRm) Register number (Rn, FRn) R0, FR0 R1, FR1 R15, FR15 Register number (DRm, XDm, Rm_BANK) Register number (DRm, XDm, Rn_BANK) DR0, XD0, R0_BANK DR2, XD2, R1_BANK DR14, XD14, R7_BANK Register number (FVm) Register number (FVn) FV0 FV4 FV8 FV12 Immediate data Displacement
Instruction code
MSB LSB
mmmm: nnnn: 0000: 0001: : 1111: mmm: nnn: 000: 001: : 111: mm: nn: 00: 01: 10: 11: iiii: dddd:
Privileged mode T bit
"Privileged" means the instruction can only be executed in privileged mode. Value of T bit after --: No change instruction execution
Note: Scaling (x1, x2, x4, or x8) is executed according to the size of the instruction operand.
Rev. 1.0, 02/03, page 61 of 1294
Table 4.3
Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L
Fixed-Point Transfer Instructions
Operation #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn imm sign extension Rn (disp x 2 + PC + 4) sign extension Rn Instruction Code 1110nnnniiiiiiii 1001nnnndddddddd Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
(disp x 4 + PC & H'FFFF FFFC 1101nnnndddddddd + 4) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) sign extension Rn (Rm) sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) sign extension Rn, Rm + 1 Rm (Rm) sign extension Rn, Rm + 2 Rm (Rm) Rn, Rm + 4 Rm R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) sign extension R0 (disp x 2 + Rm) sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) sign extension Rn (R0 + Rm) sign extension Rn (R0 + Rm) Rn 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 0110nnnnmmmm0001 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 0110nnnnmmmm0101 0110nnnnmmmm0110 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd 0101nnnnmmmmdddd 0000nnnnmmmm0100 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 0000nnnnmmmm1110
Rev. 1.0, 02/03, page 62 of 1294
Instruction MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT SWAP.B SWAP.W XTRCT R0,@(disp,GBR) R0,@(disp,GBR) R0,@(disp,GBR) @(disp,GBR),R0 @(disp,GBR),R0 @(disp,GBR),R0 @(disp,PC),R0 Rn Rm,Rn Rm,Rn Rm,Rn
Operation R0 (disp + GBR) R0 (disp x 2 + GBR) R0 (disp x 4 + GBR) (disp + GBR) sign extension R0 (disp x 2 + GBR) sign extension R0 (disp x 4 + GBR) R0 disp x 4 + PC & H'FFFF FFFC + 4 R0 T Rn Rm swap lower 2 bytes Rn Rm swap upper/lower words Rn Rm:Rn middle 32 bits Rn
Instruction Code 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd 11000101dddddddd 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 0010nnnnmmmm1101
Privileged -- -- -- -- -- -- -- -- -- -- --
T Bit -- -- -- -- -- -- -- -- -- -- --
Table 4.4
Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS
Arithmetic Operation Instructions
Operation Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, carry T Rn + Rm Rn, overflow T When R0 = imm, 1 T Otherwise, 0 T When Rn = Rm, 1 T Otherwise, 0 T When Rn Rm (unsigned), 1T Otherwise, 0 T Instruction Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 0011nnnnmmmm1111 10001000iiiiiiii 0011nnnnmmmm0000 0011nnnnmmmm0010 Privileged -- -- -- -- -- -- -- T Bit -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result
CMP/GE CMP/HI
Rm,Rn Rm,Rn
When Rn Rm (signed), 1 T 0011nnnnmmmm0011 Otherwise, 0 T When Rn > Rm (unsigned), 1T Otherwise, 0 T 0011nnnnmmmm0110
-- --
CMP/GT CMP/PZ CMP/PL
Rm,Rn Rn Rn
When Rn > Rm (signed), 1 T 0011nnnnmmmm0111 Otherwise, 0 T When Rn 0, 1 T Otherwise, 0 T When Rn > 0, 1 T Otherwise, 0 T 0100nnnn00010001 0100nnnn00010101
-- -- --
Rev. 1.0, 02/03, page 63 of 1294
Instruction CMP/STR Rm,Rn
Operation When any bytes are equal, 1T Otherwise, 0 T 1-step division (Rn / Rm) MSB of Rn Q, MSB of Rm M, M^Q T 0 M/Q/T Rm,Rn Signed, Rn x Rm MAC, 32 x 32 64 bits Unsigned, Rn x Rm MAC, 32 x 32 64 bits Rn - 1 Rn; when Rn = 0, 1T When Rn 0, 0 T Rm sign-extended from byte Rn Rm sign-extended from word Rn Rm zero-extended from byte Rn Rm zero-extended from word Rn
Instruction Code 0010nnnnmmmm1100
Privileged --
T Bit Comparison result Calculation result Calculation result 0 -- -- Comparison result -- -- -- -- --
DIV1 DIV0S DIV0U DMULS.L
Rm,Rn Rm,Rn
0011nnnnmmmm0100 0010nnnnmmmm0111 0000000000011001 0011nnnnmmmm1101 0011nnnnmmmm0101 0100nnnn00010000
-- -- -- -- -- --
DMULU.L Rm,Rn DT Rn
EXTS.B EXTS.W EXTU.B EXTU.W MAC.L
Rm,Rn Rm,Rn Rm,Rn Rm,Rn
0110nnnnmmmm1110 0110nnnnmmmm1111 0110nnnnmmmm1100 0110nnnnmmmm1101 0000nnnnmmmm1111
-- -- -- -- --
@Rm+,@Rn+ Signed, (Rn) x (Rm) + MAC MAC Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits @Rm+,@Rn+ Signed, (Rn) x (Rm) + MAC MAC Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn x Rm MACL 32 x 32 32 bits Signed, Rn x Rm MACL 16 x 16 32 bits Unsigned, Rn x Rm MACL 16 x 16 32 bits 0 - Rm Rn 0 - Rm - T Rn, borrow T Rn - Rm Rn
MAC.W
0100nnnnmmmm1111
--
--
MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV
0000nnnnmmmm0111 0010nnnnmmmm1111 0010nnnnmmmm1110 0110nnnnmmmm1011 0110nnnnmmmm1010 0011nnnnmmmm1000
-- -- -- -- -- -- -- --
-- -- -- -- Borrow -- Borrow Underflow
Rn - Rm - T Rn, borrow T 0011nnnnmmmm1010 Rn - Rm Rn, underflow T 0011nnnnmmmm1011
Rev. 1.0, 02/03, page 64 of 1294
Table 4.5
Instruction AND AND
Logic Operation Instructions
Operation Rn & Rm Rn R0 & imm R0 Instruction Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii Privileged -- -- -- -- -- -- -- -- Test result T Bit -- -- -- -- -- --
Rm,Rn #imm,R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm (R0 + GBR) NOT OR OR OR.B TAS.B Rm,Rn Rm,Rn #imm,R0 ~Rm Rn Rn | Rm Rn R0 | imm R0
#imm,@(R0,GBR) (R0 + GBR) | imm (R0 + GBR)11001111iiiiiiii @Rn When (Rn) = 0, 1 T 0100nnnn00011011 Otherwise, 0 T In both cases, 1 MSB of (Rn) Rn & Rm; when result = 0, 1T Otherwise, 0 T R0 & imm; when result = 0, 1T Otherwise, 0 T 0010nnnnmmmm1000
TST
Rm,Rn
--
Test result
TST
#imm,R0
11001000iiiiiiii
--
Test result
TST.B
#imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii = 0, 1 T Otherwise, 0 T Rm,Rn #imm,R0 Rn Rm Rn R0 imm R0 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii
--
Test result
XOR XOR
-- -- --
-- -- --
XOR.B #imm,@(R0,GBR) (R0 + GBR) imm (R0 + GBR)
Rev. 1.0, 02/03, page 65 of 1294
Table 4.6
Instruction ROTL ROTR ROTCL ROTCR SHAD
Shift Instructions
Operation Rn Rn Rn Rn Rm,Rn T Rn MSB LSB Rn T T Rn T T Rn T Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 Privileged -- -- -- -- -- T Bit MSB LSB MSB LSB --
When Rm 0, Rn << Rm Rn 0100nnnnmmmm1100 When Rm < 0, Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T 0100nnnn00100000 0100nnnn00100001
SHAL SHAR SHLD
Rn Rn Rm,Rn
-- -- --
MSB LSB --
When Rm 0, Rn << Rm Rn 0100nnnnmmmm1101 When Rm < 0, Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001
SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 SHLL16 SHLR16
Rn Rn Rn Rn Rn Rn Rn Rn
-- -- -- -- -- -- -- --
MSB LSB -- -- -- -- -- --
Rev. 1.0, 02/03, page 66 of 1294
Table 4.7
Instruction BF
Branch Instructions
Operation label When T = 0, disp x 2 + PC + 4 PC When T = 1, nop Delayed branch; when T = 0, disp x 2 + PC + 4 PC When T = 1, nop When T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch; when T = 1, disp x 2 + PC + 4 PC When T = 0, nop Delayed branch, disp x 2 + PC + 4 PC Instruction Code 10001011dddddddd Privileged -- T Bit --
BF/S
label
10001111dddddddd
--
--
BT
label
10001001dddddddd
--
--
BT/S
label
10001101dddddddd
--
--
BRA BRAF BSR BSRF JMP JSR RTS
label Rn label Rn @Rn @Rn
1010dddddddddddd
-- -- -- -- -- -- --
-- -- -- -- -- -- --
Delayed branch, Rn + PC + 4 0000nnnn00100011 PC Delayed branch, PC + 4 PR, 1011dddddddddddd disp x 2 + PC + 4 PC Delayed branch, PC + 4 PR, 0000nnnn00000011 Rn + PC + 4 PC Delayed branch, Rn PC 0100nnnn00101011 Delayed branch, PC + 4 PR, 0100nnnn00001011 Rn PC Delayed branch, PR PC 0000000000001011
Rev. 1.0, 02/03, page 67 of 1294
Table 4.8
Instruction CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L LDTLB
System Control Instructions
Operation 0 MACH, MACL 0S 0T Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,DBR Rm,Rn_BANK @Rm+,SR @Rm+,GBR @Rm+,VBR @Rm+,SSR @Rm+,SPC @Rm+,DBR @Rm+,Rn_BANK Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm DBR Rm Rn_BANK (n = 0 to 7) (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) DBR, Rm + 4 Rm (Rm) Rn_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB R0 (Rn) (without fetching cache block) No operation @Rn @Rn @Rn @Rn Instruction Code 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm11111010 0100mmmm1nnn1110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm11110110 0100mmmm1nnn0111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000nnnn11000011 0000000000001001 Privileged -- -- -- Privileged -- Privileged Privileged Privileged Privileged Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged -- -- -- -- -- -- Privileged -- -- -- -- -- -- Privileged T Bit -- -- 0 LSB -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MOVCA.L R0,@Rn NOP OCBI OCBP OCBWB PREF RTE
Invalidates operand cache block 0000nnnn10010011 Writes back and invalidates operand cache block (Rn) operand cache Delayed branch, SSR/SPC SR/PC 0000nnnn10100011
Writes back operand cache block0000nnnn10110011 0000nnnn10000011 0000000000101011
Rev. 1.0, 02/03, page 68 of 1294
Instruction SETS SETT SLEEP STC STC STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L TRAPA SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn SGR,Rn DBR,Rn Rm_BANK,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn SSR,@-Rn SPC,@-Rn SGR,@-Rn DBR,@-Rn Rm_BANK,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn #imm
Operation 1S 1T Sleep or standby SR Rn GBR Rn VBR Rn SSR Rn SPC Rn SGR Rn DBR Rn Rm_BANK Rn (m = 0 to 7) Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, VBR (Rn) Rn - 4 Rn, SSR (Rn) Rn - 4 Rn, SPC (Rn) Rn - 4 Rn, SGR (Rn) Rn - 4 Rn, DBR (Rn)
Instruction Code 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn00111010 0000nnnn11111010 0000nnnn1mmm0010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn00110010 0100nnnn11110010
Privileged -- -- Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged Privileged Privileged -- Privileged Privileged Privileged Privileged Privileged Privileged -- -- -- -- -- -- --
T Bit -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Rn - 4 Rn, 0100nnnn1mmm0011 Rm_BANK (Rn) (m = 0 to 7) MACH Rn MACL Rn PR Rn Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Rn - 4 Rn, PR (Rn) PC + 2 SPC, SR SSR, #imm << 2 TRA, H'160 EXPEVT, VBR + H'0100 PC 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii
Rev. 1.0, 02/03, page 69 of 1294
Table 4.9
Instruction FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV FMOV FMOV FMOV FMOV FMOV FMOV FLDS FSTS FABS FADD FCMP/EQ FCMP/GT FDIV FLOAT FMAC FMUL FNEG FSQRT FSUB FTRC
Floating-Point Single-Precision Instructions
Operation FRn FRn FRm,FRn @Rm,FRn @(R0,Rm),FRn @Rm+,FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) DRm,DRn @Rm,DRn @(R0,Rm),DRn @Rm+,DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn) FRm,FPUL FPUL,FRn FRn FRm,FRn FRm,FRn FRm,FRn FRm,FRn FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn FRm,FRn FRm,FPUL H'0000 0000 FRn H'3F80 0000 FRn FRm FRn (Rm) FRn (R0 + Rm) FRn FRm (Rn) Rn-4 Rn, FRm (Rn) FRm (R0 + Rn) DRm DRn (Rm) DRn (R0 + Rm) DRn DRm (Rn) Rn-8 Rn, DRm (Rn) DRm (R0 + Rn) FRm FPUL FPUL FRn FRn + FRm FRn When FRn = FRm, 1 T Otherwise, 0 T When FRn > FRm, 1 T Otherwise, 0 T FRn/FRm FRn (float) FPUL FRn FR0*FRm + FRn FRn FRn*FRm FRn FRn H'8000 0000 FRn FRn FRn FRn - FRm FRn (long) FRm FPUL Instruction Code 1111nnnn10001101 1111nnnn10011101 1111nnnnmmmm1100 1111nnnnmmmm1000 1111nnnnmmmm0110 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Comparison result Comparison result -- -- -- -- -- -- -- --
(Rm) FRn, Rm + 4 Rm 1111nnnnmmmm1001 1111nnnnmmmm1010 1111nnnnmmmm1011 1111nnnnmmmm0111 1111nnn0mmm01100 1111nnn0mmmm1000 1111nnn0mmmm0110
(Rm) DRn, Rm + 8 Rm 1111nnn0mmmm1001 1111nnnnmmm01010 1111nnnnmmm01011 1111nnnnmmm00111 1111mmmm00011101 1111nnnn00001101
FRn & H'7FFF FFFF FRn 1111nnnn01011101 1111nnnnmmmm0000 1111nnnnmmmm0100 1111nnnnmmmm0101 1111nnnnmmmm0011 1111nnnn00101101 1111nnnnmmmm1110 1111nnnnmmmm0010 1111nnnn01001101 1111nnnn01101101 1111nnnnmmmm0001 1111mmmm00111101
Rev. 1.0, 02/03, page 70 of 1294
Table 4.10 Floating-Point Double-Precision Instructions
Instruction FABS FADD FCMP/EQ FCMP/GT FDIV FCNVDS FCNVSD FLOAT FMUL FNEG FSQRT FSUB FTRC DRn DRm,DRn DRm,DRn DRm,DRn DRm,DRn DRm,FPUL FPUL,DRn FPUL,DRn DRm,DRn DRn DRn DRm,DRn DRm,FPUL Operation Instruction Code Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- Comparison result Comparison result -- -- -- -- -- -- -- -- --
DRn & H'7FFF FFFF FFFF FFFF 1111nnn001011101 DRn DRn + DRm DRn When DRn = DRm, 1 T Otherwise, 0 T When DRn > DRm, 1 T Otherwise, 0 T DRn /DRm DRn 1111nnn0mmm00000 1111nnn0mmm00100 1111nnn0mmm00101 1111nnn0mmm00011
double_to_ float[DRm] FPUL 1111mmm010111101 float_to_ double [FPUL] DRn 1111nnn010101101 (float)FPUL DRn DRn *DRm DRn DRn ^ H'8000 0000 0000 0000 DRn DRn DRn DRn - DRm DRn (long) DRm FPUL 1111nnn000101101 1111nnn0mmm00010 1111nnn001001101 1111nnn001101101 1111nnn0mmm00001 1111mmm000111101
Table 4.11 Floating-Point Control Instructions
Instruction LDS LDS LDS.L LDS.L STS STS STS.L STS.L Rm,FPSCR Rm,FPUL @Rm+,FPSCR @Rm+,FPUL FPSCR,Rn FPUL,Rn FPSCR,@-Rn FPUL,@-Rn Operation Rm FPSCR Rm FPUL (Rm) FPSCR, Rm+4 Rm (Rm) FPUL, Rm+4 Rm FPSCR Rn FPUL Rn Rn - 4 Rn, FPSCR (Rn) Rn - 4 Rn, FPUL (Rn) Instruction Code 0100mmmm01101010 0100mmmm01011010 0100mmmm01100110 0100mmmm01010110 0000nnnn01101010 0000nnnn01011010 0100nnnn01100010 0100nnnn01010010 Privileged -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- --
Rev. 1.0, 02/03, page 71 of 1294
Table 4.12 Floating-Point Graphics Acceleration Instructions
Instruction FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FTRV FRCHG FSCHG DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rn XDm,@(R0,Rn) FVm,FVn XMTRX,FVn Operation DRm XDn XDm DRn XDm XDn (Rm) XDn (Rm) XDn, Rm + 8 Rm (R0 + Rm) XDn XDm (Rn) Rn - 8 Rn, XDm (Rn) XDm (R0 + Rn) inner_product [FVm, FVn] FR[n+3] Instruction Code 1111nnn1mmm01100 1111nnn0mmm11100 1111nnn1mmm11100 1111nnn1mmmm1000 1111nnn1mmmm1001 1111nnn1mmmm0110 1111nnnnmmm11010 1111nnnnmmm11011 1111nnnnmmm10111 1111nnmm11101101 Privileged -- -- -- -- -- -- -- -- -- -- -- -- -- T Bit -- -- -- -- -- -- -- -- -- -- -- -- --
transform_vector [XMTRX, FVn] 1111nn0111111101 FVn ~FPSCR.FR FPSCR.FR ~FPSCR.SZ FPSCR.SZ 1111101111111101 1111001111111101
Rev. 1.0, 02/03, page 72 of 1294
Section 5 Pipelining
This LSI is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor. Instruction execution is pipelined, and two instructions can be executed in parallel. The execution cycles depend on the implementation of a processor. The definitions in this section may not be applied to the SH-4 Series other than this LSI.
5.1
Pipelines
Figure 5.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA), and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 5.2 shows the instruction execution patterns.
Rev. 1.0, 02/03, page 73 of 1294
1. General Pipeline
I D EX NA * Non-memory data access S * Write-back * Instruction fetch * Instruction * Operation decode * Issue * Register read * Destination address calculation for PC-relative branch
2. General Load/Store Pipeline
I D EX * Address calculation MA * Memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read
3. Special Pipeline
I D SX * Operation NA * Non-memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read
4. Special Load/Store Pipeline
I D SX * Address calculation MA * Memory data access S * Write-back * Instruction fetch * Instruction decode * Issue * Register read
5. Floating-Point Pipeline
I D F1 * Computation 1 F2 * Computation 2 FS * Computation 3 * Write-back * Instruction fetch * Instruction decode * Issue * Register read
6. Floating-Point Extended Pipeline
I D F0 * Computation 0 F1 * Computation 1 F2 * Computation 2 FS * Computation 3 * Write-back * Instruction fetch * Instruction decode * Issue * Register read
7. FDIV/FSQRT Pipeline
F3 Computation: Takes several cycles
Figure 5.1 Basic Pipelines
Rev. 1.0, 02/03, page 74 of 1294
1. 1-step operation: 1 issue cycle EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*, DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#, ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT, LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS, single-/double-precision FABS/FNEG
I D EX NA S
2. Load/store: 1 issue cycle MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
I D EX MA S
3. GBR-based load/store: 1 issue cycle MOV.[BWL]@(d,GBR)
I D SX MA S
4. JMP, RTS, BRAF: 2 issue cycles
I D EX D NA EX S NA S
5. TST.B: 3 issue cycles
I D SX D MA SX D S NA SX S NA
S
6. AND.B, OR.B, XOR.B: 4 issue cycles
I D SX D MA SX D S NA SX D S NA SX
S MA
S
7. TAS.B: 5 issue cycles
I D EX D MA EX D S MA EX D S NA EX D
S NA EX
S MA
S
8. RTE: 5 issue cycles
I D EX D NA EX D S NA EX D S NA EX D
S NA EX
S NA
S
9. SLEEP: 4 issue cycles
I D EX D NA EX D S NA EX D S NA EX
S NA
S
Figure 5.2 Instruction Execution Patterns
Rev. 1.0, 02/03, page 75 of 1294
10. OCBI: 1 issue cycle
I D EX MA S MA
11. OCBP, OCBWB: 1 issue cycle
I D EX MA S MA MA MA MA
12. MOVCA.L: 1 issue cycle
I D EX MA S MA MA MA MA MA MA
13. TRAPA: 7 issue cycles
I D EX D NA EX D S NA EX D S NA EX D
S NA EX D
S NA EX D
S NA EX
S NA
S
14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle
I D EX NA SX S SX
15. LDC to GBR: 3 issue cycles
I D EX D NA SX D S SX
16. LDC to SR: 4 issue cycles
I D EX D NA SX D S SX D
SX
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I D EX MA SX S SX
18. LDC.L to GBR: 3 issue cycles
I D EX D MA SX D S SX
Figure 5.2 Instruction Execution Patterns (cont)
Rev. 1.0, 02/03, page 76 of 1294
19. LDC.L to SR: 4 issue cycles
I D EX D MA SX D S SX D
SX
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I D SX D NA SX S NA S
21. STC. from SGR: 3 issue cycles
I D SX D NA SX D S NA SX S NA
S
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I D SX D NA SX S MA S
23. STC.L from SGR: 3 issue cycles
I D SX D NA SX D S NA SX S MA
S
24. LDS to PR, JSR, BSRF: 2 issue cycles
I D EX D NA SX S SX
25. LDS.L to PR: 2 issue cycles
I D EX D MA SX S SX
26. STS from PR: 2 issue cycles
I D SX D NA SX S NA S
27. STS.L from PR: 2 issue cycles
I D SX D NA SX S MA S
28. CLRMAC, LDS to MACH/L: 1 issue cycle
I D EX NA F1 S F1 F2 FS
29. LDS.L to MACH/L: 1 issue cycle
I D EX MA F1 S F1 F2 FS
30. STS from MACH/L: 1 issue cycle
I D EX NA S
Figure 5.2 Instruction Execution Patterns (cont)
Rev. 1.0, 02/03, page 77 of 1294
31. STS.L from MACH/L: 1 issue cycle
I D EX MA S
32. LDS to FPSCR: 1 issue cycle
I D EX NA F1 S F1 F1
33. LDS.L to FPSCR: 1 issue cycle
I D EX MA F1 S F1 F1
34. Fixed-point multiplication: 2 issue cycles DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W
I D EX D f1 f1 f1 f1 F2 FS NA EX S NA (CPU) S (FPU)
35. MAC.W, MAC.L: 2 issue cycles
I D EX D f1 f1 f1 f1 F2 FS MA EX S MA (CPU) S (FPU)
36. Single-precision floating-point computation: 1 issue cycle FCMP/EQ, FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRCHG, FSCHG
I D F1 F2 FS
37. Single-precision FDIV/SQRT: 1 issue cycle
I D F1 F2 FS F3 F1 F2 FS
38. Double-precision floating-point computation 1: 1 issue cycle FCNVDS, FCNVSD, FLOAT, FTRC
I D F1 d F2 F1 FS F2 FS
39. Double-precision floating-point computation 2: 1 issue cycle FADD, FMUL, FSUB
I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d
FS F2 F1
FS F2 F1
FS F2
FS
Figure 5.2 Instruction Execution Patterns (cont)
Rev. 1.0, 02/03, page 78 of 1294
40. Double-precision FCMP: 2 issue cycles FCMP/EQ, FCMP/GT
I D F1 D F2 F1 FS F2 FS
41. Double-precision FDIV/FSQRT: 1 issue cycle FDIV, FSQRT
I D F1 d F2 F1 FS F2 F3 F1 F2 F1 FS F2 F1 FS F2
42. FIPR: 1 issue cycle
I D F0 F1 F2 FS
FS
43. FTRV: 1 issue cycle
I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0 FS F2 F1
FS F2
FS
Notes:
??
: Cannot overlap a stage of the same kind, except when two instructions are executed in parallel. : Locks D-stage. : Register read only : Locks, but no operation is executed. : Can overlap another f1, but not another F1.
D d ?? f1
Figure 5.2 Instruction Execution Patterns (cont)
Rev. 1.0, 02/03, page 79 of 1294
5.2
Parallel-Executability
Instructions are categorized into six groups according to the internal function blocks used, as shown in table 5.1. Table 5.2 shows the parallel-executability of pairs of instructions in terms of groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel. Table 5.1 Instruction Groups
1. MT Group CLRT CMP/EQ CMP/EQ CMP/GE CMP/GT #imm,R0 Rm,Rn Rm,Rn Rm,Rn CMP/HI CMP/HS CMP/PL CMP/PZ CMP/STR Rm,Rn Rm,Rn Rn Rn Rm,Rn MOV NOP SETT TST TST #imm,R0 Rm,Rn Rm,Rn
2. EX Group ADD ADD ADDC ADDV AND AND DIV0S DIV0U DIV1 DT EXTS.B EXTS.W EXTU.B EXTU.W MOV MOVA Rm,Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn #imm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn MOVT NEG NEGC NOT OR OR ROTCL ROTCR ROTL ROTR SHAD SHAL SHAR SHLD SHLL Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn SHLL2 SHLL8 SHLR SHLR16 SHLR2 SHLR8 SUB SUBC SUBV SWAP.B SWAP.W XOR XOR XTRCT Rn Rn Rn Rn Rn Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn
@(disp,PC),R0 SHLL16
3. BR Group BF BF/S disp disp BRA BSR disp disp BT BT/S disp disp
Rev. 1.0, 02/03, page 80 of 1294
4. LS Group FABS FABS FLDI0 FLDI1 FLDS FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV.S FMOV.S DRn FRn FRn FRn FRm,FPUL @(R0,Rm),DRn @(R0,Rm),XDn @Rm,DRn @Rm,XDn @Rm+,DRn @Rm+,XDn DRm,@(R0,Rn) DRm,@-Rn DRm,@Rn DRm,DRn DRm,XDn FRm,FRn XDm,@(R0,Rn) XDm,@-Rn XDm,@Rn XDm,DRn XDm,XDn @(R0,Rm),FRn @Rm,FRn FMOV.S FMOV.S FMOV.S FMOV.S FNEG FNEG FSTS LDS MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.B MOV.L MOV.L MOV.L MOV.L MOV.L MOV.L @Rm+,FRn FRm,@(R0,Rn) FRm,@-Rn FRm,@Rn DRn FRn FPUL,FRn Rm,FPUL MOV.L MOV.L MOV.L MOV.L MOV.L MOV.W MOV.W MOV.W R0,@(disp,GBR) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn @(disp,GBR),R0 @(disp,PC),Rn @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn R0,@(disp,GBR) R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn R0,@Rn @Rn @Rn @Rn @Rn FPUL,Rn
@(disp,GBR),R0 MOV.W @(disp,Rm),R0 @(R0,Rm),Rn @Rm,Rn @Rm+,Rn MOV.W MOV.W MOV.W MOV.W
R0,@(disp,GBR) MOV.W R0,@(disp,Rn) Rm,@(R0,Rn) Rm,@-Rn Rm,@Rn MOV.W MOV.W MOVCA.L OCBI
@(disp,GBR),R0 OCBP @(disp,PC),Rn @(disp,Rm),Rn @(R0,Rm),Rn @Rm,Rn @Rm+,Rn OCBWB PREF STS
5. FE Group FADD FADD FCMP/EQ FCMP/GT FCNVDS FCNVSD FDIV FDIV DRm,DRn FRm,FRn FRm,FRn FRm,FRn DRm,FPUL FPUL,DRn DRm,DRn FRm,FRn FIPR FLOAT FLOAT FMAC FMUL FMUL FRCHG FSCHG FVm,FVn FPUL,DRn FPUL,FRn DRm,DRn FRm,FRn FSQRT FSQRT FSUB FTRC FTRC FTRV DRn FRn DRm,DRn FRm,FRn DRm,FPUL FRm,FPUL XMTRX,FVn
FR0,FRm,FRn FSUB
Rev. 1.0, 02/03, page 81 of 1294
6. CO Group AND.B BRAF BSRF CLRMAC CLRS DMULS.L DMULU.L FCMP/EQ FCMP/GT JMP JSR LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L Rm,Rn Rm,Rn DRm,DRn DRm,DRn @Rn @Rn Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SPC Rm,SR Rm,SSR Rm,VBR @Rm+,DBR @Rm+,GBR #imm,@(R0,GBR) LDS Rm Rm LDS LDS LDS LDS.L LDS.L LDS.L LDS.L LDS.L LDTLB MAC.L MAC.W MUL.L MULS.W MULU.W OR.B RTE RTS SETS SLEEP DBR,Rn GBR,Rn Rp_BANK,Rn SGR,Rn SPC,Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,FPSCR Rm,MACH Rm,MACL Rm,PR @Rm+,FPSCR @Rm+,FPUL @Rm+,MACH @Rm+,MACL @Rm+,PR STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS SR,Rn SSR,Rn VBR,Rn DBR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SGR,@-Rn SPC,@-Rn SR,@-Rn SSR,@-Rn VBR,@-Rn FPSCR,Rn MACH,Rn MACL,Rn PR,Rn FPSCR,@-Rn FPUL,@-Rn MACH,@-Rn MACL,@-Rn PR,@-Rn @Rn #imm #imm,@(R0,GBR) #imm,@(R0,GBR)
#imm,@(R0,GBR) STS.L STS.L STS.L STS.L STS.L TAS.B TRAPA TST.B XOR.B
@Rm+,Rp_BANK STC @Rm+,SPC @Rm+,SR @Rm+,SSR @Rm+,VBR STC STC STC STC
Rev. 1.0, 02/03, page 82 of 1294
Table 5.2
Parallel-Executability
2nd Instruction MT EX O X O O O X BR O O X O O X LS O O O X O X FE O O O O X X CO X X X X X X
1st Instruction
MT EX BR LS FE CO
O O O O O X
Legend: O: Can be executed in parallel X: Cannot be executed in parallel
5.3
Execution Cycles and Pipeline Stalling
This LSI has three basic clocks: CPU clock (Ick), bus clock (Bck), and peripheral clock (Pck). Each hardware unit operates on one of these clocks, as follows: * CPU clock: CPU, FPU, MMU, cache * Bus clock: External bus controller * Peripheral clock: Peripheral units The frequency ratios of the three clocks are determined with the frequency control register (FRQCR). In this section, machine cycles are based on the CPU clock unless otherwise specified. For details on FRQCR, see section 12, Clock Pulse Generator (CPG). Instruction execution cycles are summarized in table 5.3. Penalty cycles due to a pipeline stall are not considered in this table. * Issue rate: Interval between the issue of an instruction and that of the next instruction * Latency: Interval between the issue of an instruction and the generation of its result (completion) * Instruction execution pattern (see figure 5.2) * Locked pipeline stage: Pipeline stage which has been locked * Lock start: Interval between the issue of an instruction and the start of locking (see table 5.3) * Lock cycle: Period of locking (see table 5.3)
Rev. 1.0, 02/03, page 83 of 1294
The instruction execution sequence is expressed as a combination of the execution patterns shown in figure 5.2. One instruction is separated from the next by the number of machine cycles for its issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the same stages of another instruction; the only exception is when two instructions are executed in parallel under parallel-executability conditions. See (a) to (d) in figure 5.3 for some simple examples. Latency is the interval between issue and completion of an instruction, and is also the interval between the execution of two instructions with an interdependent relationship. When there is interdependency between two instructions fetched simultaneously, the latter of the two is stalled for the following number of cycles: * (Latency) cycles when there is flow dependency (read-after-write) * (Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write) Single/double-precision FDIV or FSQRT is the preceding instruction: (latency - 1) cycles Other instructions in the FE group is the preceding instruction: (latency - 2) cycles * Five or two cycles when there is anti-flow dependency (write-after-read), as in the following cases: FTRV is the preceding instruction: 5 cycles Double-precision FADD, FSUB, or FMUL is the preceding instruction: 2 cycles In the case of flow dependency, the latency may be exceptionally increased or decreased, depending on the combination of sequential instructions (figure 5.3 (e)). * When a floating-point computation is followed by a floating-point register store, latency of the floating-point computation may be decreased by one cycle. * If there is a load of the shift amount immediately before an SHAD or SHLD instruction, latency of the load is increased by one cycle. * If an instruction with latency of less than two cycles, including write-back to a floating-point register, is followed by a double-precision floating-point instruction, FIPR, or FTRV, latency of the first instruction is increased to two cycles. The number of cycles in a pipeline stall due to flow dependency will vary depending on the combination of interdependent instructions or the fetch timing (see figure 5.3 (e)). Output dependency occurs when the destination operands are the same in a preceding FE group instruction and a following LS group instruction. For the stall cycles of an instruction with output dependency, the longest latency to the last writeback among all the destination operands must be applied instead of "latency" (see figure 5.3 (f)). A stall due to output dependency with respect to FPSCR, which reflects the result of a floating-point operation, never occurs. For example, when FADD follows FDIV with no dependency between
Rev. 1.0, 02/03, page 84 of 1294
floating-point registers, FADD is not stalled even if both instructions update the cause field of FPSCR. Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL, FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS (see figure 5.3 (g)). If an executing instruction locks any resource--i.e. a function block that performs a basic operation--a following instruction that happens to attempt to use the locked resource must be stalled (figure 5.3 (h)). This kind of stall can be compensated by inserting one or more instructions independent of the locked resource to separate the interfering instructions. For example, when a load instruction and an ADD instruction that references the loaded value are consecutive, the 2cycle stall of the ADD is eliminated by inserting three instructions without dependency. Software performance can be improved by such instruction scheduling. Other penalties arise in the event of exceptions or external data accesses, as follows. * Instruction TLB miss * Instruction access to external memory (instruction cache miss, etc.) * Data access to external memory (operand cache miss, etc.) * Data access to a memory-mapped control register During the penalty cycles of an instruction TLB miss or external instruction access, no instruction is issued, but execution of instructions that have already been issued continues. The penalty for a data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted until the arrival of the requested data. The number of penalty cycles for instruction and data accesses is largely dependent on the user's memory subsystems.
Rev. 1.0, 02/03, page 85 of 1294
(a) Serial execution: Non-parallel-executable instructions
SHAD R0,R1 ADD R2,R3 next I I D 1 issue cycle EX NA EX D 1 stall cycle D ... S NA EX-group SHAD and EX-group ADD cannot be executed in parallel. Therefore, the preceding SHAD is issued, and the following ADD is recombined with the next instruction.
S
I
(b) Parallel execution: Parallel-executable and no dependency
ADD R2,R1 MOV.L @R4,R5 I I D D 1 issue cycle EX NA EX MA S S EX-group ADD and LS-group MOV.L can be executed in parallel. Overlapping of stages in the two instructions is possible.
(c) Issue rate: Multi-step instruction
4 issue cycles AND.B#1,@(R0,GBR) I D SX D MA SX D S NA SX D i I S NA SX D ... AND.B and MOV are fetched simultaneously, but MOV is stalled due to resource locking. After the lock is released, MOV is refetched together with the next instruction. S
MOV next
R1,R2
I 4 stall cycles
S MA E
S A
(d) Branch
BT/S L_far ADD R0,R1 SUB R2,R3 I I D D I EX EX D NA NA EX S S NA No stall occurs if the branch is not taken. S
BT/S L_far ADD R0,R1 L_far BT L_skip ADD #1,R0 L_skip:
I I
D D
2-cycle latency for I-stage of branch destination If the branch is taken, the I-stage of the EX S NA branch destination is stalled for the period EX S NA of latency. This stall can be covered with a 1 stall cycle delay slot instruction which is not parallelI D ... executable with the branch instruction. EX -- D NA -- ... S -- Even if the BT/BF branch is taken, the Istage of the branch destination is not stalled if the displacement is zero.
I I
D D I No stall
Figure 5.3 Examples of Pipelined Execution
Rev. 1.0, 02/03, page 86 of 1294
(e) Flow dependency
MOV ADD R0,R1 R2,R1 I I D D Zero-cycle latency EX NA S EX NA S 1-cycle latency EX NA S EX MA D ... The following instruction, ADD, is not stalled when executed after an instruction with zero-cycle latency, even if there is dependency. ADD and MOV.L are not executed in parallel, since MOV.L references the result of ADD as its load address.
ADD R2,R1 MOV.L @R1,R1 next
D i I 1 stall cycle
I I
S
MOV.L @R1,R1 ADD R0,R1 next
I
D I I
EX D ...
2-cycle latency S EX NA 1 stall cycle MA
S
Because MOV.L and ADD are not fetched simultaneously in this example, ADD is stalled for only 1 cycle even though the latency of MOV.L is 2 cycles.
2-cycle latency 1-cycle increase MOV.L @R1,R1 SHAD R1,R2 next I D I I EX D ... MA S d EX NA S Due to the flow dependency between the load and the SHAD/SHLD shift amount, the latency of the load is increased to 3 cycles.
2 stall cycles
4-cycle latency for FPSCR FADD STS STS FR1,FR2 FPUL,R1 FPSCR,R2 I D I F1 D I F2 EX FS NA S D
EX
NA
S
2 stall cycles 7-cycle latency for lower FR 8-cycle latency for upper FR FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d
FS F2 F1
FS F2 F1
FMOV FMOV
FR3,FR5 FR2,FR4
I I
FS F2 D
FR3 write FS FR2 write EX NA S EX D NA
S
3-cycle latency for upper/lower FR FLOAT FPUL,DR0 FMOV.S FR0,@-R15 I I D D Zero-cycle latency 3-cycle increase FLDI1 FIPR FR3 FV0,FV4 I I D D EX NA S d F0 F1 3 stall cycles F2 FS F1 d F2 F1 FS F2 FR1 write FS FR0 write EX S MA
2-cycle latency 1-cycle increase FMOV FTRV @R1,XD14 XMTRX,FV0 I I D D EX MA S d F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0
3 stall cycles
FS F2 F1
FS F2
FS
Figure 5.3 Examples of Pipelined Execution (cont)
Rev. 1.0, 02/03, page 87 of 1294
(e) Flow dependency (cont)
Effectively 1-cycle latency for consecutive LDS/FLOAT instructions LDS FLOAT LDS FLOAT R0,FPUL FPUL,FR0 R1,FPUL FPUL,R1 I D I I EX D D I NA F1 EX D S F2 NA F1 FS S F2
FS
FTRC STS FTRC STS
FR0,FPUL FPUL,R0 FR1,FPUL FPUL,R1
I
D I I
F1 D D I
F2 EX F1 D
FS NA F2 EX S FS NA
Effectively 1-cycle latency for consecutive FTRC/STS instructions S
(f) Output dependency
11-cycle latency FSQRT FR4 I D F1 F2 FS F3 F1 FMOV FR0,FR4 I D 10 stall cycles = latency (11) - 1 F2 FS F1 FS F2 The registers are written-back in program order. 7-cycle latency for lower FR 8-cycle latency for upper FR I D F1 d F2 F1 d FS F2 F1 d FS F2 F1 d
FADD
DR0,DR2
FS F2 F1
FS F2 F1
FS F2 EX
FR3 write FS FR2 write NA S
FMOV
FR0,FR3
I
D 6 stall cycles = longest latency (8) - 2
(g) Anti-flow dependency
FTRV XMTRX,FV0 I D F0 d F1 F0 d F2 F1 F0 d FS F2 F1 F0
FS F2 F1
FMOV @R1,XD0
I
D 5 stall cycles
FS F2 EX
FS MA
S
FADD DR0,DR2
I
D
F1 d
F2 F1 d
FS F2 F1 d
FS F2 F1 d NA
FS F2 F1 S
FS F2 F1
FS F2
FS
FMOV FR4,FR1
I
D 2 stall cycles
EX
Figure 5.3 Examples of Pipelined Execution (cont)
Rev. 1.0, 02/03, page 88 of 1294
(h) Resource conflict
#1 #2 F2 #3 FS F3 F1 F2 FS .................................................. #8 #9 #10 #11 #12
1 cycle/issue FDIV FR6,FR7
I D F1
Latency
F1 stage locked for 1 cycle
FMAC FR0,FR8,FR9 FMAC FR0,FR10,FR11 FMAC FR0,FR12,FR13
...
I
D I
F1 D
F2 F1
FS F2 FS I D F1 F2 FS
:
1 stall cycle (F1 stage resource conflict)
FIPR FV8,FV0 FADD FR15,FR4
I
D I
F0 D
F1 1 stall cycle
F2 F1
FS F2
FS
LDS.L @R15+,PR
I
D
EX D
MA SX D
FS SX
STC
GBR,R2
I
3 stall cycles FADD DR0,DR2 I D F1 d F2 F1 d FS F2 F1 d
SX D
NA SX
S NA
S
FS F2 F1 d
FS F2 F1
FS F2 F1
MAC.W @R1+,@R2+
I
D 5 stall cycles
FS F2 EX f1 D
FS MA EX f1
S MA f1 S F2 f1 FS F2
FS
MAC.W @R1+,@R2+
I
D
EX f1 D
MA EX f1
S MA f1 S F2 f1 MA EX f1 FS F2 S MA f1
f1 stage can overlap preceding f1, but F1 cannot overlap f1.
FS
MAC.W @R1+,@R2+
I 1 stall cycle
D
EX f1 D
S F2 f1 FS F2 F1 d
FADD
DR4,DR6
I 3 stall cycles
D 2 stall cycles
FS F2 F1 d
FS F2 F1 d
FS F2 F1 d
FS F2 F1
FS F2 F1
FS ...
Figure 5.3 Examples of Pipelined Execution (cont)
Rev. 1.0, 02/03, page 89 of 1294
Table 5.3
Execution Cycles
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn @(disp,PC),R0 @(disp,PC),Rn @(disp,PC),Rn @Rm,Rn @Rm,Rn @Rm,Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn EX EX EX EX MT EX EX LS LS LS LS LS LS LS LS LS LS LS LS LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 2 2 2 2 2 1/2 1/2 1/2 2 2 2 2 2 2 2 2 2 1 1 1 1/1 1/1 1/1 1 #1 #1 #1 #1 #1 #1 #1 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #3 #3 #3 #2 #2 #2 #2 #2 #2 #2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Functional Category No. Data transfer 1 instructions 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Instruction EXTS.B EXTS.W EXTU.B EXTU.W MOV MOV MOVA MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B
@(disp,GBR),R0 LS @(disp,GBR),R0 LS @(disp,GBR),R0 LS Rm,@Rn Rm,@Rn Rm,@Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn R0,@(disp,Rn) LS LS LS LS LS LS LS
Rev. 1.0, 02/03, page 90 of 1294
Functional Category No. Data transfer 32 instructions 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Fixed-point 49 arithmetic 50 instructions 51 52 53 54 55 56 57 58 59 60 61 62
Instruction MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L R0,@(disp,Rn) Rm,@(disp,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn) Rm,@(R0,Rn)
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles LS LS LS LS LS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 to 7 1 1 to 2 1 to 5 1 to 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #2 #2 #2 #2 #2 #3 #3 #3 #12 #1 #10 #11 #11 #2 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 -- -- -- -- -- -- -- -- MA -- MA MA MA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 -- 4 4 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3 to 7 -- 1 to 2 1 to 5 1 to 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
R0,@(disp,GBR) LS R0,@(disp,GBR) LS R0,@(disp,GBR) LS LS EX LS LS LS LS EX EX EX EX EX EX EX MT MT MT MT MT MT MT MT MT EX
MOVCA.L R0,@Rn MOVT OCBI OCBP OCBWB PREF SWAP.B SWAP.W XTRCT ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/GE CMP/GT CMP/HI CMP/HS CMP/PL CMP/PZ Rn @Rn @Rn @Rn @Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn
CMP/STR Rm,Rn DIV0S Rm,Rn
Rev. 1.0, 02/03, page 91 of 1294
Functional Category No. Fixed-point 63 arithmetic 64 instructions 65 66 67 68 69 70 71 72 73 74 75 76 77 Logical 78 instructions 79 80 81 82 83 84 85 86 87 88 89 90 91
Instruction DIV0U DIV1 DMULS.L Rm,Rn Rm,Rn
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles EX EX CO CO EX CO CO CO CO CO EX EX EX EX EX EX EX 1 1 2 2 1 2 2 2 2 2 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 1 1 4/4 4/4 1 2/2/4/4 2/2/4/4 4/4 4/4 4/4 1 1 1 1 1 1 1 4 1 1 1 4 5 1 1 3 1 1 4 #1 #1 #34 #34 #1 #35 #35 #34 #34 #34 #1 #1 #1 #1 #1 #1 #1 #6 #1 #1 #1 #6 #7 #1 #1 #5 #1 #1 #6 -- -- F1 F1 -- F1 F1 F1 F1 F1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4 -- 4 4 4 4 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- 2 2 2 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DMULU.L Rm,Rn DT MAC.L MAC.W MUL.L MULS.W MULU.W NEG NEGC SUB SUBC SUBV AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rn @Rm+,@Rn+ @Rm+,@Rn+ Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn #imm,R0
#imm,@(R0,GBR) CO Rm,Rn Rm,Rn #imm,R0 EX EX EX
#imm,@(R0,GBR) CO @Rn Rm,Rn #imm,R0 CO MT MT
#imm,@(R0,GBR) CO Rm,Rn #imm,R0 EX EX
#imm,@(R0,GBR) CO
Rev. 1.0, 02/03, page 92 of 1294
Functional Category No. Shift 92 instructions 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Branch 108 instructions 109 110 111 112 113 114 115 116 117 118
Instruction ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 BF BF/S BT BT/S BRA BRAF BSR BSRF JMP JSR RTS Rn Rn Rn Rn Rm,Rn Rn Rn Rm,Rn Rn Rn Rn Rn Rn Rn Rn Rn disp disp disp disp disp Rm disp Rm @Rn @Rn
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX EX BR BR BR BR BR CO BR CO CO CO CO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 (or 1) 2 (or 1) 2 (or 1) 2 (or 1) 2 3 2 3 3 3 3 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #1 #4 #14 #24 #4 #24 #4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SX SX -- SX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- 2 --
Rev. 1.0, 02/03, page 93 of 1294
Functional Category No. System 119 control 120 instructions 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Instruction NOP CLRMAC CLRS CLRT SETS SETT TRAPA RTE SLEEP LDTLB LDC LDC LDC LDC LDC LDC LDC LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L STC STC Rm,DBR Rm,GBR Rm,Rp_BANK Rm,SR Rm,SSR Rm,SPC Rm,VBR @Rm+,DBR @Rm+,GBR #imm
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles MT CO CO MT CO MT CO CO CO CO CO CO CO CO CO CO CO CO CO 1 1 1 1 1 1 7 5 4 1 1 3 1 4 1 1 1 1 3 1 4 1 1 1 1 1 2 1 1 2 2 3 0 3 1 1 1 1 7 5 4 1 3 3 3 4 3 3 3 1/3 3/3 1/3 4/4 1/3 1/3 1/3 3 3 3 1/3 1/3 2/3 2 3 #1 #28 #1 #1 #1 #1 #13 #8 #9 #2 #14 #15 #14 #16 #14 #14 #14 #17 #18 #17 #19 #17 #17 #17 #28 #28 #24 #29 #29 #25 #20 #21 -- F1 -- -- -- -- -- -- -- -- SX SX SX SX SX SX SX SX SX SX SX SX SX SX F1 F1 SX F1 F1 SX -- -- -- 3 -- -- -- -- -- -- -- -- 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 -- -- -- 2 -- -- -- -- -- -- -- -- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- --
@Rm+,Rp_BANK CO @Rm+,SR @Rm+,SSR @Rm+,SPC @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR DBR,Rn SGR,Rn CO CO CO CO CO CO CO CO CO CO CO CO
Rev. 1.0, 02/03, page 94 of 1294
Functional Category No. System 151 control 152 instructions 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Single171 precision 172 floating-point instructions 173 174 175 176 177 178 179 180 181
Instruction STC STC STC STC STC STC STC.L STC.L STC.L STC.L STC.L STC.L STC.L STC.L STS STS STS STS.L STS.L STS.L FLDI0 FLDI1 FMOV FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FMOV.S FLDS FSTS GBR,Rn Rp_BANK,Rn SR,Rn SSR,Rn SPC,Rn VBR,Rn DBR,@-Rn SGR,@-Rn GBR,@-Rn Rp_BANK,@-Rn SR,@-Rn SSR,@-Rn SPC,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn PR,@-Rn FRn FRn FRm,FRn @Rm,FRn @Rm+,FRn @(R0,Rm),FRn FRm,@Rn FRm,@-Rn FRm,@(R0,Rn) FRm,FPUL FPUL,FRn
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO LS LS LS LS LS LS LS LS LS LS LS 2 2 2 2 2 2 2 3 2 2 2 2 2 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2/2 3/3 2/2 2/2 2/2 2/2 2/2 2/2 3 3 2 1/1 1/1 2/2 0 0 0 2 1/2 2 1 1/1 1 0 0 #20 #20 #20 #20 #20 #20 #22 #23 #22 #22 #22 #22 #22 #22 #30 #30 #26 #31 #31 #27 #1 #1 #1 #2 #2 #2 #2 #2 #2 #1 #1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Rev. 1.0, 02/03, page 95 of 1294
Functional Category No. Single182 precision 183 floating-point instructions 184 185 186
Instruction FABS FADD FRn FRm,FRn
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles LS FE FE FE FE 1 1 1 1 1 0 3/4 2/4 2/4 12/13 #1 #36 #36 #36 #37 -- -- -- -- F3 F1 -- -- -- -- 2 11 -- -- -- -- 2 10 -- -- -- -- -- -- -- -- -- -- 2 2 2 2 2 2 22 2 2 2 -- -- -- -- 10 1 -- -- -- -- 9 1 -- -- -- -- -- -- -- -- -- -- 6 2 2 2 2 23 3 2 2 6
FCMP/EQ FRm,FRn FCMP/GT FRm,FRn FDIV FRm,FRn
187 188 189 190 191
FLOAT FMAC FMUL FNEG FSQRT
FPUL,FRn FR0,FRm,FRn FRm,FRn FRn FRn
FE FE FE LS FE
1 1 1 1 1
3/4 3/4 3/4 0 11/12
#36 #36 #36 #1 #37
-- -- -- -- F3 F1
192 193 194 195 196 197 198 199 200 Double201 precision 202 floating-point instructions 203 204 205 206 207
FSUB FTRC FMOV FMOV FMOV FMOV FMOV FMOV FMOV FABS FADD
FRm,FRn FRm,FPUL DRm,DRn @Rm,DRn @Rm+,DRn @(R0,Rm),DRn DRm,@Rn DRm,@-Rn DRm,@(R0,Rn) DRn DRm,DRn
FE FE LS LS LS LS LS LS LS LS FE CO CO FE FE FE
1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1
3/4 3/4 0 2 1/2 2 1 1/1 1 0 (7, 8)/9 3/5 3/5 4/5 (3, 4)/5
#36 #36 #1 #2 #2 #2 #2 #2 #2 #1 #39 #40 #40 #38 #38
-- -- -- -- -- -- -- -- -- -- F1 F1 F1 F1 F1 F3 F1 F1
FCMP/EQ DRm,DRn FCMP/GT DRm,DRn FCNVDS FCNVSD FDIV DRm,FPUL FPUL,DRn DRm,DRn
(24, 25)/ #41 26
208 209
FLOAT FMUL
FPUL,DRn DRm,DRn
FE FE
1 1
(3, 4)/5 (7, 8)/9
#38 #39
F1 F1
Rev. 1.0, 02/03, page 96 of 1294
Functional Category No. Double210 precision 211 floating-point instructions
Instruction FNEG FSQRT DRn DRn
InstrucLock Issue Execution tion Group Rate Latency Pattern Stage Start Cycles LS FE 1 1 0 #1 -- F3 F1 F1 -- 2 21 2 2 2 -- 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 3 -- -- 2 3 -- 22 3 2 6 2 -- 3 -- 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- 4 4
(23, 24)/ #41 25
212 213 FPU system 214 control 215 instructions 216 217 218 219 220 221 Graphics 222 acceleration 223 instructions 224 225 226 227 228 229 230 231 232 233 234
FSUB FTRC LDS LDS LDS.L LDS.L STS STS STS.L STS.L FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FMOV FIPR FRCHG FSCHG FTRV
DRm,DRn DRm,FPUL Rm,FPUL Rm,FPSCR @Rm+,FPUL @Rm+,FPSCR FPUL,Rn FPSCR,Rn FPUL,@-Rn FPSCR,@-Rn DRm,XDn XDm,DRn XDm,XDn @Rm,XDn @Rm+,XDn @(R0,Rm),XDn XDm,@Rn XDm,@-Rm XDm,@(R0,Rn) FVm,FVn
FE FE LS CO CO CO LS CO CO CO LS LS LS LS LS LS LS LS LS FE FE FE
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(7, 8)/9 4/5 1 4 1/2 1/4 3 3 1/1 1/1 0 0 0 2 1/2 2 1 1/1 1 4/5 1/4 1/4
#39 #38 #1 #32 #2 #33 #1 #1 #2 #2 #1 #1 #1 #2 #2 #2 #2 #2 #2 #42 #36 #36
F1 F1 -- F1 -- F1 -- -- -- -- -- -- -- -- -- -- -- -- -- F1 -- -- F0 F1
XMTRX,FVn
FE
(5, 5, 6, #43 7)/8
Notes: 1. See table 5.1 for the instruction groups. 2. Latency "L1/L2... ": Latency corresponding to a write to each register, including MACH/MACL/FPSCR. Example: MOV.B @Rm+, Rn "1/2": Latency for Rm is 1 cycle and latency for Rn is 2 cycles. 3. Branch latency: Interval until the branch destination instruction is fetched 4. Conditional branch latency "2 (or 1) ": Latency is 2 for a non-zero displacement, and 1 for a zero displacement. 5. Double-precision floating-point instruction latency " (L1, L2)/L3": L1 is the latency for FR [n+1], L2 that for FR [n], and L3 that for FPSCR. Rev. 1.0, 02/03, page 97 of 1294
6. FTRV latency " (L1, L2, L3, L4)/L5": L1 is the latency for FR [n], L2 that for FR [n+1], L3 that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR. 7. Latency "L1/L2/L3/L4" of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2 that for Rn, L3 that for MACH, and L4 that for MACL. 8. Latency "L1/L2" of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions: L1 is the latency for MACH, and L2 that for MACL. 9. Execution pattern: Instruction execution pattern number (see figure 5.2) 10. Lock/stage: Stage locked by the instruction 11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction. 12. Lock/cycles: Number of cycles locked Exceptions: 1. When a floating-point computation instruction is followed by an FMOV store instruction, an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, latency of the floating-point computation is decreased by 1 cycle. 2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, latency of the load is increased by 1 cycle. 3. When an LS group instruction with latency of less than 3 cycles is followed by a doubleprecision floating-point instruction, FIPR, or FTRV, latency of the first instruction is increased to 3 cycles. Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2 cycles. 4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an STS.L MACH/MACL, @-Rn instruction, latency of MAC.W/MAC.L/MUL.L/MULS.W/ MULU.W/DMULS.L/DMULU.L is 5 cycles. 5. In the case of consecutive executions of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/ DMULS.L/DMULU.L, latency is decreased to 2 cycles. 6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn instruction, latency of the LDS to MACH/MACL is 4 cycles. 7. When an LDS to MACH/MACL is followed by MAC.W/MAC.L/MUL.L/MULS.W/ MULU.W/DMULS.L/DMULU.L, latency of the LDS to MACH/MACL is 1 cycle. 8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that reads from or writes to a floating-point register, the aforementioned LS group instructions cannot be executed in parallel. 9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction, latency of the single-precision FTRC instruction is 1 cycle.
Rev. 1.0, 02/03, page 98 of 1294
Section 6 Memory Management Unit (MMU)
This LSI supports an 8-bit address space identifier, a 32-bit virtual address space, and a 29-bit external memory space. Address translation from virtual addresses to physical addresses is enabled by the memory management unit (MMU) in this LSI. The MMU performs high-speed address translation by caching user-created address translation table information in an address translation buffer (translation lookaside buffer: TLB). This LSI has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries. UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation, with four page sizes (1, 4, and 64 kbytes, and 1 Mbyte) supported. It is possible to set the virtual address space access right and implement memory protection independently for privileged mode and user mode.
6.1
Overview of the MMU
The MMU was conceived as a means of making efficient use of physical memory. As shown in figure 6.1, when a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory, but if the process increases in size to the point where it does not fit into physical memory, it becomes necessary to divide the process into smaller parts, and map the parts requiring execution onto physical memory as occasion arises ((1) in figure 6.1). Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process. The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden ((2) in figure 6.1). With a virtual memory system, the size of the available virtual memory is much larger than the actual physical memory, and processes are mapped onto this virtual memory. Thus processes only have to consider their operation in virtual memory, and mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally managed by the OS, and physical memory switching is carried out so as to enable the virtual memory required by a process to be mapped smoothly onto physical memory. Physical memory switching is performed via secondary storage, etc. The virtual memory system that came into being in this way works to best effect in a time sharing system (TSS) that allows a number of processes to run simultaneously ((3) in figure 6.1). Running a number of processes in a TSS did not increase efficiency since each process had to take account of physical memory mapping. Efficiency is improved and the load on each process reduced by the use of a virtual memory system ((4) in figure 6.1). In this virtual memory system, virtual memory is allocated to each process. The task of the MMU is to map a number of virtual memory areas onto physical memory in an efficient manner. It is also provided with memory protection functions to prevent a process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may happen that the translation information has not been recorded in the MMU, or the virtual memory of a different process is accessed by mistake. In such cases, the MMU will generate an
Rev. 1.0, 02/03, page 99 of 1294
exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could be implemented by software alone, having address translation performed by software each time a process accessed physical memory would be very inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB) is provided by hardware, and frequently used address translation information is placed here. The TLB can be described as a cache for address translation information. However, unlike a cache, if address translation fails--that is, if an exception occurs--switching of the address translation information is normally performed by software. Thus memory management can be performed in a flexible manner by software. There are two methods by which the MMU can perform mapping from virtual memory to physical memory: the paging method, using fixed-length address translation, and the segment method, using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space called a page (usually from 1 to 64 kbytes in size). In the following descriptions, the address space in virtual memory in this LSI is referred to as virtual address space, and the address space in physical memory as physical address space.
Rev. 1.0, 02/03, page 100 of 1294
Virtual Memory Physical Memory Process 1 Process 1 Physical Memory Process 1
MMU Physical Memory
(1)
(2)
Process 1
Physical Memory
Process 1
Virtual Memory MMU Physical Memory
Process 2
Process 2
Process 3
Process 3
(3)
(4)
Figure 6.1 Role of the MMU 6.1.1 Address Spaces
(1) Physical Address Space This LSI supports a 32-bit physical address space, and can access a 4-Gbyte address space. When the AT bit in MMUCR is cleared to 0 and the MMU is disabled, the address space is this physical address space. The physical address space is divided into a number of areas, as shown in figure 6.2. The physical address space is permanently mapped onto a 29-bit external memory space; this correspondence can be implemented by ignoring the upper 3 bits of the physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1 to P4 areas (except the store queue area) in user mode will cause an address error.
Rev. 1.0, 02/03, page 101 of 1294
External memory space H'0000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'0000 0000
P0 area Cacheable
U0 area Cacheable
H'8000 0000 H'A000 0000 H'C000 0000 H'E000 0000 H'FFFF FFFF
P1 area Cacheable P2 area Non-cacheable P3 area Cacheable P4 area Non-cacheable Privileged mode Store queue area Address error User mode Address error
H'8000 0000
H'E000 0000 H'E400 0000 H'FFFF FFFF
Figure 6.2 Physical Address Space (AT = 0 in MMUCR) Access to a PCMCIA interface area by the CPU in this LSI is always performed using the values of the SA and TC bits in PTEA. Access to a PCMCIA interface area by the DMAC is always performed using the SSAn, DSAn, STC, and DTC values in CHCRn of the DMAC. For details, see section 11, Direct Memory Access Controller (DMAC). P0, P1, P3, and U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or not the cache is used is determined by the CCR setting. When the cache is used, switching between the copy-back method and the write-through method for write accesses is specified by the WT bit in CCR, except for in the P1 area. Switching in the P1 area is determined by the CB bit in CCR. Replacing the upper 3 bits of an address in these areas with 0s gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area will exist in these areas. P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, clearing the upper 3 bits of an address to 0 gives the corresponding external memory space address. However, since area 7 in the external memory space is a reserved area, a reserved area will exist in this area. P4 Area: The P4 area is mapped onto on-chip I/O memory. The P4 area cannot be accessed using the cache. The P4 area is shown in detail in figure 6.3.
Rev. 1.0, 02/03, page 102 of 1294
H'E000 0000 H'E400 0000
Store queue Reserved area
H'F000 0000 H'F100 0000 H'F200 0000 H'F300 0000 H'F400 0000 H'F500 0000 H'F600 0000 H'F700 0000 H'F800 0000
Instruction cache address array Instruction cache data array Instruction TLB address array Instruction TLB data arrays 1 and 2 Operand cache address array Operand cache data array Unified TLB address array Unified TLB data arrays 1 and 2
Reserved area
H'FC00 0000 Control register area H'FFFF FFFF
Figure 6.3 P4 Area The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues (SQs). When the MMU is disabled (AT bit in MMUCR = 0), the SQ access right is specified by the SQMD bit in MMUCR. For details, see section 7.7, Store Queues. The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache address array. For details, see section 7.6.1, IC Address Array. The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data array. For details, see section 7.6.2, IC Data Array. The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB address array. For details, see section 6.6.1, ITLB Address Array. The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data arrays 1 and 2. For details, see section 6.6.2, ITLB Data Array 1, and section 6.6.3, ITLB Data Array 2. The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address array. For details, see section 7.6.3, OC Address Array. The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data array. For details, see section 7.6.4, OC Data Array.
Rev. 1.0, 02/03, page 103 of 1294
The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address array. For details, see section 6.6.4, UTLB Address Array. The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1 and 2. For details, see section 6.6.5, UTLB Data Array 1, and section 6.6.6, UTLB Data Array 2. The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register area. (2) External Memory Space This LSI supports a 29-bit external memory space. The external memory space is divided into eight areas as shown in figure 6.4. Areas 0 to 6 relate to memory, such as SRAM, synchronous DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 10, Bus State Controller (BSC).
H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF
Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 (reserved area)
Figure 6.4 External Memory Space
Rev. 1.0, 02/03, page 104 of 1294
(3) Virtual Address Space Setting the AT bit in MMUCR to 1 enables the P0, P3, and U0 areas of the physical address space in this LSI to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be increased to a maximum of 256. This is called the virtual address space. Mapping from the virtual address space to the 29-bit external memory space is carried out using the TLB. Only when area 7 in the external memory space is accessed using the virtual address space, addresses H'1C00 0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control register area in the physical address space. The virtual address space is shown in figure 6.5. When the P0, P3, and U0 areas are mapped onto a PCMCIA interface area by means of the TLB in the cache enabled state, either the WT bit in CCR must be set to 1 or the C bit in PTEL must be cleared to 0 for that page. In this case, access to the area is performed using the SA and TC bit values specified in page units for each TLB page. Note that the CPU cannot access a PCMCIA interface area through access of the P1, P2, or P4 area. Access to a PCMCIA interface area by the DMAC is always performed using the SSAn, DSAn, STC, and DTC values in CHCRn of the DMAC. For details, see section 11, Direct Memory Access Controller (DMAC).
Rev. 1.0, 02/03, page 105 of 1294
256
256 External memory space Area 0 Area 1 Area 2 P0 area Cacheable Address translation possible Area 3 Area 4 Area 5 Area 6 Area 7 U0 area Cacheable Address translation possible
P1 area Cacheable Address translation not possible P2 area Non-cacheable Address translation not possible P3 area Cacheable Address translation possible P4 area Non-cacheable Address translation not possible Privileged mode Store queue area Address error User mode
Address error
Figure 6.5 Virtual Address Space (AT = 1 in MMUCR) P0, P3, and U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and address translation using the TLB. These areas can be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte page units. When CCR is in the cache enabled state and the TLB cacheability bit (C bit) is 1, accesses can be performed using the cache. In write accesses to the cache, switching between the copy-back method and the write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page units. Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in the external memory space are allocated to the control register area. This enables control registers to be accessed from the U0 area even in user mode. In this case, the C bit for the corresponding page must be cleared to 0. P1, P2, and P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4 area (except for the store queue area). Accesses to these areas are the same as for the physical address space. The store queue area can be mapped onto any external memory space by the MMU. However, operation in the case of an exception differs from that for normal P0, U0, and P3 areas. For details, see section 7.7, Store Queues.
Rev. 1.0, 02/03, page 106 of 1294
(4) On-Chip RAM Space In this LSI, half of the operand cache can be used as on-chip RAM. This can be done by changing the CCR settings. When the operand cache is used as on-chip RAM (ORA bit in CCR = 1), addresses H'7C00 0000 to H'7FFF FFFF in the P0 and U0 areas are an on-chip RAM area. Data accesses (byte/word/longword/quadword) can be used in this area. This area can only be used in RAM mode. (5) Address Translation When the MMU is used, the virtual address space is divided into units called pages, and translation to physical addresses is carried out in these page units. The address translation table in external memory contains the physical addresses corresponding to virtual addresses and additional information such as memory protection codes. Fast address translation is achieved by caching the contents of the address translation table located in external memory into the TLB. In this LSI, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the event of an access to an area other than the P4 area, the accessed virtual address is translated to a physical address. If the virtual address belongs to the P1 or P2 area, the physical address is uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3 area, the TLB is searched using the virtual address, and if the virtual address is recorded in the TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and processing switches to the TLB miss exception handling routine. In the TLB miss exception handling routine, the address translation table in external memory is searched, and the corresponding physical address and page management information are recorded in the TLB. After the return from the exception handling routine, the instruction which caused the TLB miss exception is re-executed.
Rev. 1.0, 02/03, page 107 of 1294
(6) Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems, single virtual memory and multiple virtual memory, either of which can be selected with the SV bit in MMUCR. In the single virtual memory system, a number of processes run simultaneously, using virtual address space on an exclusive basis, and the physical address corresponding to a particular virtual address is uniquely determined. In the multiple virtual memory system, a number of processes run while sharing the virtual address space, and particular virtual addresses may be translated into different physical addresses depending on the process. The only difference between the single virtual memory and multiple virtual memory systems in terms of operation is in the TLB address comparison method (see section 6.3.3, Address Translation Method). (7) Address Space Identifier (ASID) In multiple virtual memory mode, an 8-bit address space identifier (ASID) is used to distinguish between multiple processes running simultaneously while sharing the virtual address space. Software can set the 8-bit ASID of the currently executing process in PTEH in the MMU. The TLB does not have to be purged when processes are switched by means of ASID. In single virtual memory mode, ASID is used to provide memory protection for multiple processes running simultaneously while using the virtual address space on an exclusive basis. Note: Two or more entries with the same virtual page number (VPN) but different ASID must not be set in the TLB simultaneously as a single virtual memory mode setting.
6.2
Register Descriptions
The following registers are related to MMU processing. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 6.1 Register Configuration (1)
Abbrev. PTEH PTEL R/W R/W R/W R/W R/W R/W R/W P4 Address H'FF00 0000 H'FF00 0004 H'FF00 0034 H'FF00 0008 H'FF00 000C H'FF00 0010 Area 7 Address Size H'1F00 0000 H'1F00 0004 H'1F00 0034 H'1F00 0008 H'1F00 000C H'1F00 0010 32 32 32 32 32 32 Sync Clock Ick Ick Ick Ick Ick Ick
Register Name Page table entry high register Page table entry low register
Page table entry assistance register PTEA Translation table base register TLB exception address register MMU control register TTB TEA MMUCR
Rev. 1.0, 02/03, page 108 of 1294
Table 6.1
Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI Undefined Undefined Undefined Undefined Undefined Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Undefined Undefined Undefined Retained Standby by Sleep Software by Sleep /Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained
Register Name Page table entry high register Page table entry low register Page table entry assistance register Translation table base register TLB exception address register MMU control register
Abbrev. PTEH PTEL PTEA TTB TEA MMUCR
H'0000 0000 H'0000 0000 Retained
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
6.2.1
Page Table Entry High Register (PTEH)
PTEH can be accessed in longwords from H'FF00 0000 in the P4 area and from H'1F00 0000 in area 7. PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an MMU exception or address error exception occurs, the VPN of the virtual address at which the exception occurred is set in the VPN bit by hardware. VPN varies according to the page size, but the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting can also be carried out by software. The number of the currently executing process is set in the ASID bit by software. ASID is not updated by hardware. VPN and ASID are recorded in the UTLB by means of the LDLTB instruction. After the ASID field in PTEH has been rewritten, a branch instruction to the P0, P3, or U0 area that uses the updated ASID value should be located at least six instructions after the PTEH update instruction.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 VPN R/W 15 R/W R/W 14 R/W R/W 13 R/W R/W 12 VPN R/W R/W R/W R/W 11 R/W 10 R/W 9 0 R R/W 8 0 R R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 ASID R/W R/W R/W R/W R/W R/W 3 R/W 2 R/W 1 R/W 0 23 22 21 20 19 18 17 16
Rev. 1.0, 02/03, page 109 of 1294
Bit
Bit Name
Initial Value All 0
R/W R/W R
Description Virtual Page Number Reserved These bits are always read as 0. The write value should always be 0. Address Space Identifier
31 to 10 VPN 9, 8
7 to 0
ASID
R/W
6.2.2
Page Table Entry Low Register (PTEL)
PTEL can be accessed in longwords from H'FF00 0004 in the P4 area and from H'1F00 0004 in area 7. PTEL is used to hold the physical page number and page management information to be recorded in the UTLB by means of the LDTLB instruction. The contents of this register are not changed unless a software directive is issued.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 R/W 30 0 R 14 R/W 29 0 R 13 PPN R/W R/W R/W R/W R/W 12 R/W 11 R/W 10 R/W 9 0 R R/W 8 V R/W 28 27 26 25 24 23 PPN R/W 7 SZ1 R/W R/W 6 PR1 R/W R/W 5 PR0 R/W R/W 4 SZ0 R/W R/W 3 C R/W R/W 2 D R/W R/W 1 SH R/W R/W 0 WT R/W 22 21 20 19 18 17 16
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Physical Page Number Reserved This bit is always read as 0. The write value should always be 0. Page Management Information For details, see section 6.3, TLB Functions.
31 to 29
28 to 10 PPN 9
0
R/W R
8 7 6 5 4 3 2 1 0
V SZ1 PR1 PR0 SZ0 C D SH WT

R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 110 of 1294
6.2.3
Page Table Entry Assistance Register (PTEA)
PTEA can be accessed in longwords from H'FF00 0034 in the P4 area and from H'1F00 0034 in area 7. PTEA is used to store assistance bits for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing access from the CPU in this LSI to the PCMCIA interface area with the AT bit in MMUCR cleared to 0, access is always performed using the values of the SA and TC bits in this register. When the AT bit in MMUCR is cleared to 0 in this LSI, the PCMCIA interface area cannot be accessed. The access to a PCMCIA interface area by the DMAC is always performed using the SSAn, DSAn, STC, and DTC values in CHCRn of the DMAC. The contents of this register are not changed unless a software directive is issued.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 TC R/W 18 0 R 2 SA2 R/W 17 0 R 1 SA1 R/W 16 0 R 0 SA0 R/W
Bit 31 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. PCMCIA Access Assistance Bits For details, see section 6.3, TLB Functions.
3 2 1 0
TC SA2 SA1 SA0

R/W R/W R/W R/W
6.2.4
Translation Table Base Register (TTB)
TTB can be accessed in longwords from H'FF00 0008 in the P4 area and from H'1F00 0008 in area 7. TTB is used, for example, to hold the base address of the currently used page table. The contents of TTB are not changed unless a software directive is issued. This register can be used freely by software.
Rev. 1.0, 02/03, page 111 of 1294
Bit: Initial value: R/W: Bit: Initial value: R/W:
31 R/W 15 R/W
30 R/W 14 R/W
29 R/W 13 R/W
28 R/W 12 R/W
27 R/W 11 R/W
26 R/W 10 R/W
25 R/W 9 R/W
24 TTB R/W 8 TTB R/W
23 R/W 7 R/W
22 R/W 6 R/W
21 R/W 5 R/W
20 R/W 4 R/W
19 R/W 3 R/W
18 R/W 2 R/W
17 R/W 1 R/W
16 R/W 0 R/W
6.2.5
TLB Exception Address Register (TEA)
TEA can be accessed in longwords from H'FF00 000C in the P4 area and from H'1F00 000C in area 7. After an MMU exception or address error exception occurs, the virtual address at which the exception occurred is set in TEA by hardware. The contents of this register can be changed by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R/W 15 R/W 30 R/W 14 R/W 29 28 27 26 25 24 23 22 21 20 19 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W
Virtual address at which MMU exception or address error occurred R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 13 12 11 10 9 8 7 6 5 4 3
Virtual address at which MMU exception or address error occurred R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
6.2.6
MMU Control Register (MMUCR)
MMUCR can be accessed in longwords from H'FF00 0010 in the P4 area and from H'1F00 0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an instruction that performs data access to the P0, P3, U0, or store queue area should be located at least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0, P3, or U0 area should be located at least eight instructions after the MMUCR update instruction. MMUCR contents can be changed by software. However, the LRUI bits and URC bits may also be updated by hardware.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 LRUI 0 R/W 15 0 R/W 14 0 R/W 13 URC 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 12 0 R/W 11 0 R/W 10 28 27 26 25 0 R 9 SQMD 0 R/W 24 0 R 8 SV 0 R/W 0 R/W 7 0 R 0 R/W 6 0 R 23 22 21 URB 0 R/W 5 0 R 0 R/W 4 0 R 0 R/W 3 0 R 0 R/W 2 TI 0 R/W 20 19 18 17 0 R 1 0 R 16 0 R 0 AT 0 R/W
Rev. 1.0, 02/03, page 112 of 1294
Bit
Bit Name
Initial Value All 0
R/W R/W
Description Least Recently Used ITLB These bits indicate the ITLB entry to be replaced. The LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits. LRUI is updated by means of the algorithm shown below. x means that updating is not performed. 000xxx: ITLB entry 0 is used 1xx00x: ITLB entry 1 is used x1x1x0: ITLB entry 2 is used xx1x11: ITLB entry 3 is used xxxxxx: Other than above When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by an ITLB miss. Ensure that values for which "Setting prohibited" is indicated below are not set at the discretion of software. After a power-on or manual reset, the LRUI bits are initialized to 0, and therefore a prohibited setting is never made by a hardware update. x means "don't care". 111xxx: ITLB entry 0 is updated 0xx11x: ITLB entry 1 is updated x0x0x1: ITLB entry 2 is updated xx0x00: ITLB entry 3 is updated Other than above: Setting prohibited
31 to 26 LRUI
25, 24
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. UTLB Replace Boundary These bits indicate the UTLB entry boundary at which replacement is to be performed. Valid only when URB > 0. Reserved These bits are always read as 0. The write value should always be 0.
23 to 18 URB
All 0
R/W
17, 16
All 0
R
Rev. 1.0, 02/03, page 113 of 1294
Bit
Bit Name
Initial Value All 0
R/W R/W
Description UTLB Replace Counter These bits serve as a random counter for indicating the UTLB entry for which replacement is to be performed with an LDTLB instruction. This bit is incremented each time the UTLB is accessed. If URB > 0, URC is cleared to 0 when the condition URC = URB is satisfied. Also note that if a value is written to URC by software which results in the condition of URC > URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB instruction. Store Queue Mode Bit Specifies the right of access to the store queues. 0: User/privileged access possible 1: Privileged access possible (address error exception in case of user access)
15 to 10 URC
9
SQMD
0
R/W
8
SV
0
R/W
Single Virtual Memory Mode/Multiple Virtual Memory Mode Switching Bit When this bit is changed, ensure that 1 is also written to the TI bit. 0: Multiple virtual memory mode 1: Single virtual memory mode
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. TLB Invalidate Bit Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit is always read as 0. Reserved This bit is always read as 0. The write value should always be 0. Address Translation Enable Bit These bits enable or disable the MMU. 0: MMU disabled 1: MMU enabled MMU exceptions are not generated when the AT bit is 0. In the case of software that does not use the MMU, the AT bit should be cleared to 0.
2
TI
0
R/W
1
0
R
0
AT
0
R/W
Rev. 1.0, 02/03, page 114 of 1294
6.3
6.3.1
TLB Functions
Unified TLB (UTLB) Configuration
The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. As a table of address translation information to be recorded in the ITLB in the event of an ITLB miss The UTLB is so called because of its use for the above two purposes. Information in the address translation table located in external memory is cached into the UTLB. The address translation table contains virtual page numbers and address space identifiers, and corresponding physical page numbers and page management information. Figure 6.6 shows the UTLB configuration. The UTLB consists of 64 fully-associative type entries. Figure 6.7 shows the relationship between the page size and address format.
Entry 0 Entry 1 Entry 2
ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Entry 63
ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR [1:0] D WT SA [2:0] TC
Figure 6.6 UTLB Configuration
Rev. 1.0, 02/03, page 115 of 1294
* 1-kbyte page 31 Virtual address 10 9 VPN * 4-kbyte page 31 Virtual address 12 11 VPN * 64-kbyte page 31 Virtual address 16 15 VPN Offset 0 28 Physical address 16 15 PPN Offset 0 Offset 0 28 Physical address 12 11 PPN Offset 0 Offset 0 28 Physical address 10 9 PPN Offset 0
* 1-Mbyte page Virtual address 31 20 19 VPN Offset
0
28 PPN
Physical address 20 19 Offset
0
Figure 6.7 Relationship between Page Size and Address Format Legend: * VPN: Virtual page number For 1-kbyte page: Upper 22 bits of virtual address For 4-kbyte page: Upper 20 bits of virtual address For 64-kbyte page: Upper 16 bits of virtual address For 1-Mbyte page: Upper 12 bits of virtual address * ASID: Address space identifier Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, this identifier is compared with the ASID in PTEH when address comparison is performed. * SH: Share status bit When 0, pages are not shared by processes. When 1, pages are shared by processes. * SZ[1:0]: Page size bits Specify the page size. 00: 1-kbyte page 01: 4-kbyte page 10: 64-kbyte page 11: 1-Mbyte page
Rev. 1.0, 02/03, page 116 of 1294
* V: Validity bit Indicates whether the entry is valid. 0: Invalid 1: Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. * PPN: Physical page number Upper 22 bits of the physical address of the physical page number. With a 1-kbyte page, PPN[28:10] are valid. With a 4-kbyte page, PPN[28:12] are valid. With a 64-kbyte page, PPN[28:16] are valid. With a 1-Mbyte page, PPN[28:20] are valid. The synonym problem must be taken into account when setting the PPN (see section 6.4.5, Avoiding Synonym Problems). * PR[1:0]: Protection key data 2-bit data expressing the page access right as a code. 00: Can be read from only in privileged mode 01: Can be read from and written to in privileged mode 10: Can be read from only in privileged or user mode 11: Can be read from and written to in privileged mode or user mode * C: Cacheability bit Indicates whether a page is cacheable. 0: Not cacheable 1: Cacheable When the control register space is mapped, this bit must be cleared to 0. When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0 or set the WT bit to 1. * D: Dirty bit Indicates whether a write has been performed to a page. 0: Write has not been performed 1: Write has been performed * WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-through mode
Rev. 1.0, 02/03, page 117 of 1294
When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or clear the C bit to 0. * SA[2:0]: Space attribute bits Valid only when the page is mapped onto PCMCIA connected to area 5 or 6. 000: Undefined 001: Variable-size I/O space (base size according to IOIS16 signal) 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit shared memory space 101: 16-bit shared memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space * TC: Timing control bit Used to select wait control register bits in the bus control unit for areas 5 and 6. 0: WCR2 (A5W2 to A5W0) and PCR (A5PCW1 to A5PCW0, A5TED2 to A5TED0, A5TEH2 to A5TEH0) are used 1: WCR2 (A6W2 to A6W0) and PCR (A6PCW1 to A6PCW0, A6TED2 to A6TED0, A6TEH2 to A6TEH0) are used 6.3.2 Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access. Information in the address translation table located in the UTLB is cached into the ITLB. Figure 6.8 shows the ITLB configuration. The ITLB consists of four fully-associative type entries.
Entry 0 ASID [7:0] VPN [31:10] V Entry 1 ASID [7:0] VPN [31:10] V Entry 2 ASID [7:0] VPN [31:10] V Entry 3 ASID [7:0] VPN [31:10] V
PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC PPN [28:10] SZ [1:0] SH C PR SA [2:0] TC
Notes: 1. The D and WT bits are not supported. 2. There is only one PR bit, corresponding to the upper bit of the PR bits in the UTLB.
Figure 6.8 ITLB Configuration
Rev. 1.0, 02/03, page 118 of 1294
6.3.3
Address Translation Method
Figure 6.9 shows a flowchart of a memory access using the UTLB.
Data access to virtual address (VA) VA is in P4 area On-chip I/O access VA is in P2 area 0 VA is in P1 area CCR.OCE? 1 0 CCR.CB? 1 No CCR.WT? 1 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes No VPNs match and V = 1 Yes No VPNs match and ASIDs match and V=1 Yes Only one entry matches Yes SR.MD? 0 (User) PR? 10 R/W? R Data TLB protection violation exception 1 (Privileged) PR? 01 or 11 W W 1 R/W? R Data TLB multiple hit exception No No VA is in P0, U0, or P3 area MMUCR.AT = 1 Yes 0
Data TLB miss exception
00 or 01 W
11 R/W? R D? 0
00 or 10 R/W? R Data TLB protection violation exception W
Initial page write exception
C=1 and CCR.OCE = 1 Yes Cache access in copy-back mode 0 WT? 1 Cache access in write-through mode
No
Memory access (Non-cacheable)
Figure 6.9 Flowchart of Memory Access Using UTLB
Rev. 1.0, 02/03, page 119 of 1294
Figure 6.10 shows a flowchart of a memory access using the ITLB.
Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area 0 VA is in P1 area No CCR.ICE? 1 MMUCR.AT = 1 Yes VA is in P0, U0, or P3 area
Access prohibited
No
SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) Yes
No
VPNs match and V = 1 Yes
No
VPNs match and ASIDs match and V=1 Yes
Search UTLB Yes
Hardware ITLB miss handling Record in ITLB
Only one entry matches Yes
No
Match? No
Instruction TLB miss exception 0
SR.MD? 0 (User) 1 (Privileged) PR? 1 Instruction TLB multiple hit exception
Instruction TLB protection violation exception
C=1 and CCR.ICE = 1 Yes Cache access
No
Memory access (Non-cacheable)
Figure 6.10 Flowchart of Memory Access Using ITLB
Rev. 1.0, 02/03, page 120 of 1294
6.4
6.4.1
MMU Functions
MMU Hardware Management
This LSI supports the following MMU functions. 1. The MMU decodes the virtual address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 2. The MMU determines the cache access status on the basis of the page management information read during address translation (C, WT, SA, and TC bits). 3. If address translation cannot be performed normally in a data access or instruction access, the MMU notifies software by means of an MMU exception. 4. If address translation information is not recorded in the ITLB in an instruction access, the MMU searches the UTLB. If the necessary address translation information is recorded in the UTLB, the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR. 6.4.2 MMU Software Management
Software processing for the MMU consists of the following: 1. Setting of MMU-related registers. Some registers are also partially updated by hardware automatically. 2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. Deleting or reading UTLB/ITLB entries is enabled by accessing the memory-mapped UTLB/ITLB. 3. MMU exception handling. When an MMU exception occurs, processing is performed based on information set by hardware. 6.4.3 MMU Instruction (LDTLB)
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the contents of PTEH, PTEL, and PTEA to the UTLB entry indicated by the URC bit in MMUCR. ITLB entries are not updated by the LDTLB instruction, and therefore address translation information purged from the UTLB entry may still remain in the ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in figure 6.11.
Rev. 1.0, 02/03, page 121 of 1294
MMUCR 31
LRUI
26252423
-- URB
18171615
-- URC
10 9 8 7
SV --
3210
TI -- AT
Entry specification
SQMD
PTEL 31 2928 PTEH 31 VPN
--
PPN
10 9 8 7 6 5 4 3 2 1 0
--V
SZ1 PR[1:0] SZ0 C
D SH WT
10 9 8 7 -- ASID
0 PTEA 31
--
432
0
TC SA[2:0]
Write
Entry 0 Entry 1 Entry 2
ASID [7:0] ASID [7:0] ASID [7:0]
VPN [31:10] VPN [31:10] VPN [31:10]
V V V
PPN [28:10] PPN [28:10] PPN [28:10]
SZ [1:0] SZ [1:0] SZ [1:0]
SH C PR [1:0] SH C PR [1:0] SH C PR [1:0]
D D D
WT SA [2:0] WT SA [2:0] WT SA [2:0]
TC TC TC
Entry 63
ASID [7:0]
VPN [31:10]
V
PPN [28:10] UTLB
SZ [1:0]
SH C PR [1:0]
D
WT SA [2:0]
TC
Figure 6.11 Operation of LDTLB Instruction 6.4.4 Hardware ITLB Miss Handling
In an instruction access, this LSI searches the ITLB. If it cannot find the necessary address translation information (ITLB miss occurred), the UTLB is searched by hardware, and if the necessary address translation information is present, it is recorded in the ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address translation information is not found in the UTLB search, an instruction TLB miss exception is generated and processing passes to software.
Rev. 1.0, 02/03, page 122 of 1294
6.4.5
Avoiding Synonym Problems
When 1- or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses are mapped onto a single physical address, the same physical address data is recorded in a number of cache entries, and it becomes impossible to guarantee data integrity. This problem does not occur with the instruction TLB and instruction cache because data is only read in these cases. In this LSI, entry specification is performed using bits 13 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits 13 to 10 of the virtual address in the case of a 1-kbyte page, and bits 13 and 12 of the virtual address in the case of a 4-kbyte page, are subject to address translation. As a result, bits 13 to 10 of the physical address after translation may differ from bits 13 of 10 of the virtual address. Consequently, the following restrictions apply to the recording of address translation information in UTLB entries. * When address translation information whereby a number of 1-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN[13:10] values are the same. * When address translation information whereby a number of 4-kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB, ensure that the VPN[13:12] values are the same. * Do not use 1-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. * Do not use 4-kbyte page UTLB entry physical addresses with UTLB entries of a different page size. The above restrictions apply only when performing accesses using the cache. When cache index mode is used, VPN[25] is used for the entry address instead of VPN[13], and therefore the above restrictions apply to VPN[25]. Note: When multiple items of address translation information use the same physical memory to provide for future expansion of the SuperH RISC engine family, ensure that the VPN[20:10] values are the same. Also, do not use the same physical address for address translation information of different page sizes.
Rev. 1.0, 02/03, page 123 of 1294
6.5
MMU Exceptions
There are seven MMU exceptions: instruction TLB multiple hit exception, instruction TLB miss exception, instruction TLB protection violation exception, data TLB multiple hit exception, data TLB miss exception, data TLB protection violation exception, and initial page write exception. Refer to figures 6.9 and 6.10 for the conditions under which each of these exceptions occurs. 6.5.1 Instruction TLB Multiple Hit Exception
An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the virtual address to which an instruction access has been made. If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit exception will result. When an instruction TLB multiple hit exception occurs, a reset is executed and cache coherency is not guaranteed. Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated.
Rev. 1.0, 02/03, page 124 of 1294
6.5.2
Instruction TLB Miss Exception
An instruction TLB miss exception occurs when address translation information for the virtual address to which an instruction access is made is not found in the UTLB entries by the hardware ITLB miss handling routine. The instruction TLB miss exception processing carried out by hardware and software is shown below. This is the same as the processing for a data TLB miss exception. Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the instruction TLB miss exception handling routine. Software Processing (Instruction TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
Rev. 1.0, 02/03, page 125 of 1294
6.5.3
Instruction TLB Protection Violation Exception
An instruction TLB protection violation exception occurs when, even though an ITLB entry contains address translation information matching the virtual address to which an instruction access is made, the actual access type is not permitted by the access right specified by the PR bit. The instruction TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an instruction TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the instruction TLB protection violation exception handling routine. Software Processing (Instruction TLB Protection Violation Exception Handling Routine): Resolve the instruction TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
Rev. 1.0, 02/03, page 126 of 1294
6.5.4
Data TLB Multiple Hit Exception
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual address to which a data access has been made. A data TLB multiple hit exception is also generated if multiple hits occur when the UTLB is searched in hardware ITLB miss handling. When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted. Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the following processing: 1. Sets the virtual address at which the exception occurred in TEA. 2. Sets exception code H'140 in EXPEVT. 3. Branches to the reset handling routine (H'A000 0000). Software Processing (Reset Routine): The UTLB entries which caused the multiple hit exception are checked in the reset handling routine. This exception is intended for use in program debugging, and should not normally be generated. 6.5.5 Data TLB Miss Exception
A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries. The data TLB miss exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB miss exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1.
Rev. 1.0, 02/03, page 127 of 1294
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and starts the data TLB miss exception handling routine. Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible for searching the external memory page table and assigning the necessary page table entry. Software should carry out the following processing in order to find and assign the necessary page table entry. 1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table entry recorded in the external memory address translation table. If necessary, the values of the SA and TC bits should be written to PTEA. 2. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 4. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 6.5.6 Data TLB Protection Violation Exception
A data TLB protection violation exception occurs when, even though a UTLB entry contains address translation information matching the virtual address to which a data access is made, the actual access type is not permitted by the access right specified by the PR bit. The data TLB protection violation exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of a data TLB protection violation exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVCA.L: write). 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
Rev. 1.0, 02/03, page 128 of 1294
8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the data TLB protection violation exception handling routine. Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve the data TLB protection violation, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction. 6.5.7 Initial Page Write Exception
An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual address to which a data access (write) is made, and the access is permitted. The initial page write exception processing carried out by hardware and software is shown below. Hardware Processing: In the event of an initial page write exception, hardware carries out the following processing: 1. Sets the VPN of the virtual address at which the exception occurred in PTEH. 2. Sets the virtual address at which the exception occurred in TEA. 3. Sets exception code H'080 in EXPEVT. 4. Sets the PC value indicating the address of the instruction at which the exception occurred in SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the delayed branch instruction in SPC. 5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are saved in SGR. 6. Sets the MD bit in SR to 1, and switches to privileged mode. 7. Sets the BL bit in SR to 1, and masks subsequent exception requests. 8. Sets the RB bit in SR to 1. 9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and starts the initial page write exception handling routine.
Rev. 1.0, 02/03, page 129 of 1294
Software Processing (Initial Page Write Exception Handling Routine): Software is responsible for the following processing: 1. Retrieve the necessary page table entry from external memory. 2. Write 1 to the D bit in the external memory page table entry. 3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table entry recorded in external memory. If necessary, the values of the SA and TC bits should be written to PTEA. 4. When the entry to be replaced in entry replacement is specified by software, write that value to the URC bits in MMUCR. If URC is greater than URB at this time, the value should be changed to an appropriate value after issuing an LDTLB instruction. 5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the UTLB. 6. Finally, execute the exception handling return instruction (RTE), terminate the exception handling routine, and return control to the normal flow. The RTE instruction should be issued at least one instruction after the LDTLB instruction.
6.6
Memory-Mapped TLB Configuration
To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read from and written to by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. A branch to an area other than the P2 area should be made at least eight instructions after this MOV instruction. The ITLB and UTLB are allocated to the P4 area in the physical address space. VPN, V, and ASID in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN, D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address array side and the data array side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined.
Rev. 1.0, 02/03, page 130 of 1294
6.6.1
ITLB Address Array
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, V, and ASID to be written to the address array are specified in the data field. In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID. The following two kinds of operation can be used on the ITLB address array: 1. ITLB address array read VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB address array write VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to the entry set in the address field.
24 23 31 Address field 1 1 1 1 0 0 1 0 31 Data field VPN VPN: Virtual page number V: Validity bit E: Entry 10 9 8 7 E 10 9 8 7 V ASID 0 0
ASID: Address space identifier : Reserved bits (write value should be 0, and read value is undefined )
Figure 6.12 Memory-Mapped ITLB Address Array
Rev. 1.0, 02/03, page 131 of 1294
6.6.2
ITLB Data Array 1
ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are specified in the data field. In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1 and the entry is specified by bits [9:8]. In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bit [6] indicates PR, bit [3] indicates C, and bit [1] indicates SH. The following two kinds of operation can be used on ITLB data array 1: 1. ITLB data array 1 read PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field. 2. ITLB data array 1 write PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry corresponding to the entry set in the address field.
24 23 31 Address field 1 1 1 1 0 0 1 1 0 31 30 29 28 Data field PPN 10 9 8 7 E 10 9 8 7 6 5 4 3 2 1 0 V C 0
PPN: V: E: SZ[1:0]:
Physical page number Validity bit Entry Page size bits
PR: C: SH: :
SZ1 SZ0 PR SH Protection key data Cacheability bit Share status bit Reserved bits (write value should be 0, and read value is undefined )
Figure 6.13 Memory-Mapped ITLB Data Array 1
Rev. 1.0, 02/03, page 132 of 1294
6.6.3
ITLB Data Array 2
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2 and the entry is specified by bits [9:8]. In the data field, bit [3] indicates TC and bits [2:0] indicate SA. The following two kinds of operation can be used on ITLB data array 2: 1. ITLB data array 2 read SA and TC are read into the data field from the ITLB entry corresponding to the entry set in the data field. 2. ITLB data array 2 write SA and TC specified in the data field are written to the ITLB entry corresponding to the entry set in the address field.
31 24 23 Address field 1 1 1 1 0 0 1 1 1 31 Data field TC TC: Timing control bit SA[2:0]: Space attribute bits E: Entry : Reserved bits (write value should be 0, SA[2:0] and read value is undefined ) 10 9 8 7 E 4320 0
Figure 6.14 Memory-Mapped ITLB Data Array 2 6.6.4 UTLB Address Array
The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and VPN, D, V, and ASID to be written to the address array are specified in the data field.
Rev. 1.0, 02/03, page 133 of 1294
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array and the entry is specified by bits [13:8]. Bit [7] that is the association bit (A bit) in the address field specifies whether address comparison is performed in a write to the UTLB address array. In the data field, bits [31:10] indicate VPN, bit [9] indicates D, bit [8] indicates V, and bits [7:0] indicate ASID. The following three kinds of operation can be used on the UTLB address array: 1. UTLB address array read VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. UTLB address array write (non-associative) VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. UTLB address array write (associative) When a write is performed with the A bit in the address field set to 1, comparison of all the UTLB entries is carried out using the VPN specified in the data field and ASID in PTEH. The usual address comparison rules are followed, but if a UTLB miss occurs, the result is no operation, and an exception is not generated. If the comparison identifies a UTLB entry corresponding to the VPN specified in the data field, D and V specified in the data field are written to that entry. If there is more than one matching entry, a data TLB multiple hit exception occurs. This associative operation is simultaneously carried out on the ITLB, and if a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB comparison results in no operation, a write to the ITLB side only is performed as long as there is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is also written to the ITLB.
24 23 31 Address field 1 1 1 1 0 1 1 0 31 Data field VPN: V: E: D: Virtual page number Validity bit Entry Dirty bit VPN 14 13 E 876 A 0 ASID 0
10 9 8 7 DV
ASID: Address space identifier A: Association bit : Reserved bits (write value should be 0, and read value is undefined )
Figure 6.15 Memory-Mapped UTLB Address Array
Rev. 1.0, 02/03, page 134 of 1294
6.6.5
UTLB Data Array 1
UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to data array 1 are specified in the data field. In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1 and the entry is specified by bits [13:8]. In the data field, bits [28:10] indicate PPN, bit [8] indicates V, bits [7] and [4] indicate SZ, bits [6:5] indicate PR, bit [3] indicates C, bit [2] indicates D, bit [1] indicates SH, and bit [0] indicates WT. The following two kinds of operation can be used on UTLB data array 1: 1. UTLB data array 1 read PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 1 write PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry corresponding to the entry set in the address field.
31 24 23 22 Address field 1 1 1 1 0 1 1 1 0 31 Data field PPN: V: E: SZ[1:0]: D: 29 28 PPN 14 13 E 10 9 8 7 6 5 4 3 2 1 0 V CD 87 0
SH SZ1 SZ0 Physical page number PR[1:0]: Protection key data WT PR[1:0] C: Cacheability bit Validity bit SH: Share status bit Entry WT: Write-through bit Page size bits : Reserved bits (write value should be 0, Dirty bit and read value is undefined )
Figure 6.16 Memory-Mapped UTLB Data Array 1
Rev. 1.0, 02/03, page 135 of 1294
6.6.6
UTLB Data Array 2
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification (when writing). Information for selecting the entry to be accessed is specified in the address field, and SA and TC to be written to data array 2 are specified in the data field. In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2 and the entry is specified by bits [13:8]. In the data field, bit [3] indicates TC and bits [2:0] indicate SA. The following two kinds of operation can be used on UTLB data array 2: 1. UTLB data array 2 read SA and TC are read into the data field from the UTLB entry corresponding to the entry set in the address field. 2. UTLB data array 2 write SA and TC specified in the data field are written to the UTLB entry corresponding to the entry set in the address field.
31 23 22 Address field 1 1 1 1 0 1 1 1 1 31 Data field 14 13 E 432 0 87 0
SA[2:0] TC TC: Timing control bit SA[2:0]: Space attribute bits E: Entry : Reserved bits (write value should be 0, and read value is undefined )
Figure 6.17 Memory-Mapped UTLB Data Array 2
Rev. 1.0, 02/03, page 136 of 1294
Section 7 Caches
7.1 Features
This LSI has an on-chip 16-kbyte instruction cache (IC) for instructions and an on-chip 32-kbyte operand cache (OC) for data. Half of the memory of the operand cache (16 kbytes) may alternatively be used as on-chip RAM. When the EMODE bit in CCR is 0, this LSI's cache behaves as shown in table 7.1. The features of the cache when the EMODE bit in CCR is 1 are given in table 7.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset. This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. The features of the store queues are given in table 7.3. Table 7.1
Item Capacity Type Line size Entries Write method
Cache Features (EMODE = 0)
Instruction Cache 8-kbyte cache Direct mapping 32 bytes 256 entires Operand Cache 16-kbyte cache or 8-kbyte cache + 8-kbyte RAM Direct mapping 32 bytes 512 entires Copy-back/write-through selectable
Table 7.2
Item Capacity Type Line size Entries Write method
Cache Features (EMODE = 1)
Instruction Cache 16-kbyte cache 2-way set-associative 32 bytes 256 entries/way Operand Cache 32-kbyte cache or 16-kbyte cache + 16-kbyte RAM 2-way set-associative 32 bytes 512 entries/way Copy-back/write-through selectable
Replacement method
LRU (least-recently-used) algorithm LRU (least-recently-used) algorithm
Rev. 1.0, 02/03, page 137 of 1294
Table 7.3
Item Capacity Addresses Write Write-back Access right
Store Queue Features
Store Queues 32 bytes x 2 H'E000 0000 to H'E3FF FFFF Store instruction (1-cycle write) Prefetch instruction (PREF instruction) MMU is off: Determined by SQMD bit in MMUCR MMU is on: Determined by PR for each page
Rev. 1.0, 02/03, page 138 of 1294
The operand cache of this LSI uses the 2-way set-associative method, and each way is configured of 512 cache lines. Figure 7.1 shows the configuration of the operand cache. The instruction cache uses the 2-way set-associative method, and each way is configured of 256 cache lines. Figure 7.2 shows the configuration of the instruction cache.
Effective address 31 26 25 13 12 10 54 2 0
RAM area definition OIX ORA Entry selection 22 9 0 Address array (way 0, way 1) Tag U V 3 [12:5] [13]
Longword (LW) selection
Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
LRU
MMU
19
511
19 bits
1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
1 bit
Compare Compare way 0 way 1
Read data
Write data
Hit signal
Figure 7.1 Configuration of Operand Cache
Rev. 1.0, 02/03, page 139 of 1294
Effective address 31 25 13 12 11 10 54 2 0
[11:5] IIX [12] Entry selection 22 8 0 Address array (way 0, way1) Tag V 3 Data array (way 0, way 1) LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7 LRU Longword (LW) selection
MMU
19
255
19 bits
1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
1 bit
Compare Compare way 1 way 0
Read data
Hit signal
Figure 7.2 Configuration of Instruction Cache * Tag Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is not initialized by a power-on or manual reset. * V bit (validity bit) Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset. * U bit (dirty bit) The U bit is set to 1 if data is written to the cache line while the cache is being used in copyback mode. That is, the U bit indicates a mismatch between the data in the cache line and the data in external memory. The U bit is never set to 1 while the cache is being used in writethrough mode, unless it is modified by accessing the memory-mapped cache (see section 7.5, Memory-Mapped Cache Configuration (Cache Direct Mapping Mode)). The U bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Rev. 1.0, 02/03, page 140 of 1294
* Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. * LRU In a 2-way set-associative method, up to 2 items of data can be registered in the cache at each entry address. When an entry is registered, the LRU bit indicates which of the 2 ways it is to be registered in. The LRU bit is a single bit of each entry, and its usage is controlled by hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a manual reset. The LRU bits cannot be read from or written to by software.
7.2
Register Descriptions
The following registers are related to cache. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 7.4 Register Configuration (1)
Abbrev. CCR QACR0 QACR1 R/W R/W R/W R/W P4 Address H'FF00 001C H'FF00 0038 H'FF00 003C Area 7 Address H'1F00 001C H'1F00 0038 H'1F00 003C Size 32 32 32 Sync Clock Ick Ick Ick
Register Name Cache control register Queue address control register 0 Queue address control register 1
Table 7.4
Register Configuration (2)
Standby Manual Reset by Sleep Power-on Reset RESET Pin/WDT/ by Sleep by RESET Multiple Instruction/ by Deep Sleep Hardware by Software/ Each Module
Register Name
Abbrev.
Pin/WDT/H-UDI Exception
Cache control register Queue address control register 0 Queue address control register 1
CCR QACR0 QACR1
H'0000 0000 Undefined Undefined
H'0000 0000 Undefined Undefined
Retained Retained Retained
*
Retained Retained Retained
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
Rev. 1.0, 02/03, page 141 of 1294
7.2.1
Cache Control Register (CCR)
CCR selects the cache operating mode, whether all cache entries are disabled, and the cache write mode. CCR can be accessed in longwords from H'FF00 001C in the P4 area and from H'1F00 001C in area 7. CCR modifications must only be made by a program in the non-cached P2 area. After CCR is updated, an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or U0 area should be located at least eight instructions after the CCR update instruction.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31
EMODE
30 0 R 14 0 R
29 0 R 13 0 R
28 0 R 12 0 R
27 0 R 11 ICI 0 R/W
26 0 R 10 0 R
25 0 R 9 0 R
24 0 R 8 ICE 0 R/W
23 0 R 7 OIX 0 R/W
22 0 R 6 0 R
21 0 R 5 ORA 0 R/W
20 0 R 4 0 R
19 0 R 3 OCI 0 R/W
18 0 R 2 CB 0 R/W
17 0 R 1 WT 0 R/W
16 0 R 0 OCE 0 R/W
0 R/W 15 IIX 0 R/W
Bit 31
Bit Name EMODE
Initial Value 0
R/W R/W
Description Double-Size Cache Mode Bit This bit selects whether double-size cache mode is used or not. Do not write to this bit while cache is being used. 0: Cache direct mapping mode 1: Double-size cache mode
30 to 16
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. IC Index Enable Bit 0: Effective address bits [12:5] used for IC entry selection 1: Effective address bits [25] and [11:5] used for IC entry selection
15
IIX
0
R/W
14 to 12
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. IC Invalidation Bit When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit is always read as 0.
11
ICI
0
R/W
Rev. 1.0, 02/03, page 142 of 1294
Bit 10, 9
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. IC Enable Bit Selects whether the IC is used. Note however when address translation is performed, the IC cannot be used unless the C bit in the page management information is also 1. 0: IC not used 1: IC used
8
ICE
0
R/W
7
OIX
0
R/W
OC Index Enable Bit 0: Effective address bits [13:5] used for OC entry selection 1: Effective address bits [25] and [12:5] used for OC entry selection When the ORA bit is 1, this bit should be cleared to 0.
6
0
R
Reserved This bit is always read as 0. The write value should always be 0. OCRAM Bit When the OC is enabled (OCE = 1), this bit specifies whether half of the OC is to be used as RAM. When the OC is disabled (OCE = 0), this bit should be cleared to 0. 0: Normal mode (the entire OC is used as a cache) 1: RAM mode (half of the OC is used as a cache and the other half is used as RAM) When the OIX bit is 1, this bit should be cleared to 0.
5
ORA
0
R/W
4
0
R
Reserved This bit is always read as 0. The write value should always be 0. OC Invalidation Bit When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit is always read as 0. Copy-Back Bit Indicates the P1 area cache write mode. 0: Write-through mode 1: Copy-back mode
3
OCI
0
R/W
2
CB
0
R/W
Rev. 1.0, 02/03, page 143 of 1294
Bit 1
Bit Name WT
Initial Value 0
R/W R/W
Description Write-Through Mode Indicates the P0, U0, and P3 area cache write mode. When address translation is performed, the value of the WT bit in the page management information has priority. 0: Copy-back mode 1: Write-through mode
0
OCE
0
R/W
OC Enable Bit Selects whether the OC is used. Note however when address translation is performed, the OC cannot be used unless the C bit in the page management information is also 1. 0: OC not used 1: OC used
7.2.2
Queue Address Control Register 0 (QACR0)
QACR0 can be accessed in longwords from H'FF00 0038 in the P4 area and from H'1F00 0038 in area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is off.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 23 R 7 R 22 R 6 R 21 R 5 R R/W 20 R 4 19 R 3 AREA0 R/W R/W 18 R 2 17 R 1 R 16 R 0 R
Bit 31 to 5
Bit Name
Initial Value
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. When the MMU is off, these bits generate external address bits [28:26] for SQ0. Reserved These bits are always read as 0. The write value should always be 0.
4 to 2 1, 0
AREA0

R/W R
Rev. 1.0, 02/03, page 144 of 1294
7.2.3
Queue Address Control Register 1 (QACR1)
QACR1 can be accessed in longwords from H'FF00 003C in the P4 area and from H'1F00 003C in area 7. QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is off.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 23 R 7 R 22 R 6 R 21 R 5 R R/W 20 R 4 19 R 3 AREA1 R/W R/W 18 R 2 17 R 1 R 16 R 0 R
Bit 31 to 5
Bit Name
Initial Value
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. When the MMU is off, these bits generate external address bits [28:26] for SQ1. Reserved These bits are always read as 0. The write value should always be 0.
4 to 2 1, 0
AREA1

R/W R
7.3
7.3.1
Operand Cache Operation
Read Operation
When the OC is enabled (OCE = 1 in CCR) and data is read by means of an effective address from a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: 3. * If the tag matches and the V bit is 1 * If the tag matches and the V bit is 0 * If the tag does not match and the V bit is 0 4. 4.
* If the tag does not match, the V bit is 1, and the U bit is 0 4. * If the tag does not match, the V bit is 1, and the U bit is 1 5.
Rev. 1.0, 02/03, page 145 of 1294
3. Cache hit The data indexed by effective address bits [4:0] is read from the data field of the cache line indexed by effective address bits [13:5] in accordance with the access size (quadword/longword/word/byte). 4. Cache miss (no write-back) Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 5. Cache miss (with write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the write-back buffer. Then data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU. While the remaining one cache line of data is being read, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back buffer is then written back to external memory. 7.3.2 Write Operation
When the OC is enabled (OCE = 1 in CCR) and data is written by means of an effective address to a cacheable area, the cache operates as follows: 1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: Copy-back Write-through * If the tag matches and the V bit is 1 * If the tag matches and the V bit is 0 * If the tag does not match and the V bit is 0 3. 5. 5. 4. 6. 6. 6. 6.
* If the tag does not match, the V bit is 1, and the U bit is 0 5. * If the tag does not match, the V bit is 1, and the U bit is 1 7.
Rev. 1.0, 02/03, page 146 of 1294
3. Cache hit (copy-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by effective address bits [4:0] of the data field of the cache line indexed by effective address bits [13:5]. Then 1 is written to the U bit. 4. Cache hit (write-through) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by effective address bits [4:0] of the data field of the cache line indexed by effective address bits [13:5]. A write is also performed to the corresponding external memory using the specified access size. 5. Cache miss (no copy-back/write-back) A data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by effective address bits [4:0] of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. 6. Cache miss (write-through) A write of the specified access size is performed to the external memory corresponding to the effective address. In this case, a write to cache is not performed. 7. Cache miss (with copy-back/write-back) The tag and data field of the cache line indexed by effective address bits [13:5] are first saved in the write-back buffer, and then a data write in accordance with the access size (quadword/longword/word/byte) is performed for the data indexed by effective address bits [4:0] of the data field of the cache line indexed by effective address bits [13:5]. Then, data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and one cache line of data is read excluding the written data. During this time, the CPU can execute the next processing. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written back to external memory.
Rev. 1.0, 02/03, page 147 of 1294
7.3.3
Write-Back Buffer
In order to give priority to data reads to the cache and improve performance, this LSI has a writeback buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache entry into external memory as the result of a cache miss. The write-back buffer contains one cache line of data and the physical address of the purge destination.
Physical address bits [28:5]
LW0
LW1
LW2
LW3
LW4
LW5
LW6
LW7
Figure 7.3 Configuration of Write-Back Buffer 7.3.4 Write-Through Buffer
This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as the write to the write-through buffer is completed, without waiting for completion of the write to external memory.
Physical address bits [28:0]
LW0
LW1
Figure 7.4 Configuration of Write-Through Buffer 7.3.5 RAM Mode
Setting the ORA bit in CCR to 1 enables half of the operand cache to be used as RAM. In cache direct mapping mode, the 8-kbyte area otherwise used for OC entries 256 to 511 is designated as a RAM area. In double-size cache mode, a total of 16 kbytes, comprising entries 256 to 511 in both of the ways of the operand cache, is designated as a RAM area. Other entries can still be used as cache. RAM can be accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-size data reads and writes can be performed in the operand cache RAM area. Instruction fetches cannot be performed in this area. This LSI cannot be used in OC index mode when RAM mode is selected. Examples of RAM usage is shown below. * In cache direct mapping mode (EMODE = 0 in CCR) H'7C00 0000 to H'7C00 1FFF (8 kbytes): RAM area (entries 256 to 511) H'7C00 2000 to H'7C00 3FFF (8 kbytes): RAM area (entries 256 to 511) : : : In the same pattern, shadows of the RAM area are created in 8-kbyte blocks until H'7FFF FFFF is reached.
Rev. 1.0, 02/03, page 148 of 1294
* In double-size cache mode (EMODE = 1 in CCR) In this mode, the 8 kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM area 1 and the 8-kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM area 2. H'7C00 0000 to H'7C00 1FFF (8 kbytes): Corresponds to RAM area 1 H'7C00 2000 to H'7C00 3FFF (8 kbytes): Corresponds to RAM area 2 H'7C00 4000 to H'7C00 5FFF (8 kbytes): Corresponds to RAM area 1 H'7C00 6000 to H'7C00 7FFF (8 kbytes): Corresponds to RAM area 2 : : : In the same pattern, shadows of the RAM area are created in 16-kbyte blocks until H'7FFF FFFF is reached. 7.3.6 OC Index Mode
Setting the OIX bit in CCR to 1 enables OC indexing to be performed using bit [25] of the effective address. This is called OC index mode. In normal mode, with the OIX bit in CCR cleared to 0, OC indexing is performed using bits [13:5] of the effective address. Using index mode allows the OC to be handled as two 8-kbyte areas by means of effective address bit [25], providing efficient use of the cache. This LSI cannot be used in RAM mode when OC index mode is selected. 7.3.7 Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In this LSI, the following four new instructions are supported for cache operations. Details of these instructions are given in the Programming Manual.
* * * * Invalidate instruction Purge instruction Write-back instruction Allocate instruction
: OCBI @Rn : OCBP @Rn : OCBWB @Rn : MOVCA.L R0,@Rn
Cache invalidation (no write-back) Cache invalidation (with write-back) Cache write-back Cache allocation
7.3.8
Prefetch Operation
This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss. If it is known that a cache miss will result from a read or write operation, it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operation, and so improve software performance. If a prefetch instruction is executed for data already held in the cache, or if the prefetch address results in a UTLB miss or a protection violation, the result is no operation, and an exception is not generated. Details of the prefetch instruction are given in the Programming Manual.
Rev. 1.0, 02/03, page 149 of 1294
* Prefetch instruction
: PREF @Rn
7.4
7.4.1
Instruction Cache Operation
Read Operation
When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed by means of an effective address from a cacheable area, the instruction cache operates as follows: 1. The tag and V bit are read from the cache line indexed by effective address bits [12:5]. 2. The tag is compared with bits [28:10] of the address resulting from effective address translation by the MMU: 3. * If the tag matches and the V bit is 1 * If the tag matches and the V bit is 0 * If the tag does not match and the V bit is 0 * If the tag does not match and the V bit is 1 3. Cache hit The data indexed by effective address bits [4:2] is read as an instruction from the data field of the cache line indexed by effective address bits [12:5]. 4. Cache miss Data is read into the cache line from the external memory space corresponding to the effective address. Data reading is performed, using the wraparound method, in order from the longword data corresponding to the effective address, and when the corresponding data arrives in the cache, the read data is returned to the CPU as an instruction. When reading of one line of data is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V bit. 7.4.2 IC Index Mode 4. 4. 4.
Setting the IIX bit in CCR to 1 enables IC indexing to be performed using bit [25] of the effective address. This is called IC index mode. In normal mode, with the IIX bit in CCR cleared to 0, IC indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled as two 4-kbyte areas by means of effective address bit [25], providing efficient use of the cache.
Rev. 1.0, 02/03, page 150 of 1294
7.5
Memory-Mapped Cache Configuration (Cache Direct Mapping Mode)
To enable the IC and OC to be managed by software, the IC contents can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least eight instructions after this MOV instruction. In privileged mode, the OC contents can be read from or written to by a program in the P1 or P2 area by means of a MOV instruction. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least eight instructions after this MOV instruction The IC and OC are allocated to the P4 area in the physical address space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified and the read value is undefined. 7.5.1 IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry is specified by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0.
Rev. 1.0, 02/03, page 151 of 1294
2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. 3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine.
24 23 31 Address field 1 1 1 1 0 0 0 0 31 Data field Tag V : Validity bit A : Association bit : Reserved bits (write value should be 0, and read value is undefined ) 13 12 Entry 10 9 543210 A 10 V
Figure 7.5 Memory-Mapped IC Address Array 7.5.2 IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is specified by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification.
Rev. 1.0, 02/03, page 152 of 1294
The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the entry set in the address field.
24 23 31 Address field 1 1 1 1 0 0 0 1 31 Data field Longword data L : Longword specification bits : Reserved bits (write value should be 0, and read value is undefined ) 13 12 Entry 54 L 0 210
Figure 7.6 Memory-Mapped IC Data Array 7.5.3 OC Address Array
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the entry is specified by bits [13:5]. The OIX and ORA bits in CCR have no effect on this entry specification. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed.
Rev. 1.0, 02/03, page 153 of 1294
The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag stored in the entry specified in the address field is compared with the tag specified in the data field. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry. In other cases, no operation is performed. This operation is used to invalidate a specific OC entry. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine.
31 24 23 Address field 1 1 1 1 0 1 0 0 31 Data field Tag V : Validity bit U : Dirty bit A : Association bit : Reserved bits (write value should be 0, and read value is undefined ) 14 13 Entry 10 9 543210 A 210 UV
Figure 7.7 Memory-Mapped OC Address Array
Rev. 1.0, 02/03, page 154 of 1294
7.5.4
OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The entry to be accessed is specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is specified by bits [13:5]. The OIX and ORA bits in CCR have no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding the entry set in the address field. This write does not set the U bit to 1 on the address array side.
24 23 31 Address field 1 1 1 1 0 1 0 1 31 Data field Longword data L : Longword specification bits : Reserved bits (write value should be 0, and read value is undefined ) 14 13 Entry 54 L 0 210
Figure 7.8 Memory-Mapped OC Data Array
Rev. 1.0, 02/03, page 155 of 1294
7.6
Memory-Mapped Cache Configuration (Double-Size Cache Mode)
To enable the IC and OC to be managed by software, the IC contents can be read from or written to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be made at least eight instructions after this MOV instruction. In privileged mode, the OC contents can be read from or written to by a program in the P1 or P2 area by means of a MOV instruction. Operation is not guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0, or P3 area should be made at least eight instructions after this MOV instruction. The IC and OC are allocated to the P4 area in the physical address space. Only data accesses can be used on both the IC address array and data array and the OC address array and data array, and accesses are always longword-size. Instruction fetches cannot be performed in these areas. For reserved bits, a write value of 0 should be specified; their read value is undefined. 7.6.1 IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is specified by bit [13], and the entry by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the IC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed. The following three kinds of operation can be used on the IC address array: 1. IC address array read The tag and V bit are read into the data field from the IC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. IC address array write (non-associative) The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0.
Rev. 1.0, 02/03, page 156 of 1294
3. IC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [13] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses match and the V bit for that way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If an instruction TLB multiple hit exception occurs during address translation, processing switches to the instruction TLB multiple hit exception handling routine.
24 23 31 Address field 1 1 1 1 0 0 0 0 14 13 12 Entry Way 31 Data field Tag V : Validity bit A : Association bit : Reserved bits (write value should be 0, and read value is undefined ) 10 9 10 V 543210 A
Figure 7.9 Memory-Mapped IC Address Array 7.6.2 IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is specified by bit [13], and the entry by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification.
Rev. 1.0, 02/03, page 157 of 1294
The following two kinds of operation can be used on the IC data array: 1. IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field. 2. IC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the IC entry corresponding to the way and entry set in the address field.
24 23 31 Address field 1 1 1 1 0 0 0 1 14 13 12 Entry Way 31 Data field Longword data L : Longword specification bits : Reserved bits (write value should be 0, and read value is undefined ) 0 54 L 210
Figure 7.10 Memory-Mapped IC Data Array 7.6.3 OC Address Array
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An address array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the write tag, U bit, and V bit are specified in the data field. In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is specified by bit [14], and the entry by bits [13:5]. The OIX bit in CCR has no effect on this entry specification. In RAM mode (ORA = 1 in CCR), the OC address arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 7.6.5, Summary of Memory-Mapping of OC. The association bit (A bit) [3] in the address field specifies whether or not association is performed when writing to the OC address array. As only longword access is used, 0 should be specified for address field bits [1:0]. In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0]. As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which association is not performed. Data field bits [31:29] are used for the virtual address specification only in the case of a write in which association is performed.
Rev. 1.0, 02/03, page 158 of 1294
The following three kinds of operation can be used on the OC address array: 1. OC address array read The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the way and entry set in the address field. In a read, associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0. 2. OC address array write (non-associative) The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field. The A bit in the address field should be cleared to 0. When a write is performed to a cache line for which the U bit and V bit are both 1, after writeback of that cache line, the tag, U bit, and V bit specified in the data field are written. 3. OC address array write (associative) When a write is performed with the A bit in the address field set to 1, the tag for each of the ways stored in the entry specified in the address field is compared with the tag specified in the data field. The way number set by bit [14] is not used. If the MMU is enabled at this time, comparison is performed after the virtual address specified by data field bits [31:10] has been translated to a physical address using the UTLB. If the addresses match and the V bit for that way is 1, the U bit and V bit specified in the data field are written into the OC entry. In other cases, no operation is performed. This operation is used to invalidate a specific OC entry. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss occurs during address translation, or the comparison shows a mismatch, an exception is not generated, no operation is performed, and the write is not executed. If a data TLB multiple hit exception occurs during address translation, processing switches to the data TLB multiple hit exception handling routine.
24 23 31 Address field 1 1 1 1 0 1 0 0 15 14 13 Entry Way 31 Data field Tag V : Validity bit U : Dirty bit A : Association bit : Reserved bits (write value should be 0, and read value is undefined ) 10 9 210 UV 543210 A
Figure 7.11 Memory-Mapped OC Address Array
Rev. 1.0, 02/03, page 159 of 1294
7.6.4
OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data array access requires a 32-bit address field specification (when reading or writing) and a 32-bit data field specification. The way and entry to be accessed are specified in the address field, and the longword data to be written is specified in the data field. In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is specified by bit [14], and the entry by bits [13:5]. The OIX bit in CCR has no effect on this entry specification. In RAM mode (ORA = 1 in CCR), the OC data arrays are only accessible in the memory-mapped cache area, and bit [13] is used to specify the way. For details about address mapping, see section 7.6.5, Summary of Memory-Mapping of OC. Address field bits [4:2] are used for the longword data specification in the entry. As only longword access is used, 0 should be specified for address field bits [1:0]. The data field is used for the longword data specification. The following two kinds of operation can be used on the OC data array: 1. OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. 2. OC data array write The longword data specified in the data field is written for the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field. This write does not set the U bit to 1 on the address array side.
31 24 23 Address field 1 1 1 1 0 1 0 1 15 14 13 Entry Way Longword data L : Longword specification bits : Reserved bits (write value should be 0, and read value is undefined ) 54 L 210
31 Data field
0
Figure 7.12 Memory-Mapped OC Data Array
Rev. 1.0, 02/03, page 160 of 1294
7.6.5
Summary of Memory-Mapping of OC
The address ranges to which the OC is memory-mapped in double-size cache mode of this LSI are summarized below in the example of data array access. * In normal mode (ORA = 0 in CCR) H'F500 0000 to H'F500 3FFF (16 kbytes ): Way 0 (entries 0 to 511) H'F500 4000 to H'F500 7FFF (16 kbytes ): Way 1 (entries 0 to 511) In the same pattern, shadows of the cache area are created in 32-kbyte blocks until H'F5FF FFFF. * In RAM mode (ORA = 1 in CCR) H'F500 0000 to H'F500 1FFF (8 kbytes ): Way 0 (entries 0 to 255) H'F500 2000 to H'F500 3FFF (8 kbytes ): Way 1 (entries 0 to 255) In the same pattern, shadows of the cache area are created in 16-kbyte blocks until H'F5FF FFFF.
7.7
Store Queues
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external memory. If the SQs are not used, power-down modes, in which SQ functions are stopped, can be used to reduce power consumption. The queue address control registers (QACR0 and QACR1) cannot be accessed while SQ functions are stopped. See section 14, Power-Down Modes, for the procedure for stopping SQ functions. 7.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 7.13. These two store queues can be set independently.
SQ0
SQ0[0]
SQ0[1]
SQ0[2]
SQ0[3]
SQ0[4]
SQ0[5]
SQ0[6]
SQ0[7]
SQ1
SQ1[0] 4 bytes
SQ1[1] 4 bytes
SQ1[2] 4 bytes
SQ1[3] 4 bytes
SQ1[4] 4 bytes
SQ1[5] 4 bytes
SQ1[6] 4 bytes
SQ1[7] 4 bytes
Figure 7.13 Store Queue Configuration
Rev. 1.0, 02/03, page 161 of 1294
7.7.2
Writing to SQ
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of the address bits are as follows: [31:26] [25:6] [5] [4:2] [1:0] : 111000 : Don't care : 0/1 : LW specification : 00 Store queue specification Used for external memory transfer/access right 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0
7.7.3
Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF). Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start address is always at a 32-byte boundary. While the contents of one SQ are being transferred to external memory, the other SQ can be written to without a penalty cycle. However, writing to the SQ involved in the transfer to external memory is kept waiting until the transfer is completed. The external address bits [28:0] of the SQ transfer destination are specified as shown below, according to whether the MMU is on or off. * When MMU is on (AT = 1 in MMUCR) The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same meaning as for normal address translation, but the C and WT bits have no meaning with regard to this page. Transfer to the PCMCIA interface area by means of the SQs is not allowed. When a prefetch instruction is issued for the SQ area, address translation is performed and external address bits [28:10] are generated in accordance with the SZ bit specification. For external address bits [9:5], the address prior to address translation is generated in the same way as when the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to external memory is performed to this address.
Rev. 1.0, 02/03, page 162 of 1294
* When MMU is off (AT = 0 in MMUCR) The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF instruction is issued. The meanings of address bits [31:0] are as follows: [31:26] [25:6] [5] [4:2] [1:0] : 111000 : Address : 0/1 : Don't care : 00 Store queue specification External address bits [25:6] 0: SQ0 specification 1: SQ1 specification and external address bit [5] No meaning in a prefetch Fixed at 0
External address bits [28:26], which cannot be generated from the above address, are generated from QACR0 and QACR1. QACR0[4:2] QACR1[4:2] : External address bits [28:26] corresponding to SQ0 : External address bits [28:26] corresponding to SQ1
External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte boundary. Data transfer to a PCMCIA interface area in this LSI is always performed using the values of the SA and TC bits in PTEA. 7.7.4 Determination of SQ Access Exception
Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) is performed as follows according to whether the MMU is on or off. If an exception occurs during a write to an SQ, the SQ contents before the write are retained. If an exception occurs in a data transfer from an SQ to external memory, the transfer to external memory will be aborted. * When MMU is on (AT = 1 in MMUCR) Operation is in accordance with the address translation information recorded in the UTLB, and the SQMD bit in MMUCR. Write type exception judgment is performed for writes to the SQs, and read type exception judgment for transfer from the SQs to external memory (using a PREF instruction). As a result, a TLB miss exception, protection violation exception, or initial page write exception is generated as required. However, if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR, an address error will occur even if address translation is successful in user mode. * When MMU is off (AT = 0 in MMUCR) Operation is in accordance with the SQMD bit in MMUCR. 0: Privileged/user mode access possible
Rev. 1.0, 02/03, page 163 of 1294
1: Privileged mode access possible If the SQ area is accessed in user mode when the SQMD bit in MMUCR is set to 1, an address error will occur. 7.7.5 Reading from SQ
In privileged mode in this LSI, reading the contents of the SQs may be performed by means of a load instruction for addresses H'FF00 1000 to H'FF00 103C in the P4 area. Only longword access is possible. [31:6] [5] [4:2] [1:0] : H'FF00 1000 : 0/1 : LW specification : 00 Store queue specification 0: SQ0 specification 1: SQ1 specification Specifies longword position in SQ0/SQ1 Fixed at 0
Rev. 1.0, 02/03, page 164 of 1294
Section 8 Exceptions
8.1 Exception Handling Functions
Exception handling processing is handled by a special routine, separate from normal program processing, which is executed by the CPU in case of abnormal events. For example, if the executing instruction ends abnormally, appropriate action must be taken in order to return to the original program sequence, or report the abnormality before terminating the processing. The process of generating an exception handling request in response to abnormal termination, and passing control to a user-written exception handling routine, in order to support such functions, is given the generic name of exception handling. The exception handling in this LSI is of three kinds: resets, general exceptions, and interrupts. 8.1.1 Exception Handling Flow
In exception handling, the contents of the program counter (PC), status register (SR), and R15 are saved in the saved program counter (SPC), saved status register (SSR), and saved general register15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to the vector address. An exception handling routine is a program written by the user to handle a specific exception. The exception handling routine is terminated and control returned to the original program by executing a return-from-exception instruction (RTE). This instruction restores the PC and SR contents and returns control to the normal processing routine at the point at which the exception occurred. The SGR contents are not written back to R15 with an RTE instruction. The basic processing flow is as follows. 1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR, respectively. 2. The block bit (BL) in SR is set to 1. 3. The mode bit (MD) in SR is set to 1. 4. The register bank bit (RB) in SR is set to 1. 5. In a reset, the FPU disable bit (FD) in SR is cleared to 0. 6. The exception code is written to bits 11 to 0 of the exception event register (EXPEVT) or interrupt event register (INTEVT). 7. The CPU branches to the determined exception handling vector address, and the exception handling routine begins.
Rev. 1.0, 02/03, page 165 of 1294
8.1.2
Exception Handling Vector Addresses
The reset vector address is fixed at H'A000 0000. Exception and interrupt vector addresses are determined by adding the offset for the specific event to the vector base address, which is set by software in the vector base register (VBR). In the case of the TLB miss exception, for example, the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses (in P1 and P2 areas) should be specified for vector addresses.
Rev. 1.0, 02/03, page 166 of 1294
8.2
Exception Types and Priorities
Table 8.1 shows the types of exceptions, with their relative priorities, vector addresses, and exception/interrupt codes. Table 8.1 Exception Sources and Priorities
Priority Priority Vector Level Order Address 1 1 1 1 1 2 1 3 4 0 1 2 3 4 4 4 4 5 5 6 6 7 7 8 9 4 10 Offset Exception Code H'000 H'020 H'000 H'140 H'140
Exception Execution Category Mode Exception Reset Abort type Power-on reset Manual reset H-UDI reset Instruction TLB multiple-hit exception
H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- H'A000 0000 -- (VBR/DBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR) (VBR/DBR)
Data TLB multiple-hit exception 1 General exception ReUser break before instruction execution execution*1 type Instruction address error Instruction TLB miss exception Instruction TLB protection violation exception General illegal instruction exception 2 2 2 2 2
H'100/-- H'1E0 H'100 H'400 H'100 H'100 H'100 H'100 H'100 H'100 H'100 H'400 H'400 H'100 H'100 H'100 H'100 H'100 H'0E0 H'040 H'0A0 H'180 H'1A0 H'800 H'820 H'0E0 H'100 H'040 H'060 H'0A0 H'0C0 H'120 H'080 H'160
Slot illegal instruction exception 2 General FPU disable exception 2 Slot FPU disable exception Data address error (read) Data address error (write) 2 2 2
Data TLB miss exception (read) 2 Data TLB miss exception (write) 2 Data TLB protection violation exception (read) Data TLB protection violation exception (write) FPU exception Initial page write exception Completion Unconditional trap (TRAPA) type User break after instruction execution*1 2 2 2 2 2 2
H'100/-- H'1E0
Rev. 1.0, 02/03, page 167 of 1294
Exception Execution Category Mode Exception Interrupt Completion NMI type External IRL3 to interrupts IRL0
Priority Priority Vector Level Order Address 3 0 1 2 3 4 5 6 7 8 9 A B C D E IRL IRL0 IRL1 IRL2 IRL3 4 -- *
2
Offset H'600 H'600
Exception Code H'1C0 H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 H'240 H'2A0 H'300 H'360
(VBR) (VBR)
Peripheral DMAC module interrupt (module/ source)
DMTE0 4 DMTE1 DMTE2 DMTE3 DMTE4 DMTE5 DMTE6 DMTE7 DMAE
*
2
(VBR)
H'600
H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 H'800 H'820 H'840 H'860
IRQ*
3
IRQ4 IRQ5 IRQ6 IRQ7
Rev. 1.0, 02/03, page 168 of 1294
Exception Execution Category Mode Exception Interrupt Completion Peripheral HCAN2 type module interrupt (module/ SSI source) HAC
Priority Priority Vector Level Order Address CANI0 4 CANI1 SSII0 SSII1 HACI0 HACI1 IIC IICI0 IICI1 USB LCDC DMABRG USBI VINT
DMABRGI0 DMABRGI1 DMABRGI2
Offset H'600
Exception Code H'900 H'920 H'940 H'960 H'980 H'9A0 H'9C0 H'9E0 H'A00 H'A20 H'A80 H'AA0 H'AC0 H'880 H'8A0 H'8C0 H'8E0 H'B00 H'B20 H'B40 H'B60 H'B80 H'BA0 H'BC0 H'BE0 H'C00 H'C20 H'C40 H'C60 H'C80
*2
(VBR)
SCIF
ERI0 RXI0 BRI0 TXI0 ERI1 RXI1 BRI1 TXI1 ERI2 RXI2 BRI2 TXI2
SIM
SIMERI SIMRXI SIMTXI SIMTEI
HSPI
SPII
Rev. 1.0, 02/03, page 169 of 1294
Exception Execution Category Mode Exception Interrupt Completion Peripheral MMCIF type module interrupt (module/ source) MFI --
Priority Priority Vector Level Order Address MMCI0 4 MMCI1 MMCI2 MMCI3 MFII -- -- -- -- H-UDI GPIO ADC CMT TMU H-UDI GPIOI ADI CMTI TUNI0 TUNI1 TUNI2 TICPI2 WDT REF ITI RCMI ROVI *2 (VBR)
Offset H'600
Exception Code H'D00 H'D20 H'D40 H'D60 H'E80 H'F00 H'F20 H'F40 H'F60 H'600 H'620 H'F80 H'FA0 H'400 H'420 H'440 H'460 H'560 H'580 H'5A0
: Priority is first assigned by priority level, then by priority order within each level (the lowest number represents the highest priority). For details of the interrupt priority level, see section 9, Interrupt Controller (INTC). Exception transition destination : Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases. Exception code : Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt. IRL : Interrupt request level (pins IRL3 to IRL0). Module/source : See the sections on the relevant peripheral modules. Notes: 1. When UBDE in BRCR = 1, PC = DBR. In other cases, PC = VBR + H'100. 2. The priority order of external interrupts and peripheral module interrupts can be set by software. 3. IRQ is external interrupt.
Priority
Rev. 1.0, 02/03, page 170 of 1294
8.3
8.3.1
Exception Flow
Exception Flow
Figure 8.1 shows an outline flowchart of the basic operations in instruction execution and exception handling. For the sake of clarity, the following description assumes that instructions are executed sequentially, one by one. Figure 8.1 shows the relative priority order of the different kinds of exceptions (reset, general exception, and interrupt). Register settings in the event of an exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC. However, other registers may be set automatically by hardware, depending on the exception. For details, see section 8.5, Operation. Also, see section 8.5.4, Priority Order with Multiple Exceptions, for exception handling during execution of a delayed branch instruction and a delay slot instruction, or in the case of instructions in which two data accesses are performed.
Reset requested? No Execute next instruction
Yes
General exception requested? No Interrupt requested? No
Yes
Is highestYes priority exception re-exception type? Cancel instruction execution No result
Yes
SSR SR SPC PC SGR R15 EXPEVT/INTEVT exception code SR.{MD,RB,BL} 111 PC (BRCR.UBDE=1 && User_Break? DBR: (VBR + Offset))
EXPEVT exception code SR. {MD, RB, BL, FD, IMASK} 11101111 PC H'A000 0000
Figure 8.1 Instruction Execution and Exception Handling
Rev. 1.0, 02/03, page 171 of 1294
8.3.2
Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more simultaneously generated exceptions should be accepted. Five of the general exceptions--general illegal instruction exception, slot illegal instruction exception, general FPU disable exception, slot FPU disable exception, and unconditional trap exception--are detected in the process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These exceptions therefore all have the same priority. General exceptions are detected in the order of instruction execution. However, exception handling is performed in the order of instruction flow (program order). Thus, an exception for an earlier instruction is accepted before that for a later instruction. An example of the order of acceptance for general exceptions is shown in figure 8.2.
Pipeline flow: Instruction n Instruction n + 1 TLB miss (data access) ID EX MA WB ID EX MA WB General illegal instruction exception TLB miss (instruction access) IF ID EX MA WB
IF IF
Instruction n + 2
Instruction n + 3
IF
ID
EX
MA WB
Order of detection: General illegal instruction exception (instruction n + 1) and TLB miss (instruction n + 2) are detected simultaneously TLB miss (instruction n) Order of exception handling: TLB miss (instruction n) Re-execution of instruction n General illegal instruction exception (instruction n + 1) Re-execution of instruction n + 1 TLB miss (instruction n + 2) 3 Re-execution of instruction n + 2 Execution of instruction n + 3 Legend: IF ID EX MA WB : Instruction fetch : Instruction decode : Instruction execution : Memory access : Write-back 4 Program order 1
2
Figure 8.2 Example of General Exception Acceptance Order
Rev. 1.0, 02/03, page 172 of 1294
8.3.3
Exception Requests and BL Bit
When the BL bit in SR is 0, exceptions and interrupts are accepted. When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's internal registers and the registers of the other modules are set to their states following a manual reset, and the CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a user break, see section 31, User Break Controller (UBC). If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable multiple exception state acceptance. 8.3.4 Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns from the exception handling routine by branching to the SPC address. If SPC and SSR were saved to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and issuing the RTE instruction.
Rev. 1.0, 02/03, page 173 of 1294
8.4
Register Descriptions
There are three registers related to exception handling. These are allocated to memory, and can be accessed by specifying the P4 address or area 7 address. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 8.2 Register Configuration (1)
Abbrev. TRA EXPEVT INTEVT R/W R/W R/W R/W P4 Address H'FF00 0020 H'FF00 0024 H'FF00 0028 Area 7 Address Size H'1F00 0020 H'1F00 0024 H'1F00 0028 32 32 32 Sync Clock Ick Ick Ick
Register Name TRAPA exception register Exception event register Interrupt event register
Table 8.2
Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI Undefined Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Standby by Sleep Software by Sleep /Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained * Retained Retained Retained
Register Name TRAPA exception register Exception event register Interrupt event register
Abbrev. TRA EXPEVT INTEVT
H'0000 0000 H'0000 0020 Undefined Undefined
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
Rev. 1.0, 02/03, page 174 of 1294
8.4.1
Exception Event Register (EXPEVT)
EXPEVT consists of a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R * R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0. 12-bit exception code
31 to 12
11 to 0
*
R/W
Note: * H'000 is set in a power-on reset, and H'020 in a manual reset.
8.4.2
Interrupt Event Register (INTEVT)
INTEVT consists of a 14-bit interrupt exception code. The interrupt exception code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 29 0 R 13 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0. 14-bit interrupt exception code
31 to 14
13 to 0
R/W
Rev. 1.0, 02/03, page 175 of 1294
8.4.3
TRAPA Exception Register (TRA)
TRA consists of 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R R/W R/W R/W 25 0 R 9 24 0 R 8 23 0 R 7 22 0 R 6 imm R/W R/W R/W R/W R/W 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 0 R 16 0 R 0 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0. 8-bit immediate data Reserved These bits are always read as 0, and the write value should always be 0.
31 to 10
9 to 2 1, 0
imm
All 0
R/W R
Rev. 1.0, 02/03, page 176 of 1294
8.5
8.5.1
Operation
Resets
(1) Power-On Reset * Sources: RESET pin low level When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is cleared to 0 in WTCSR. For details, see section 13, Watchdog timer (WDT). * Transition address: H'A000 0000 * Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits (IMASK3 to IMASK0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin must be driven low. It is therefore essential to execute a power-on reset and drive the TRST pin low when powering on. If the RESET pin is driven high before the MRESET pin while both these pins are low, a manual reset may occur after the power-on reset operation. The RESET pin must be driven high at the same time as, or after, the MRESET pin.
Power_on_reset() { EXPEVT = H'0000 0000; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD=0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A000 0000; }
Rev. 1.0, 02/03, page 177 of 1294
(2) Manual Reset * Sources: MRESET pin low level and RESET pin high level When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details, see section 13, Watchdog Timer (WDT). * Transition address: H'A000 0000 * Transition operations: Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits (IMASK3 to IMASK0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections.
Manual_reset() { EXPEVT = H'0000 0020; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A000 0000; }
Rev. 1.0, 02/03, page 178 of 1294
(3) H-UDI Reset * Source: SDIR.TI7-TI4 = B'0110 (negation) or B'0111 (assertion) * Transition address: H'A000 0000 * Transition operations: Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits (IMASK3 to IMASK0) are set to B'1111. CPU and on-chip peripheral module initialization is performed. For details, see the register descriptions in the relevant sections.
H-UDI_reset() { EXPEVT = H'0000 0000; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(PowerOn); PC = H'A000 0000; }
Rev. 1.0, 02/03, page 179 of 1294
(4) Instruction TLB Multiple-Hit Exception * Source: Multiple ITLB address matches * Transition address: H'A000 0000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits (IMASK3 to IMASK0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections.
TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'0000 0140; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A000 0000; }
Rev. 1.0, 02/03, page 180 of 1294
(5) Data TLB Multiple-Hit Exception * Source: Multiple UTLB address matches * Transition address: H'A000 0000 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a branch is made to PC = H'A000 0000. In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD, RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits (IMASK3 to IMASK0) are set to B'1111. CPU and on-chip peripheral module initialization is performed in the same way as in a manual reset. For details, see the register descriptions in the relevant sections.
TLB_multi_hit() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; EXPEVT = H'0000 0140; VBR = H'0000 0000; SR.MD = 1; SR.RB = 1; SR.BL = 1; SR.(I0-I3) = B'1111; SR.FD = 0; Initialize_CPU(); Initialize_Module(Manual); PC = H'A000 0000; }
Rev. 1.0, 02/03, page 181 of 1294
8.5.2
General Exceptions
(1) Data TLB Miss Exception * Source: Address mismatch in UTLB address comparison * Transition address: VBR + H'0000 0400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions.
Data_TLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'0000 0040 : H'0000 0060; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0400; }
Rev. 1.0, 02/03, page 182 of 1294
(2) Instruction TLB Miss Exception * Source: Address mismatch in ITLB address comparison
* Transition address: VBR + H'0000 0400 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400. To speed up TLB miss processing, the offset is separate from that of other exceptions.
ITLB_miss_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0040; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0400; }
Rev. 1.0, 02/03, page 183 of 1294
(3) Initial Page Write Exception * Source: TLB is hit in a store access, but dirty bit D = 0 * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Initial_write_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0080; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 184 of 1294
(4) Data TLB Protection Violation Exception * Source: The access does not accord with the UTLB protection information (PR bits) shown below.
PR 00 01 10 11 Privileged Mode Only read access possible Read/write access possible Only read access possible Read/write access possible User Mode Access not possible Access not possible Only read access possible Read/write access possible
* Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Data_TLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access ? H'0000 00A0 : H'0000 00C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 185 of 1294
(5) Instruction TLB Protection Violation Exception * Source: The access does not accord with the ITLB protection information (PR bits) shown below.
PR 0 1 Privileged Mode Access possible Access possible User Mode Access not possible Access possible
* Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 186 of 1294
(6) Data Address Error * Sources: Word data access from other than a word boundary (2n +1) Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3) Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n + 4, 8n + 5, 8n + 6, or 8n + 7) Access to area H'8000 0000-H'FFFF FFFF in user mode * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 6, Memory Management Unit (MMU).
Data_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = read_access? H'0000 00E0: H'0000 0100; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 187 of 1294
(7) Instruction Address Error * Sources: Instruction fetch from other than a word boundary (2n +1) Instruction fetch from area H'8000 0000-H'FFFF FFFF in user mode * Transition address: VBR + H'0000 0100 * Transition operations: The virtual address (32 bits) at which this exception occurred is set in TEA, and the corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates the ASID when this exception occurred. The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For details, see section 6, Memory Management Unit (MMU).
Instruction_address_error() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 188 of 1294
(8) Unconditional Trap * Source: Execution of TRAPA instruction * Transition address: VBR + H'0000 0100 * Transition operations: As this is a processing-completion-type exception, the PC contents for the instruction following the TRAPA instruction are saved in SPC. The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
TRAPA_exception() { SPC = PC + 2; SSR = SR; SGR = R15; TRA = imm << 2; EXPEVT = H'0000 0160; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 189 of 1294
(9) General Illegal Instruction Exception * Sources: Decoding of an undefined instruction not in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding in user mode of a privileged instruction not in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded.
General_illegal_instruction_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0180; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 190 of 1294
(10) Slot Illegal Instruction Exception * Sources: Decoding of an undefined instruction in a delay slot Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'FFFD Decoding of an instruction that modifies PC in a delay slot Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR Decoding in user mode of a privileged instruction in a delay slot Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC instructions that access GBR Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot * Transition address: VBR + H'0000 0100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other than H'FFFD is decoded.
Slot_illegal_instruction_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'0000 01A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 191 of 1294
(11) General FPU Disable Exception * Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1 * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F (but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L instructions corresponding to FPUL and FPSCR.
General_fpu_disable_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0800; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 192 of 1294
(12) Slot FPU Disable Exception * Source: Decoding of an FPU instruction in a delay slot with SR.FD =1 * Transition address: VBR + H'0000 0100 * Transition operations: The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and R15 contents when this exception occurred are saved in SSR and SGR. Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Slot_fpu_disable_exception() { SPC = PC - 2; SSR = SR; SGR = R15; EXPEVT = H'0000 0820; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 193 of 1294
(13) User Breakpoint Trap * Source: Fulfilling of a break condition set in the user break controller * Transition address: VBR + H'0000 0100, or DBR * Transition operations: In the case of a post-execution break, the PC contents for the instruction following the instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break, the PC contents for the instruction at which the breakpoint is set are set in SPC. The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code H'1E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is also possible to branch to PC = DBR. For details of PC, etc., when a data break is set, see section 31, User Break Controller (UBC).
User_break_exception() { SPC = (pre_execution break? PC : PC + 2); SSR = SR; SGR = R15; EXPEVT = H'0000 01E0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = (BRCR.UBDE==1 ? DBR : VBR + H'0000 0100); }
Rev. 1.0, 02/03, page 194 of 1294
(14) FPU Exception * Source: Exception due to execution of a floating-point operation * Transition address: VBR + H'0000 0100 * Transition operations: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
FPU_exception() { SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 0120; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; }
Rev. 1.0, 02/03, page 195 of 1294
8.5.3 (1) NMI
Interrupts
* Source: NMI pin edge detection * Transition address: VBR + H'0000 0600 * Transition operations: The PC and SR contents for the instruction at which this exception is accepted are saved in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or accepted. For details, see section 9, Interrupt Controller (INTC).
NMI() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 01C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0600; }
Rev. 1.0, 02/03, page 196 of 1294
(2) IRL Interrupts * Source: The interrupt mask level bits (IMASK3 to IMASK0) setting in SR is smaller than the IRL (3-0) level, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'0000 0600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the IRL (3-0) level is set in INTEVT. See table 9.7, for the corresponding codes. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The acceptance level is not set in the interrupt mask level bits (IMASK3 to IMASK0) in SR. When the BL bit in SR is 1, the interrupt is masked. For details, see section 9, Interrupt Controller (INTC).
IRL() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 0200 ~ H'0000 03C0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0600; }
Rev. 1.0, 02/03, page 197 of 1294
(3) Peripheral Module Interrupts * Source: The interrupt mask level bits (IMASK3 to IMASK0) setting in SR is smaller than the 2 peripheral module (DMAC, IRQ, HCAN2, SSI, HAC, I C, USB, LCDC, DMABRG, SCIF, SIM, HSPI, MMCIF, MFI, H-UDI, ADC, CMT, TMU, WDT, or REF) interrupt level, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'0000 0600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The module interrupt levels should be set as values between B'0000 and B'1111 in the interrupt priority level setting registers (IPRA-IPRC) in the interrupt controller. For details, see section 9, Interrupt Controller (INTC).
Module_interruption() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 0400 ~ H'0000 0FA0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0600; }
Rev. 1.0, 02/03, page 198 of 1294
(4) IRQ Interrupts * Source: The interrupt mask bit setting in SR is smaller than the IRL (3-0) level, and the BL bit in SR is 0 (accepted at instruction boundary). * Transition address: VBR + H'0000 0600 * Transition operations: The PC contents immediately after the instruction at which the interrupt is accepted are set in SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR. The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. The IRQ interrupt levels should be set as values between B'0000 and B'1111 in the interrupt priority level setting register 00 (INTPRI00) in the interrupt controller. For details, see section 9, Interrupt Controller (INTC).
IRQ() { SPC = PC; SSR = SR; SGR = R15; INTEVT = H'0000 0800 ~ H'0000 0860; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0600; }
Rev. 1.0, 02/03, page 199 of 1294
8.5.4
Priority Order with Multiple Exceptions
With some instructions, such as instructions that make two accesses to memory, and the indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple exceptions occur. Care is required in these cases, as the exception priority order differs from the normal order. * Instructions that make two accesses to memory With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS instructions, two data transfers are performed by a single instruction, and an exception will be detected for each of these data transfers. In these cases, therefore, the following order is used to determine priority. 1. Data address error in first data transfer 2. TLB miss in first data transfer 3. TLB protection violation in first data transfer 4. Initial page write exception in first data transfer 5. Data address error in second data transfer 6. TLB miss in second data transfer 7. TLB protection violation in second data transfer 8. Initial page write exception in second data transfer * Indivisible delayed branch instruction and delay slot instruction As a delayed branch instruction and its associated delay slot instruction are indivisible, they are treated as a single instruction. Consequently, the priority order for exceptions that occur in these instructions differs from the usual priority order. The priority order shown below is for the case where the delay slot instruction has only one data transfer. 1. A check is performed for the interrupt type and re-execution type exceptions of priority levels 1 and 2 in the delayed branch instruction. 2. A check is performed for the interrupt type and re-execution type exceptions of priority levels 1 and 2 in the delay slot instruction. 3. A check is performed for the completion type exception of priority level 2 in the delayed branch instruction. 4. A check is performed for the completion type exception of priority level 2 in the delay slot instruction. 5. A check is performed for priority level 3 in the delayed branch instruction and priority level 3 in the delay slot instruction. (There is no priority ranking between these two.) 6. A check is performed for priority level 4 in the delayed branch instruction and priority level 4 in the delay slot instruction. (There is no priority ranking between these two.) If the delay slot instruction has a second data transfer, two checks are performed in step 2, as in the above case (Instructions that make two accesses to memory).
Rev. 1.0, 02/03, page 200 of 1294
If the accepted exception (the highest-priority exception) is a delay slot instruction reexecution type exception, the branch instruction PR register write operation (PC PR operation performed in a BSR, BSRF, or JSR instruction) is not disabled.
8.6
Usage Notes
1. Return from exception handling A. Check the BL bit in SR with software. If SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR contents are saved in SR, and branch is made to the SPC address to return from the exception handling routine. 2. If an exception or interrupt occurs when BL bit in SR = 1 A. Exception When an exception other than a user break occurs, a manual reset is executed. The value in EXPEVT at this time is H'0000 0020; the SPC and SSR contents are undefined. B. Interrupt If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting made by software. In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set to 1. 3. SPC when an exception occurs A. Re-execution type exception The PC value for the instruction at which the exception occurred is set in SPC, and the instruction is re-executed after returning from the exception handling routine. If an exception occurs in a delay slot instruction, however, the PC value for the delay slot instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied. B. Completion type exception or interrupt The PC value for the instruction following that at which the exception occurred is set in SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value for the branch destination is saved in SPC. 4. An exception must not be generated in an RTE instruction delay slot, as the operation cannot be guaranteed in this case.
Rev. 1.0, 02/03, page 201 of 1294
8.7
8.7.1
Restrictions
Restrictions on First Instruction in Exception Handling Routine
* Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR + H'400, or VBR + H'600. * When the UBDE bit in BRCR is set to 1 and the user break debug support function is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address indicated by DBR.
Rev. 1.0, 02/03, page 202 of 1294
Section 9 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to user-set priority.
9.1
Features
The INTC has the following features. * Fifteen interrupt priority levels can be set By setting the eight interrupt priority level setting registers, the priorities of peripheral module interrupts can be selected from 15 levels for different request sources. * NMI noise canceler function The NMI input level bit indicates the NMI pin state. The pin state can be checked by reading this bit in the interrupt exception handling routine, enabling it to be used as a noise canceler. * NMI request masking when the BL bit in SR is set to 1. It is possible to select whether or not NMI requests are to be masked when the BL bit in SR is set to 1.
Rev. 1.0, 02/03, page 203 of 1294
Figure 9.1 shows a block diagram of the INTC.
IRQ7-IRQ4 NMI IRL3-IRL0 Peripheral modules WDT REF DMAC H-UDI GPIO
4 Input control 4 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) CPU 4 Comparator Interrupt request SR I3 I2 I1 I0
Priority identifier
IPRA-IPRD ICR
INTPRI00- INTPRI0C
Bus interface INTC Note : Peripheral modules: The following 14 modules can output interrupt requests. The number of channel is enclosed within parentheses. HCAN2 (2) SSI (2) HAC (2) I2C (2) USB LCDC SCIF (3) SIM HSPI MMCIF MFI ADC CMT TMU (3) Legend: : Watchdog timer : Memory refresh controller section of the bus state controller : Direct memory access controller DMAC : Hitachi user debug interface H-UDI : General I/O ports GPIO : Interrupt control register ICR : Interrupt priority level setting registers A-D IPRA-IPRD INTPRI00-0C : Interrupt priority level setting registers 00-0C : Status register SR WDT REF : Hitachi Controller Area Network 2 : Serial Sound Interface : Hitachi Audio Codec Interface : I2C Bus Interface : USB Host : LCD Controller : Serial Communication Interface with FIFO : SIM Card Module : Hitachi Serial Peripheral Interface : Multimedia Card Interface : Multifunctional Interface : A/D Converter : Compare Match Timer : Timer Unit
Figure 9.1 Block Diagram of INTC
Rev. 1.0, 02/03, page 204 of 1294
Peripheral bus
9.2
Input/Output Pins
Table 9.1 shows the INTC pin configuration. Table 9.1
Pin Name Nonmaskable interrupt input pin IRL interrupt input pins IRQ interrupt input pins
Pin Configuration
Abbreviation NMI IRL3 to IRL0 IRQ7 to IRQ4 I/O Input Input Input Function Input of nonmaskable interrupt request signal Input of IRL interrupt request signals (maskable by the I3 to I0 bits in SR) Input of IRQ interrupt request signals
9.3
Register Descriptions
The INTC has the following registers. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 9.2 Register Configuration (1)
Abbrev.
ICR IPRA IPRB IPRC IPRD INTPRI00 INTPRI04 INTPRI08
Register Name
Interrupt control register Interrupt priority level setting register A Interrupt priority level setting register B Interrupt priority level setting register C Interrupt priority level setting register D Interrupt priority level setting register 00 Interrupt priority level setting register 04 Interrupt priority level setting register 08
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
P4 Address
H'FFD0 0000 H'FFD0 0004 H'FFD0 0008 H'FFD0 000C H'FFD0 0010 H'FE08 0000 H'FE08 0004 H'FE08 0008 H'FE08 000C H'FE08 0020 H'FE08 0024 H'FE08 0040 H'FE08 0044 H'FE08 0060
Area 7 Address Size
H'1FD0 0000 H'1FD0 0004 H'1FD0 0008 H'1FD0 000C H'1FD0 0010 H'1E08 0000 H'1E08 0004 H'1E08 0008 H'1E08 000C H'1E08 0020 H'1E08 0024 H'1E08 0040 H'1E08 0044 H'1E08 0060 16 16 16 16 16 32 32 32 32 32 32 32 32 32
Sync Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Interrupt priority level setting register 0C INTPRI0C R/W Interrupt source register 00 Interrupt source register 04 Interrupt mask register 00 Interrupt mask register 04 Interrupt mask clear register 00 INTREQ00 R INTREQ04 R INTMSK00 R/W INTMSK04 R/W INTMSK CLR00 INTMSK CLR04 W
Interrupt mask clear register 04
W
H'FE08 0064
H'1E08 0064
32
Pck
Rev. 1.0, 02/03, page 205 of 1294
Table 9.2
Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI
H'0000*
1
Register Name
Interrupt control register Interrupt priority level setting register A Interrupt priority level setting register B Interrupt priority level setting register C Interrupt priority level setting register D Interrupt priority level setting register 00 Interrupt priority level setting register 04 Interrupt priority level setting register 08 Interrupt priority level setting register 0C Interrupt source register 00 Interrupt source register 04 Interrupt mask register 00 Interrupt mask register 04 Interrupt mask clear register 00
Abbrev.
ICR
Manual Reset by RESET Pin/WDT/ Multiple Exception
H'0000* H'8000* H'0000 H'0000 H'0000 H'DA74
1
Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained -- * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained --
H'8000* IPRA IPRB IPRC IPRD H'0000 H'0000 H'0000 H'DA74
2
2
INTPRI00 H'0000 0000 Retained INTPRI04 H'0000 0000 Retained INTPRI08 H'0000 0000 Retained INTPRI0C H'0000 0000 Retained INTREQ00 H'0000 0000 Retained INTREQ04 H'0000 0000 Retained INTMSK00 H'F3FF 7FFF Retained INTMSK04 H'00FF FFFF Retained INTMSK CLR00 INTMSK CLR04 -- --
Interrupt mask clear register 04
--
--
--
--
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. 1. The NMI pin is a low level. 2. The NMI pin is a high level.
Rev. 1.0, 02/03, page 206 of 1294
9.3.1
Interrupt Priority Level Setting Registers A to D (IPRA to IPRD)
IPRA to IPRD are 16-bit readable/writable registers that set priority levels from 15 to 0 for the peripheral module interrupts. * IPRA to IPRC
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 IPRn 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name IPRn
Initial Value All 0
R/W R/W
Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 9.3, Interrupt Request Sources and IPRA to IPRD.
Note: n = 15 to 0
* IPRD
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 IPRn 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name IPRn
Initial Value H'DA74
R/W R/W
Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 9.3, Interrupt Request Sources and IPRA to IPRD.
Note: n = 15 to 0
Rev. 1.0, 02/03, page 207 of 1294
Table 9.3
Interrupt Request Sources and IPRA to IPRD
Bits
Register IPRA IPRB IPRC IPRD
15 to 12 TMU0 WDT GPIO (IRL, IRQ)* IRL0
3
11 to 8 TMU1 REF*
1
7 to 4 TMU2 Reserved* Reserved* IRL2
2 2
3 to 0 Reserved* Reserved* H-UDI IRL3
2 2
DMAC IRL1
Notes: 1. REF is the memory refresh control unit in the bus state controller (BSC). See section 10, Bus State Controller (BSC), for details. 2. Reserved: These bits are always read as 0. The write value should always be 0. 3. These bits set the interrupt priority level of the GPIO in normal mode and that of the GPIO, IRL, IRQ4, and IRQ5 in software standby mode. To exit software standby mode by an IRQ4 or IRQ5 interrupt, INTPRI00 must also be set. The same value must be set in both registers. Note that software standby mode cannot be exited by an IRQ6 or IRQ7 interrupt.
As shown in table 9.3, four peripheral modules are assigned to each register. Setting a value from H'F (1111) to H'0 (0000) in each of the 4-bit groups, 15 to 12, 11 to 8, 7 to 4, and 3 to 0, configures interrupt priority level for each group. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). 9.3.2 Interrupt Priority Level Setting Registers 00 to 0C (INTPRI00 to INTPRI0C)
INTPRI00 to INTPRI0C are 32-bit readable/writable registers that set priority levels from 15 to 0 for the peripheral module interrupts.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name
Initial Value All 0
R/W R/W
Description These bits set the priority level for each interrupt source in 4-bit units. For details, see table 9.4, Interrupt Request Sources and INTPRI00 to INTPRI0C.
Rev. 1.0, 02/03, page 208 of 1294
Table 9.4
Interrupt Request Sources and INTPRI00 to INTPRI0C*
Bits
1
Register INTPRI00 INTPRI04 INTPRI08 INTPRI0C
31 to 28 IRQ4*
3
27 to 24 IRQ5*
3
23 to 20 IRQ6 SSI(0) DMABRG
2
19 to 16 IRQ7 SSI(1) SCIF(0) Reserved*
2
15 to 12 Reserved* HAC(0) SCIF(1) MFI
2
11 to 8 Reserved* HAC(1) SCIF(2) Reserved*
2 2
7 to 4 Reserved* I2C(0) SIM ADC
2
3 to 0 Reserved*2 I2C(1) HSPI CMT
HCAN2(0) USB Reserved*
2
HCAN2(1) LCDC Reserved*
MMCIF
Notes: 1. As shown in table 9.4, eight peripheral modules are assigned to each register. Setting a value from H'F (1111) to H'0 (0000) in each of the 4-bit groups configures interrupt priority level for each group. Setting H'F designates priority level 15 (the highest level), and setting H'0 designates priority level 0 (requests are masked). 2. Reserved: These bits are always read as 0. The write value should always be 0. 3. To enable an IRQ4 or IRQ5 interrupt in software standby mode, setting must be made in this register as well as in IPRC. The same value must be set in both registers. Note that software standby mode cannot be exited by an IRQ6 or IRQ7 interrupt.
9.3.3
Interrupt Control Register (ICR)
ICR sets the input signal detection mode for external interrupt input pin NMI and indicates the input signal level at the NMI pin.
Bit: Initial value: R/W: 15 NMIL 0/1* R 14 MAI 0 R/W 13 0 12 0 11 0 10 0 9 8 7 6 0 5 0 4 0 3 0 2 0 1 0 0 0 -
NMIB NMIE IRLM 0 R/W 0 R/W 0 R/W
Bit 15
Bit Name NMIL
Initial Value 0/1*
R/W R
Description NMI Input Level Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. It cannot be modified. 0: NMI pin input level is low 1: NMI pin input level is high
Rev. 1.0, 02/03, page 209 of 1294
Bit 14
Bit Name MAI
Initial Value 0
R/W R/W
Description NMI Interrupt Mask Specifies whether or not all interrupts are to be masked while the NMI pin input level is low, irrespective of the BL bit in SR of the CPU. NMI interrupts are accepted in normal operation and in sleep mode. In standby mode, all interrupts are masked, and standby is not cleared, while the NMI pin is low. 0: Interrupts enabled even while NMI pin is low 1: Interrupts disabled while NMI pin is low
13 to 10 --
All 0
--
Reserved These bits are always read as 0.The write value should always be 0. NMI Block Mode Specifies whether an NMI request is to be held pending or detected immediately while the BL bit in SR of the CPU is set to 1. If interrupt requests are enabled while the BL bit is 1, the previous exception information will be lost, and so must be saved beforehand. This bit is cleared automatically by NMI acceptance. 0: NMI interrupt requests held pending while the BL bit in SR is set to 1 1: NMI interrupt requests detected while the BL bit in SR is set to 1
9
NMIB
0
R/W
8
NMIE
0
R/W
NMI Edge Select Specifies whether the falling or rising edge of the interrupt request signal to the NMI pin is detected. 0: Interrupt request detected on falling edge of NMI input 1: Interrupt request detected on rising edge of NMI input
7
IRLM
0
R/W
IRL Pin Mode Specifies whether pins IRL3 to IRL0 are to be used as level-encoded interrupt requests or as four independent interrupt requests. 0: IRL pins used as level-encoded interrupt requests 1: IRL pins used as four independent interrupt requests (level-sensing IRQ mode)
Rev. 1.0, 02/03, page 210 of 1294
Bit 6 to 0
Bit Name --
Initial Value All 0
R/W --
Description Reserved These bits are always read as 0.The write value should always be 0.
Note: * 1 when NMI pin input is high, 0 when low.
9.3.4
Interrupt Source Registers 00, 04 (INTREQ00, INTREQ04)
INTREQ00 and INTREQ04 are 32-bit read-only registers that indicate the origin of the interrupt request sent to the INTC. The states of the bits in these registers are not affected by masking of the corresponding interrupts by the settings in INTPRI00 and INTPRI04.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
0 R 7
0 R 6
0 R 5
0 R 4
0 R 3
0 R 2
0 R 1
0 R 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 0
Bit Name
Initial Value All 0
R/W R
Description Interrupt Requests 31 to 0 Each bit indicates that there is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt sources, see table 9.5. 0: There is no interrupt request that corresponds to this bit 1: There is an interrupt request that corresponds to this bit.
Rev. 1.0, 02/03, page 211 of 1294
Table 9.5
Interrupt Request Sources and Bit Assignments in Each Register (1)
* INTREQ00, INTMSK00, and INTMSKCLR00
Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Module IRQ IRQ IRQ IRQ HCAN2(0) HCAN2(1) SSI(0) SSI(1) HAC(0) HAC(1) I C(0) I C(1) USB LCDC
2 2
Interrupt IRQ4 IRQ5 IRQ6 IRQ7 HCANI0 HCANI1 SSII0 SSII1 HACI0 HACI1 IICI0 IICI1 USBI VINT
Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Module DMABRG DMABRG DMABRG SCIF(0) SCIF(0) SCIF(0) SCIF(0) SCIF(1) SCIF(1) SCIF(1) SCIF(1) SCIF(2) SCIF(2) SCIF(2) SCIF(2)
Interrupt DMABRGI0 DMABRGI1 DMABRGI2 ERI0 RXI0 BRI0 TXI0 ERI1 RXI1 BRI1 TXI1 ERI2 RXI2 BRI2 TXI2
Rev. 1.0, 02/03, page 212 of 1294
Table 9.5
Interrupt Request Sources and Bit Assignments in Each Register (2)
* INTREQ04, INTMSK04, and INTMSKCLR04
Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Module SIM SIM SIM SIM HSPI MMCIF MMCIF MMCIF Interrupt SIMERI SIMRXI SIMTXI SIMTEI HSPII MMCI0 MMCI1 MMCI2 Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Module MMCIF MFI ADC CMT Interrupt MMCI3 MFII ADI CMTI
9.3.5
Interrupt Mask Registers 00, 04 (INTMSK00, INTMSK04)
INTMSK00 and INTMSK04 are 32-bit registers that set the masking of individual interrupt requests. Writing 1 to the corresponding bits in INTMSK00 and INTMSK04 masks interrupt requests. To cancel masking of an interrupt, write 1 to the corresponding bit in INTMSKCLR00 and INTMSKCLR04. Note that writing 0 to the related bit in INTMSK00 and INTMSK04 does not cancel masking of the interrupt.
Rev. 1.0, 02/03, page 213 of 1294
* INTMSK00
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
0 R 11
0 R 10
1 R/W 9
1 R/W 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
0 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 28
Bit Name
Initial Value All 1
R/W R/W
Description Interrupt Masks 31 to 28 These bits set the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see table 9.5. 0: Corresponding interrupt requests are accepted 1: Corresponding interrupt requests are masked
27, 26
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
25 to 16
All 1
R/W
Interrupt Masks 25 to 16 These bits set the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see table 9.5. 0: Corresponding interrupt requests are accepted 1: Corresponding interrupt requests are masked
15
0
R
Reserved This bit is always read as 0. The write value should always be 0.
14 to 0
All 1
R/W
Interrupt Masks 14 to 0 These bits set the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see table 9.5. 0: Corresponding interrupt requests are accepted 1: Corresponding interrupt requests are masked
Rev. 1.0, 02/03, page 214 of 1294
* INTMSK04
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 R 15
0 R 14
0 R 13
0 R 12
0 R 11
0 R 10
0 R 9
0 R 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
1 R/W
1 R
1 R
1 R
1 R
1 R
1 R
1 R
1 R
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 31 to 24
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
23 to 15
All 1
R/W
Interrupt Masks 23 to 15 These bits set the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see table 9.5. 0: Corresponding interrupt requests are accepted 1: Corresponding interrupt requests are masked
14 to 7
All 1
R
Reserved These bits are read as 1s at the first time. After that, these bits are read as 0s. The write value should always be 0.
6 to 0
All 1
R/W
Interrupt Masks 6 to 0 These bits set the masking of the interrupt request that corresponds to the given bit. For the correspondence between bits and interrupt sources, see table 9.5. 0: Corresponding interrupt requests are accepted 1: Corresponding interrupt requests are masked
Rev. 1.0, 02/03, page 215 of 1294
9.3.6
Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04)
INTMSKCLR00 and INTMSKCLR04 are 32-bit read-only registers that clear the masking of individual interrupt requests.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 W 15 W 30 W 14 W 29 W 13 W 28 W 12 W 27 W 11 W 26 W 10 W 25 W 9 W 24 W 8 W 23 W 7 W 22 W 6 W 21 W 5 W 20 W 4 W 19 W 3 W 18 W 2 W 17 W 1 W 16 W 0 W
Bit 31 to 0
Bit Name
--
Initial Value
--
R/W W
Description Interrupt Mask Clear 31 to 0 Each bit selects whether or not to clear the masking of the interrupt source that corresponds to that bit. For the correspondence between the bits and interrupt sources, see table 9.5. 0: Masking of corresponding interrupt is not changed 1: Masking of corresponding interrupt is cleared
Rev. 1.0, 02/03, page 216 of 1294
9.4
Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, IRL, and peripheral modules. Each interrupt has a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 9.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in SR of the CPU is set to 1. In sleep or standby mode, the interrupt is accepted even if the BL bit is set to 1. A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR is used to select either rising or falling edge as the detection edge. When the NMIE bit in ICR is modified, the NMI interrupt is not detected for a maximum of six bus clock cycles after the modification. NMI interrupt exception handling does not affect the interrupt mask level bits (IMASK3 to IMASK0) in SR. 9.4.2 IRQ Interrupts
IRQ interrupts are input by level at pins IRQ7 to IRQ4. After an IRQ interrupt is accepted, the pin level must be retained until the interrupt processing starts. 9.4.3 IRL Interrupts
IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the level indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 9.2 shows an example of IRL interrupt connection, and table 9.6 shows the correspondence between the IRL pins and interrupt levels.
Rev. 1.0, 02/03, page 217 of 1294
This LSI
Interrupt requests
Priority encoder
IRL3 to IRL0 IRL3 to IRL0
Figure 9.2 Example of IRL Interrupt Connection Table 9.6
IRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
IRL3 to IRL0 Pins and Interrupt Levels
IRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request
IRL interrupt detection requires a built-in noise-cancellation feature. The IRL interrupt is not detected unless the levels sampled at every bus clock cycle remain unchanged for three consecutive cycles, so that no transient level on the IRL pin change is detected. The priority level of the IRL interrupt must not be lowered until the interrupt is accepted and the interrupt processing starts. However, the priority level can be changed to a higher one. The interrupt mask level bits (IMASK3 to IMASK0) in the status register (SR) are not affected by IRL interrupt processing.
Rev. 1.0, 02/03, page 218 of 1294
Pins IRL0 to IRL3 can be used for four independent interrupt requests by setting the IRLM bit in ICR to 1. When independent interrupt requests are used, the interrupt priority levels can be set in interrupt priority level setting register D (IPRD). 9.4.4 Peripheral Module Interrupts
Peripheral module interrupts are interrupts generated by peripheral modules. Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the interrupt event register (INTEVT), so it is easy to identify sources by using the INTEVT value as a branch offset in the exception handling routine. A priority level from 15 to 0 can be set for each module by means of IPRA to IPRD and INTPRI00 to INTPRI0C. The interrupt mask level bits (IMASK3 to IMASK0) in SR are not affected by peripheral module interrupt processing. Updating of the interrupt source flag and interrupt enable flag of a peripheral module should only be carried out when the BL bit in SR is set to 1. To prevent erroneous interrupt acceptance from an interrupt source that should have been updated, first read the on-chip peripheral register containing the relevant flag, then clear the BL bit to 0. This will secure the necessary timing internally. When updating a number of flags, there is no problem if only the register containing the last flag updated is read from. If flag updating is performed while the BL bit is cleared to 0, the program may jump to the interrupt handling routine when the INTEVT value is 0. In this case, interrupt processing is initiated due to the timing relationship between the flag update and interrupt request recognition within this LSI. Processing can be continued without any problem by executing an RTE instruction.
Rev. 1.0, 02/03, page 219 of 1294
9.4.5
Interrupt Exception Handling and Priority
Table 9.7 lists the codes for the interrupt event register (INTEVT), and the order of interrupt priority. Each interrupt source is assigned a unique INTEVT code. The start address of the exception handling routine is common to each interrupt source. Therefore, to identify the interrupt source, branching is performed at the start of the exception handling routine using the INTEVT value. For instance, the INTEVT value is used as a branch offset . The priority order of the peripheral modules is specified as desired by setting priority levels from 15 to 0 in IPRA to IPRD and INTPRI00 to INTPRI0C. The priority order of the peripheral modules is set to 0 by a reset. When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated simultaneously, they are handled according to the default priority order shown in table 9.7. Updating of IPRA to IPRD and INTPRI00 to INTPRI0C should only be carried out when the BL bit in SR is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt priority level setting registers, then clear the BL bit to 0. This will secure the necessary timing internally.
Rev. 1.0, 02/03, page 220 of 1294
Table 9.7
Interrupt Exception Handling Sources and Priority Order
INTEVT Interrupt Priority Relevant IPR Priority within Default Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority H'1C0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 to 0 (13) 15 to 0 (10) 15 to 0 (7) 15 to 0 (4) 15 to 0 (0) 15 to 0 (0) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High
Interrupt Source NMI
IRL3 to IRL3 to IRL0 = 0 H'200 IRL0 IRL3 to IRL0 = 1 H'220 IRL3 to IRL0 = 2 H'240 IRL3 to IRL0 = 3 H'260 IRL3 to IRL0 = 4 H'280 IRL3 to IRL0 = 5 H'2A0 IRL3 to IRL0 = 6 H'2C0 IRL3 to IRL0 = 7 H'2E0 IRL3 to IRL0 = 8 H'300 IRL3 to IRL0 = 9 H'320 IRL3 to IRL0 = A H'340 IRL3 to IRL0 = B H'360 IRL3 to IRL0 = C H'380 IRL3 to IRL0 = D H'3A0 IRL3 to IRL0 = E H'3C0 IRL IRL0 IRL1 IRL2 IRL3 H-UDI GPIO H-UDI GPIOI H'240 H'2A0 H'300 H'360 H'600 H'620
IPRD (15 to 12) -- IPRD (11 to 8) -- IPRD (7 to 4) IPRD (3 to 0) IPRC (3 to 0) -- -- -- Low
IPRC (15 to 12) --
Rev. 1.0, 02/03, page 221 of 1294
Interrupt Source DMAC DMTE0 DMTE1 DMTE2 DMTE3 DMTE4 DMTE5 DMTE6 DMTE7 DMAE IRQ IRQ4 IRQ5 IRQ6 IRQ7 HCAN2(0) CANI0 HCAN2(1) CANI1 SSI(0) SSI(1) HAC(0) HAC(1) I C(0) I C(1)
2 2
INTEVT Interrupt Priority Relevant IPR Priority within Default Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 H'800 H'820 H'840 H'860 H'900 H'920 H'940 H'960 H'980 H'9A0 H'9C0 H'9E0 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) INTPRI00 (31 to 28) INTPRI00 (27 to 24) INTPRI00 (23 to 20) INTPRI00 (19 to 16) INTPRI04 (31 to 28) INTPRI04 (27 to 24) INTPRI04 (23 to 20) INTPRI04 (19 to 16) INTPRI04 (15 to 12) INTPRI04 (11 to 8) INTPRI04 (7 to 4) INTPRI04 (3 to 0) Low Low Low High 15 to 0 (0) IPRC (11 to 8) High High
SSII0 SSII1 HACI0 HACI1 IICI0 IICI1
Rev. 1.0, 02/03, page 222 of 1294
Interrupt Source USB LCDC USBI VINT
INTEVT Interrupt Priority Relevant IPR Priority within Default Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority H'A00 H'A20 H'A80 H'AA0 H'AC0 H'880 H'8A0 H'8C0 H'8E0 H'B00 H'B20 H'B40 H'B60 H'B80 H'BA0 H'BC0 H'BE0 H'C00 H'C20 H'C40 H'C60 H'C80 H'D00 H'D20 H'D40 H'D60 Low Low 15 to 0 (0) 15 to 0 (0) INTPRI08 (3 to 0) INTPRI0C (23 to 20) High Low 15 to 0 (0) INTPRI08 (7 to 4) Low High 15 to 0 (0) INTPRI08 (11 to 8) Low High 15 to 0 (0) INTPRI08 (15 to 12) Low High 15 to 0 (0) INTPRI08 (19 to 16) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) INTPRI08 (31 to 28) INTPRI08 (27 to 24) INTPRI08 (23 to 20) High Low High High
DMABRG DMABRGI0 DMABRGI1 DMABRGI2 SCIF(0) ERI0 RXI0 BRI0 TXI0 SCIF(1) ERI1 RXI1 BRI1 TXI1 SCIF(2) ERI2 RXI2 BRI2 TXI2 SIM SIMERI SIMRXI SIMTXI SIMTEI HSPI MMCIF HSPII MMCI0 MMCI1 MMCI2 MMCI3
Rev. 1.0, 02/03, page 223 of 1294
Interrupt Source MFI -- MFII -- -- -- -- ADC CMT TMU0 TMU1 TMU2 ADI CMTI TUNI0 TUNI1 TUNI2 TICPI2 WDT REF
Note:
INTEVT Interrupt Priority Relevant IPR Priority within Default Code (Initial Value) (Bit Numbers) IPR Setting Unit Priority H'F80 H'F00 H'F20 H'F40 H'F60 H'F80 H'FA0 H'400 H'420 H'440 H'460 H'560 H'580 H'5A0
: Underflow interrupts : Input capture interrupt : Receive-error interrupt : Receive-data-full interrupt : Transmit-data-empty interrupt : Transmit-end interrupt : Break interrupt request : Interval timer interrupt : Compare-match interrupt : Refresh count overflow interrupt : Hitachi user debug interface : DMAC transfer end interrupts : DMAC address error interrupt : Vertical synchronization interrupt
15 to 0 (0) 15 to 0 (0)
INTPRI0C (15 to 12) INTPRI0C (11 to 8) High
High
Low 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) 15 to 0 (0) INTPRI0C (7 to 4) INTPRI0C (3 to 0) IPRA (15 to 12) -- IPRA (11 to 8) IPRA (7 to 4) -- High Low 15 to 0 (0) 15 to 0 (0) IPRB (15 to 12) -- IPRB (11 to 8) High Low Low
ITI RCMI ROVI
TUNI0 to TUNI2 TICPI2 ERI RXI TXI SIMTEI BRI ITI RCMI ROVI H-UDI DMTE0 to DMTE7 DMAE VINT
Rev. 1.0, 02/03, page 224 of 1294
9.5
9.5.1
Operation
Interrupt Operation Sequence
The sequence of operations when an interrupt is generated is described below. Figure 9.3 shows a flowchart of the interrupt operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in IPRA to IPRD and INTPRI00 to INTPRI0C. Lowerpriority interrupts are held pending. If two of these interrupts have the same priority level, or if multiple interrupts occur within a single module, the interrupt with the highest priority according to table 9.4 is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask level (IMASK3 to IMASK0) in SR of the CPU. If the request's priority level is higher than the level in bits IMASK3 to IMASK0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. The CPU accepts an interrupt between instructions. 5. The interrupt source code is set in the interrupt event register (INTEVT). 6. The contents of the status register (SR) and program counter (PC) are saved to SSR and SPC, respectively. The R15 contents at this time are saved in SGR. 7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1. 8. The CPU jumps to the start address of the interrupt-related exception handling routine (the sum of the value set in the vector base register (VBR) and H'0000 0600). The exception handling routine may branch with the INTEVT value as its offset in order to identify the interrupt source. This enables it to easily branch to the handling routine for the particular interrupt source. Notes: 1. In this LSI, the interrupt mask level bits (IMASK3 to IMASK0) in the status register (SR) of the CPU are not changed by acceptance of an interrupt. 2. Clear the interrupt source flag during the interrupt handling routine. To ensure that the cleared interrupt source is not inadvertently accepted again, read the interrupt source flag after it has been cleared, wait for the interval shown in table 9.8, and then clear the BL bit or execute an RTE instruction. 3. For some interrupt sources, the interrupt masks (INTMSK00 and INTMSK04) must be cleared using INTMSKCLR00 and INTMSKCLR04.
Rev. 1.0, 02/03, page 225 of 1294
Program execution state
Interrupt generated? Yes (BL bit in SR = 0) or (sleep or standby mode)? Yes NMI? Yes
No
No
NMIB in ICR = 1 and NMI? No Yes
No
Level 15 interrupt? Yes Yes
IMASK3-IMASK0* = level 14 or lower?
No
Level 14 interrupt? Yes
IMASK3-IMASK0 = level 13 or lower?
No
No Set interrupt source in INTEVT Save SR to SSR and save PC to SPC Set BL, MD, and RB bits in SR to 1 Branch to exception handling routine
Yes
Level 1 interrupt? Yes
IMASK3-IMASK0 = level 0?
No
No Yes
No
Note: * IMASK3-IMASK0: Interrupt mask level bits in status register (SR)
Figure 9.3 Interrupt Operation Flowchart
Rev. 1.0, 02/03, page 226 of 1294
9.5.2
Multiple Interrupts
When handling multiple interrupts, the interrupt handling routine should include the following procedures: 1. Branch to the interrupt handling routine of each interrupt source using the INTEVT value as an offset to identify the interrupt source. 2. Clear the interrupt source in the corresponding interrupt handling routine. 3. Save SPC and SSR in the stack. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask level bits (IMASK3 to IMASK0) in SR. 5. Write the actual processing. 6. Set the BL bit in SR to 1. 7. Restore SSR and SPC from memory. 8. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted immediately after step 4. This enables the interrupt response time to be shortened for urgent processing. 9.5.3 Interrupt Masking with MAI Bit
By setting the MAI bit to 1 in ICR, interrupts can be masked while the NMI pin is low, irrespective of the BL and IMASK bits in SR. * In normal operation and sleep mode All interrupts are masked while the NMI pin is low. However, an NMI interrupt only is generated by a transition at the NMI pin. * In standby mode All interrupts are masked while the NMI pin is low, and an NMI interrupt is not generated by a transition at the NMI pin. Therefore, standby mode cannot be cleared by an NMI interrupt while the MAI bit is set to 1.
Rev. 1.0, 02/03, page 227 of 1294
9.6
Interrupt Response Time
The time from interrupt request generation until interrupt exception handling is performed and fetching of the first instruction of the exception handling routine is started (the interrupt response time) is shown in table 9.8. Table 9.8 Interrupt Response Time
Number of States Item Time for priority decision and SR mask bit comparison Wait time until end of sequence being executed by CPU Time from interrupt exception handling (save of SR and PC) until fetch of first instruction of exception handling routine is started Response time Total Minimum case Maximum case NMI 1 Icyc + 4 Bcyc S - 1 ( 0) x Icyc 4 x Icyc IRL IRQ Peripheral Modules 1 Icyc + 2 Bcyc S - 1 ( 0) x Icyc 4 x Icyc Notes
1 Icyc + 7 Bcyc S - 1 ( 0) x Icyc 4 x Icyc
5 Icyc + 4 Bcyc + (S - 1) Icyc 13 Icyc 36 + S Icyc
5 Icyc + 7 Bcyc + (S - 1) Icyc 19 Icyc 60 + S Icyc
5 Icyc + 2 Bcyc + (S - 1) Icyc 9 Icyc 20 + S Icyc When Icyc: Bcyc = 2:1 When Icyc: Bcyc = 8:1
Icyc : One cycle of internal clock supplied to CPU, etc. Bcyc : One CKIO cycle S : Number of instruction execution states
Rev. 1.0, 02/03, page 228 of 1294
Section 10 Bus State Controller (BSC)
The BSC divides the off-chip memory space and outputs control signals complying with specifications of various types of memory and bus interfaces. It enables the connection of synchronous DRAM, SRAM, ROM, etc., to this LSI. It also supports the PCMCIA interface protocol, which implements simplified system design and high-speed data transfers by a compact system.
10.1
Features
The BSC has the following features: * Divides the off-chip memory space into seven areas for management. Maximum 64 Mbytes for each of areas 0 to 6 Bus width of each area can be controlled by register settings (except area 0, which uses an off-chip pin setting) Wait-cycle insertion by RDY pin Wait-cycle insertion can be controlled by program Types of memory are specifiable for connection to each area Output the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different areas, or a read access followed by a write access to the same area Write strobe setup time and hold time periods can be inserted in a write cycle to enable connection to low-speed memory * SRAM interface Wait-cycle insertion can be controlled by program Wait-cycle insertion by RDY pin Connectable areas: 0 to 6 Settable bus widths: 32, 16, 8 * Synchronous DRAM interface Row address/column address multiplexing according to synchronous DRAM capacity Burst operation Auto-refresh and self-refresh Synchronous DRAM control signal timing can be controlled by register settings Consecutive accesses to the same row address Connectable areas: 2, 3 Settable bus width: 32
Rev. 1.0, 02/03, page 229 of 1294
* Burst ROM interface Wait-cycle insertion can be controlled by program Burst transfer for the number of times specified by the register Connectable areas: 0, 5, 6 Settable bus widths: 32, 16, 8 * MPX interface Address/data multiplexing Peripheral LSI, which requires address/data multiplexing, can be connected Connectable areas: 0 to 6 Settable bus width: 32 * Byte control SRAM interface SRAM interface with byte control Connectable areas: 1, 4 Settable bus widths: 32, 16 * PCMCIA interface (valid only in little-endian mode) Wait-cycle insertion can be controlled by program Bus sizing function for I/O bus width Connectable areas: 5, 6 Settable bus widths: 16, 8 * Refresh counter can be used as interval timer Interrupt request generated by compare-match Interrupt request generated by refresh counter overflow
Rev. 1.0, 02/03, page 230 of 1294
Figure 10.1 shows a block diagram of the BSC.
Bus interface WCR1 Wait control unit WCR2 WCR3 WCR4 CS6-CS0 CE2A-CE2B BS RD RD/WR WE3-WE0 RAS CASS CKE ICIORD, ICIOWR REG IOIS16
Peripheral bus
RDY
Area control unit
BCR1 BCR2
Module bus
BCR3 BCR4 MCR PCR RFCR RTCNT Refresh control unit Comparator
Memory control unit
Interrupt controller
RTCOR RTCSR BSC WCR: BCR: MCR: PCR: Wait control register Bus control register Memory control register PCMCIA control register RFCR: RTCNT: RTCOR: RTCSR: Refresh count register Refresh timer counter Refresh time constant register Refresh timer control/status register
Figure 10.1 Block Diagram of BSC
Rev. 1.0, 02/03, page 231 of 1294
On-chip peripheral bus
10.2
Input/Output Pins
Table 10.1 shows the BSC pin configuration. Table 10.1 Pin Configuration
Name Address bus Data bus Bus cycle start Signals A25 to A0 D31 to D0 BS I/O Description
Output Address output Input/ Output Output Signal that indicates the start of a bus cycle When setting synchronous DRAM interface or MPX interface: asserted once for a burst transfer For other burst transfers: asserted each data cycle Data input/output
Chip select 6 to 0
CS6 to CS0
Output Chip select signals that indicate the area being accessed CS5 and CS6 are also used as PCMCIA CE1A and CE1B
Read/write
RD/WR
Output Data bus input/output direction designation signal Also used as the DRAM/PCMCIA interface write designation signal
Row address strobe Read/column address strobe/ cycle frame
RAS RD/CASS/ FRAME
Output RAS signal when setting synchronous DRAM interface Output Strobe signal that indicates a read cycle When setting synchronous DRAM interface: CAS signal When setting MPX interface: FRAME signal Output When setting PCMCIA interface: REG signal When setting SRAM interface: write strobe signal for D7 to D0 When setting synchronous DRAM interface: selection signal for D7 to D0
Data enable 0
WE0/ DQM0/ REG
Data enable 1
WE1/ DQM1
Output When setting PCMCIA interface: write strobe signal When setting SRAM interface: write strobe signal for D15 to D8 When setting synchronous DRAM interface: selection signal for D15 to D8
Rev. 1.0, 02/03, page 232 of 1294
Name Data enable 2
Signals WE2/ DQM2/ ICIORD
I/O
Description
Output When setting PCMCIA interface: ICIORD signal When setting SRAM interface: write strobe signal for D23 to D16 When setting synchronous DRAM interface: selection signal for D23 to D16
Data enable 3
WE3/ DQM3/ ICIOWR
Output When setting PCMCIA interface: ICIOWR signal When setting SRAM interface: write strobe signal for D31 to D24 When setting synchronous DRAM interface: selection signal for D31 to D24
Ready Area 0 MPX interface setting/ 16-bit I/O Clock enable Bus release request Bus request acknowledge Area 0 bus width/PCMCIA card select
RDY MD6/IOIS16
Input Input
Wait-cycle request signal At power-on reset: Designates area 0 bus as MPX interface (1: SRAM, 0: MPX) When setting PCMCIA interface: 16-bit I/O designation signal. Valid only in little-endian mode.
CKE BREQ BACK MD3/CE2A* MD4/CE2B*
Output Synchronous DRAM clock enable control signal Input Bus release request signal
Output Bus request acknowledge signal Input/ At power-on reset: area 0 bus width specification Output signal When using PCMCIA: CE2A, CE2B Input Endian setting at a power-on reset
Endian switchover MD5
Note: * The input/output switching is specified by the A56PCM bit in bus control register 1 (BCR1).
10.3
Overview of Areas
(1) Space Divisions The architecture of this LSI provides a 32-bit virtual address space. The virtual address space is divided into five areas according to the upper address value. Off-chip memory space comprises a 29-bit address space, divided into eight areas. The virtual address space can be allocated to any off-chip address by means of the memory management unit (MMU). Details are given in section 6, Memory Management Unit (MMU). This section describes the areas into which the off-chip address space is divided.
Rev. 1.0, 02/03, page 233 of 1294
With this LSI, various types of memory or PC cards can be connected to each of the seven areas of off-chip address space as shown in table 10.2, and chip select signals (CS0 to CS6, CE2A, CE2B) are output for each of these areas. CS0 is asserted when accessing area 0, and CS6 when accessing area 6. When synchronous DRAM is connected to area 2 or 3, signals such as RAS, CASS, RD/WR, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or 6, CE2A or CE2B is asserted in addition to CS5 or CS6 for the byte to be accessed.
256 H'0000 0000 Area 0 (CS0) Area 1 (CS1) P0 and U0 areas P0 and U0 areas Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) H'8000 0000 P1 area H'A000 0000 H'C000 0000 P2 area P3 area P1 area P2 area P3 area Store queue area P4 area Area 5 (CS5) Area 6 (CS6) Area 7 (reserved area) H'0000 0000 H'0400 0000 H'0800 0000 H'0C00 0000 H'1000 0000 H'1400 0000 H'1800 0000 H'1C00 0000 H'1FFF FFFF
H'E000 0000 Store queue area H'E400 0000 P4 area H'FFFF FFFF
Physical address space (MMU off)
Virtual address space (MMU on)
External memory space
Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and memory is mapped onto a fixed 29-bit external address. 2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be mapped onto any external address using the TLB.
Figure 10.2 Correspondence between Virtual Address Space and Off-chip Memory Space
Rev. 1.0, 02/03, page 234 of 1294
Table 10.2 Off-chip Memory Space Map
Off-chip Area Addresses 0 H'0000 0000 to H'03FF FFFF H'0400 0000 to H'07FF FFFF H'0800 0000 to H'0BFF FFFF H'0C00 0000 to H'0FFF FFFF H'1000 0000 to H'13FF FFFF H'1400 0000 to H'17FF FFFF Size Connectable Memory Specifiable 12 Bus Width* * 8, 16, 32 8, 16, 32 32 8, 16, 32 32 16, 32 8, 16, 32 32* 32 8, 16, 32 32* 32 8, 16, 32 32 16, 32 8, 16, 32 32 8, 16, 32 8, 16* 32 8, 16, 32 8, 16* --
4 4 6 3 3
Access Size 8, 16, 32, 64* bits, 32 bytes
6
64 Mbytes SRAM Burst ROM MPX 64 Mbytes SRAM MPX Byte control SRAM 64 Mbytes SRAM Synchronous DRAM MPX 64 Mbytes SRAM Synchronous DRAM MPX 64 Mbytes SRAM MPX Byte control RAM 64 Mbytes SRAM MPX Burst ROM PCMCIA 64 Mbytes SRAM MPX Burst ROM PCMCIA 64 Mbytes --
1
8, 16, 32, 64* bits, 32 bytes
6
2
8, 16, 32, 64* bits, 32 bytes
6
3
8, 16, 32, 64* bits, 32 bytes
6
4
8, 16, 32, 64* bits, 32 bytes
6
5
8, 16, 32, 64* bits, 32 bytes
6
6
H'1800 0000 to H'1BFF FFFF
8, 16, 32
8, 16, 32, 64* bits, 32 bytes
7*
5
H'1C00 0000 to H'1FFF FFFF
--
Notes: *1. The memory bus width in area 0 is specified by off-chip pins. *2. The memory bus width in areas other than area 0 is specified by the register. *3. With synchronous DRAM interface, the bus width is 32 bits only. *4. With PCMCIA interface, the bus width is 8 or 16 bits only. *5. Do not access a reserved area, as operation cannot be guaranteed in this case. *6. A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000). In the case of access to off-chip memory by means of FMOV (FPSCR.SZ = 1), two 32-bit access size transfers are performed.
Rev. 1.0, 02/03, page 235 of 1294
Area 0: H'0000 0000 Area 1: H'0400 0000 Area 2: H'0800 0000 Area 3: H'0C00 0000 Area 4: H'1000 0000 Area 5: H'1400 0000 Area 6: H'1800 0000
SRAM/burst ROM/MPX SRAM/MPX/byte control SRAM SRAM/synchronous DRAM/ MPX SRAM/synchronous DRAM/ MPX SRAM/MPX/byte control SRAM SRAM/burst ROM/PCMCIA/MPX SRAM/burst ROM/PCMCIA/MPX The PCMCIA interface is for memory and I/O card use
Figure 10.3 Off-chip Memory Space Allocation (2) Memory Bus Width In this LSI, the memory bus width can be set independently for each area. For area 0, a bus width of 8, 16, or 32 bits can be selected at a power-on reset by a RESET signal, using off-chip pins. The correspondence between the off-chip pins (MD4 and MD3) and the bus width at a power-on reset by a RESET signal is shown below. Table 10.3 Correspondence between Off-chip Pins (MD4 and MD3) and Bus Width
MD4 0 1 MD3 0 1 0 1 Bus Width Reserved (Setting prohibited) 8 bits 16 bits 32 bits
When SRAM interface is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be selected by BCR2. When burst ROM interface is used, a bus width of 8, 16, or 32 bits can be selected. When byte control SRAM interface is used, a bus width of 16 or 32 bits can be selected. When the MPX interface is used, a bus width of 32 bits should be selected. For the synchronous DRAM interface, a bus width of 32 bits should be selected by the MCR register. When using the PCMCIA interface, a bus width of 8 or 16 bits should be selected. The addresses of area 7 (H'1C00 0000 to H'1FFF FFFF) are reserved and must not be used.
Rev. 1.0, 02/03, page 236 of 1294
10.4
PCMCIA Support
This LSI supports PCMCIA interface specifications for off-chip memory space areas 5 and 6. The IC memory card interface and I/O card interface prescribed in JEIDA specifications version 4.2 (PCMCIA2.1) are supported. The PCMCIA interface is only supported in little endian mode. Table 10.4 PCMCIA Interface Features
Item Access Data bus Memory type Common memory capacity Attribute memory capacity Others Features Random access 8/16 bits Masked ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Max. 64 Mbytes Max. 64 Mbytes Dynamic bus sizing for I/O bus width, access to PCMCIA interface from address translation areas
Rev. 1.0, 02/03, page 237 of 1294
Table 10.5 PCMCIA Support Interfaces
IC Memory Card Interface Signal Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 I/O Function Ground I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Ready/busy Operating power supply Programming power supply I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address Signal Name GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE/PGM IREQ VCC VPP1 I/O Card Interface I/O Function Ground I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I O Card enable Address Output enable Address Address Address Address Address Write enable Interrupt request Operating power supply Programming/ peripheral power supply I I I I I I I I I I Address Address Address Address Address Address Address Address Address Address Corresponding Pin for this LSI -- D3 D4 D5 D6 D7 CS5 or CS6 A10 RD A11 A9 A8 A13 A14 WE1 Sensed on port -- --
19 20 21 22 23 24 25 26 27 28
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1
A16 A15 A12 A7 A6 A5 A4 A3 A2 A1
Rev. 1.0, 02/03, page 238 of 1294
IC Memory Card Interface Signal Pin Name 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A0 D0 D1 D2 WP*
1
I/O Card Interface Signal Name A0 D0 D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 O I/O Function I Address Corresponding Pin for this LSI A0 D0 D1 D2 IOIS16 -- -- Sensed on port D11 D12 D13 D14 D15 CE2A or CE2B Output from port ICIORD ICIOWR A17 A18 A19 A20 A21 -- --
I/O Function I Address
I/O Data I/O Data I/O Data O Write protect Ground Ground O Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I Card enable Refresh request Reserved Reserved I I I I I Address Address Address Address Address Power supply Programming power supply I I I I Address Address Address Address
I/O Data I/O Data I/O Data O 16-bit I/O port Ground Ground Card detection I/O Data I/O Data I/O Data I/O Data I/O Data I I I I I I I I I Card enable Refresh request I/O read I/O write Address Address Address Address Address Power supply Programming/ peripheral power supply I I I I Address Address Address Address
GND GND CD1 D11 D12 D13 D14 D15 CE2 RFSH RFU RFU A17 A18 A19 A20 A21 VCC VPP2
53 54 55 56
A22 A23 A24 A25
A22 A23 A24 A25
A22 A23 A24 A25
Rev. 1.0, 02/03, page 239 of 1294
IC Memory Card Interface Signal Pin Name 57 58 59 60 61 62 63 64 65 66 67 68 RFU RESET WAIT RFU REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I O I/O Function Reserved Reset Wait request Reserved Attribute memory space select Battery voltage detection Battery voltage detection Signal Name RFU RESET WAIT INPACK REG SPKR
I/O Card Interface I/O Function Reserved I O O I O O Reset Wait request Attribute memory space select Digital speech signal Card status change Corresponding Pin for this LSI -- Output from port RDY* REG Sensed on port Sensed on port D8 D9 D10 Sensed on port --
2
Input acknowledge --
STSCHG D8 D9 D10 CD2 GND
I/O Data I/O Data I/O Data O Card detection Ground
I/O Data I/O Data I/O Data O Card detection Ground
Notes: *1. WP is not supported. *2. Check the polarity.
Rev. 1.0, 02/03, page 240 of 1294
10.5
Register Descriptions
The BSC has the following registers. The synchronous DRAM mode register in synchronous DRAM can be accessed as a register for this LSI. The following registers control memory interfaces, wait-cycles, and refresh cycles, etc. Table 10.6 Register Configuration (1)
Register Name Bus control register 1 Bus control register 2 Bus control register 3 Bus control register 4 Wait control register 1 Wait control register 2 Wait control register 3 Wait control register 4 Memory control register PCMCIA control register Abbrev. BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 WCR4 MCR PCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W P4 Address H'FF80 0000 H'FF80 0004 H'FF80 0050 H'FE0A 00F0 H'FF80 0008 H'FF80 000C H'FF80 0010 H'FE0A 0028 H'FF80 0014 H'FF80 0018 H'FF80 001C H'FF80 0020 H'FF80 0024 H'FF80 0028 H'FF90 xxxx*
1
Area 7 Address Size H'1F80 0000 H'1F80 0004 H'1F80 0050 H'1E0A 00F0 H'1F80 0008 H'1F80 000C H'1F80 0010 H'1E0A 0028 H'1F80 0014 H'1F80 0018 H'1F80 001C H'1F80 0020 H'1F80 0024 H'1F80 0028 H'1F90 xxxx H'1F94 xxxx 32 16 16 32 32 32 32 32 32 16 16 16 16 16 8 8
Sync Clock Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck
Refresh timer control/status register RTCSR Refresh timer counter Refresh timer constant register Refresh count register RTCNT RTCOR RFCR
Synchronous DRAM mode register SDMR2 (for area 2) Synchronous DRAM mode register SDMR3 (for area 3)
H'FF94 xxxx*1
Rev. 1.0, 02/03, page 241 of 1294
Table 10.6 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Abbrev. H-UDI BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 WCR4 MCR PCR Manual Reset by RESET Pin/WDT/ Multiple Exception Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Register Name Bus control register 1 Bus control register 2 Bus control register 3 Bus control register 4 Wait control register 1 Wait control register 2 Wait control register 3 Wait control register 4 Memory control register PCMCIA control register
H'0000 0000 Retained H'3FFC H'0001 Retained Retained
H'0000 0000 Retained H'7777 7777 Retained H'FFFE EFFF Retained H'0777 7777 Retained H'0000 0000 Retained H'0000 0000 Retained H'0000 H'0000 H'0000 H'0000 H'0000 Write only Write only Retained Retained Retained Retained Retained
Refresh timer control/status register RTCSR Refresh timer counter Refresh timer constant register Refresh count register RTCNT RTCOR RFCR
Synchronous DRAM mode register SDMR2 (for area 2) Synchronous DRAM mode register SDMR3 (for area 3)
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. *1. For details, refer to the descriptions of SDMR2 and SDMR3.
Rev. 1.0, 02/03, page 242 of 1294
10.5.1
Bus Control Register 1 (BCR1)
BCR1 is a 32-bit readable/writable register that specifies the function, bus cycle status, etc., of each area. Do not access off-chip memory space other than area 0 until register initialization is complete.
Bit: 31 END IAN 0/1 R 30 0 R 14 HIZ CNT 0 RW 29 A0M PX 0/1 R 28 0 R 27 0 R 26 DPUP 0 R/W 25 0 R 24 OPUP 0 R/W 23 0 R 22 0 R 21 A1 MBC 0 R/W 20 19 A4 BREQ MBC EN 0 0 R/W R/W 18 17 MEM MPX 0 R/W 1 0 R 16 DMA BST 0 R/W 0 A56 PCM 0 R/W
Initial value: R/W: Bit:
0 R
15 HIZ MEM Initial value: 0 R/W: R/W
13 12 11 10 9 8 7 6 5 4 3 2 A0 A0 A0 A5 A5 A5 A6 A6 A6 DRA DRA DRA BST2 BST1 BST0 BST2 BST1 BST0 BST2 BST1 BST0 MTP2 MTP1 MTP0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 31
Bit Name ENDIAN
Initial Value 0/1
R/W R
Description Endian Flag The value of the endian setting off-chip pin (MD5) is sampled at a power-on reset by the RESET pin. This bit determines the endian mode of all spaces. 0: Indicates that pin MD5 is low at a power-on reset and big-endian mode is specified for this LSI. 1: Indicates that pin MD5 is high at a power-on reset and little-endian mode is specified for this LSI.
30
0
R
Reserved This bit is always read as 0. The write value should always be 0.
29
A0MPX
0/1
R
Area 0 Memory Type The value of the area 0 memory type setting off-chip pin (MD6) is sampled at a power-on reset by the RESET pin. This bit determines the memory type of area 0. 0: Indicates that pin MD6 is high and area 0 is specified as SRAM interface 1: Indicates that pin MD6 is low, and area 0 is specified as MPX interface
28, 27
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 243 of 1294
Bit 26
Bit Name DPUP
Initial Value 0
R/W R/W
Description Data Pin Pull-Up Resistor Control Specifies the pull-up resistor status of the data pins (D31 to D0). It is initialized by a power-on reset. The pins are not pulled up when access is performed or when the bus is released, even if the pull-up resistor is on. 0: Cycle is provided for turning on the pull-up resistor for data pins (D31 to D0) before and after memory access.* 1: Pull-up resistor is off for data pins (D31 to D0). Note: *It is recommended that a pull-up resistor be externally attached for the data pins if it is required.
25
0
R
Reserved This bit is always read as 0. The write value should always be 0.
24
OPUP
0
R/W
Control Output Pin Pull-Up Resistor Control Specifies the pull-up resistor status (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, CE2A, CE2B) when the control output pins are high-impedance. This bit is initialized by a power-on reset. 0: Pull-up resistor is on for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, CE2A, CE2B) 1: Pull-up resistor is off for control output pins (A[25:0], BS, CSn, RD, WEn, RD/WR, RAS, CE2A, CE2B)
23, 22
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
21
A1MBC
0
R/W
Area 1 SRAM Byte Control Mode MPX interface has priority when MPX interface is set. This bit is initialized by a power-on reset. 0: Area 1 SRAM is set to normal mode 1: Area 1 SRAM is set to byte control mode
20
A4MBC
0
R/W
Area 4 SRAM Byte Control Mode MPX interface has priority when MPX interface is set. This bit is initialized by a power-on reset. 0: Area 4 SRAM is set to normal mode 1: Area 4 SRAM is set to byte control mode
Rev. 1.0, 02/03, page 244 of 1294
Bit 19
Bit Name
Initial Value
R/W R/W
Description BREQ Enable Indicates whether off-chip requests can be accepted. BREQEN is initialized to the off-chip request acceptance disabled state by a power-on reset. 0: Off-chip requests are not accepted 1: Off-chip requests are accepted
BREQEN 0
18
0
R
Reserved This bit is always read as 0. The write value should always be 0. Area 1 to 6 MPX Bus Setting Sets the MPX interface when areas 1 to 6 are specified as SRAM interface (or burst ROM interface). This bit is initialized by a power-on reset. 0: SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are specified as SRAM interface (or burst ROM interface) 1: MPX interface is selected when areas 1 to 6 are specified as SRAM interface (or burst ROM interface)
17
MEMMPX 0
R/W
16
DMABST 0
R/W
DMAC Burst Mode Transfer Priority Setting Specifies the priority of burst mode transfers by the DMAC. When OFF, the priority is as follows: bus released, refresh, DMAC, CPU. When ON, bus release and refresh operations are not performed until the end of the DMAC burst mode transfer. This bit is initialized at a power-on reset. 0: DMAC burst mode transfer priority setting OFF 1: DMAC burst mode transfer priority setting ON
15
HIZMEM
0
R/W
High Impedance (High-Z) Control Specifies the state of address and other signals (A[25:0], BS, CSn, RD/WR, CE2A, CE2B) in software standby mode and the bus-released state. 0: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals made to the high-impedance state in software standby mode and the bus-released state 1: The A[25:0], BS, CSn, RD/WR, CE2A, and CE2B signals driven in software standby mode and made to the high-impedance state in the bus-released state
Rev. 1.0, 02/03, page 245 of 1294
Bit 14
Bit Name HIZCNT
Initial Value 0
R/W R/W
Description High Impedance (High-Z) Control Specifies the state of the RAS and CAS signals in software standby mode and the bus-released state. 0: The RAS, WEn /DQMn, and RD/CASS/FRAME signals made to the high-impedance in software standby mode and the bus-released state 1: The RAS, WEn /DQMn, and RD/CASS/FRAME signals driven in software standby mode and the bus-released state
13 12 11
A0BST2 A0BST1 A0BST0
0 0 0
R/W R/W R/W
Area 0 Burst ROM Control These bits specify whether burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the number of accesses in a burst. When area 0 is used as an MPX interface area, the settings of these bits are ignored. 000: Area 0 is accessed as SRAM interface. 001: Area 0 is accessed as burst ROM interface (4 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 010: Area 0 is accessed as burst ROM interface (8 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 011: Area 0 is accessed as burst ROM interface (16 consecutive accesses). Can only be used with 8- or 16-bit bus width. The setting of 32-bit bus width is prohibited. 100: Area 0 is accessed as burst ROM interface (32 consecutive accesses). Can only be used with 8-bit bus width 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 1.0, 02/03, page 246 of 1294
Bit 10 9 8
Bit Name A5BST2 A5BST1 A5BST0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Area 5 Burst ROM Control These bits specify whether burst ROM interface is used in area 5. When burst ROM interface is used, they also specify the number of accesses in a burst. When area 5 is an MPX interface area, the settings of these bits are ignored. When area 5 is used as a PCMCIA area, these bits should be cleared to 0. 000: Area 5 is accessed as SRAM interface. 001: Area 5 is accessed as burst ROM interface (4 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 010: Area 5 is accessed as burst ROM interface (8 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 011: Area 5 is accessed as burst ROM interface (16 consecutive accesses). Can only be used with 8- or 16-bit bus width. The setting of 32-bit bus width is prohibited. 100: Area 5 is accessed as burst ROM interface (32 consecutive accesses). Can only be used with 8-bit bus width 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 1.0, 02/03, page 247 of 1294
Bit 7 6 5
Bit Name A6BST2 A6BST1 A6BST0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Area 6 Burst ROM Control These bits specify whether burst ROM interface is used in area 6. When burst ROM interface is used, they also specify the number of accesses in a burst. When area 6 is an MPX interface area, the settings of these bits are ignored. When area 6 is used as a PCMCIA area, these bits should be cleared to 0. 000: Area 6 is accessed as SRAM interface. 001: Area 6 is accessed as burst ROM interface (4 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 010: Area 6 is accessed as burst ROM interface (8 consecutive accesses). Can be used with 8-, 16-, or 32-bit bus width 011: Area 6 is accessed as burst ROM interface (16 consecutive accesses). Can only be used with 8or 16-bit bus width. The setting of 32-bit bus width is prohibited. 100: Area 6 is accessed as burst ROM interface (32 consecutive accesses). Can only be used with 8bit bus width 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 1.0, 02/03, page 248 of 1294
Bit 4 3 2
Bit Name
Initial Value
R/W R/W R/W R/W
Description Areas 2 and 3 Memory Type These bits specify the type of memory connected to areas 2 and 3. Memory types such as ROM, SRAM, and flash ROM can be connected as an SRAM interface. Synchronous DRAM can also be connected. 000: Areas 2 and 3 are accessed as an SRAM interface or MPX interface* 001: Setting prohibited 010: Area 2 is accessed as an SRAM interface or MPX interface* and area 3 as a synchronous DRAM interface 011: Areas 2 and 3 are accessed as a synchronous DRAM interface 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited Note: * The MEMMPX bit setting selects the SRAM interface or MPX interface.
DRAMTP2 0 DRAMTP1 0 DRAMTP0 0
1
0
R
Reserved This bit is always read as 0. The write value should always be 0. Area 5 and 6 Bus Type Specifies whether areas 5 and 6 are accessed as PCMCIA interface. The setting of this bit has priority over the MEMMPX bit. When this bit is 1, the MD3 pin is designated for output as the CE2A pin, and the MD4 pin is designated for output as the CE2B pin. 0: Areas 5 and 6 are accessed as SRAM interface 1: Areas 5 and 6 are accessed as PCMCIA interface
0
A56PCM 0
R/W
10.5.2
Bus Control Register 2 (BCR2)
BCR2 is a 16-bit readable/writable register that specifies the bus width for each area and whether the GPIO interrupt is used. Do not access off-chip memory space other than area 0 until register initialization is complete.
Rev. 1.0, 02/03, page 249 of 1294
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 0 -
A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 Initial value: R/W: 0/1 R 0/1 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
0 STBI RLEN 0 R/W
Bit 15 14
Bit Name A0SZ1 A0SZ0
Initial Value 0/1 0/1
R/W R R
Description Area 0 Bus Width The off-chip pins (MD4 and MD3) that specify the bus width are sampled at a power-on reset by the RESET signal. 00: Setting prohibited 01: 8 bits 10: 16 bits 11: 32 bits
2n + 1 2n
AnSZ1 AnSZ0
All 1 All 1
R/W R/W
Bus Width Setting Specifies the bus width of area n. 00: Setting prohibited 01: Bus width is 8 bits 10: Bus width is 16 bits 11: Bus width is 32 bits
1
0
Reserved This bit is always read as 0. The write value should always be 0. GPIO Interrupt Enable 0: GPIO interrupt is not used 1: GPIO interrupt is used
0
STBIRLEN 0
R/W
Note: n = 1 to 6
10.5.3
Bus Control Register 3 (BCR3)
BCR3 is a 16-bit readable/writable register that specifies the selection of either the MPX interface or the SRAM interface and specifies the burst length when the synchronous DRAM interface is used. Do not access off-chip memory space other than area 0 until register initialization is complete.
15 14 MEM A1 MODE MPX Initial value: 0 0 R/W: R/W R/W Bit: 13 A4 MPX 0 R/W 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 SDBL 1 R/W
Rev. 1.0, 02/03, page 250 of 1294
Bit 15
Bit Name MEM MODE
Initial Value 0
R/W R/W
Description A1MPX/A4MPX Enable Determines whether to use A1MPX and A4MPX or to use MEMMPX for selecting the MPX interface or the SRAM interface. 0: MPX or SRAM interface is selected by MEMMPX 1: MPX or SRAM interface is selected by A1MPX and A4MPX
14
A1MPX
0
R/W
MPX-Interface Setting for Area 1 Specifies the type of memory connected to area 1. This setting is validated by the MEMMODE bit. 0: SRAM/byte control SRAM interface is selected for area 1 1: MPX interface is selected for area 1
13
A4MPX
0
R/W
MPX-Interface Setting for Area 4 Specifies the type of memory connected to area 4. This setting is validated by the MEMMODE bit. 0: SRAM/byte control SRAM interface is selected for area 4 1: MPX interface is selected for area 4
12 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Burst Length Sets the burst length when the synchronous DRAM interface is used. The burst-length setting is only valid when the bus width is 32 bits. 0: Burst length is 8 1: Burst length is 4
0
SDBL
1
R/W
Rev. 1.0, 02/03, page 251 of 1294
10.5.4
Bus Control Register 4 (BCR4)
BCR4 is a 32-bit readable/writable register that enables asynchronous input for pins corresponding to individual bits. When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than when synchronous input is set (ASYNCn = 0). With the synchronous input setting, ensure that setup and hold times are observed. The timings shown in this section and section 33, Electrical Characteristics, are all for the case where synchronous input is set (ASYNCn = 0).
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
ASYN ASYN ASYN ASYN ASYN ASYN ASYN C6 C5 C4 C3 C2 C1 C0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Asynchronous Input 6 0: The DREQ3 pin can be used for synchronous input with the CKIO signal. 1: The DREQ3 pin can be used for asynchronous input with the CKIO signal.
31 to 7
6
ASYNC6
0
R/W
5
ASYNC5
0
R/W
Asynchronous Input 5 0: The DREQ2 pin can be used for synchronous input with the CKIO signal. 1: The DREQ2 pin can be used for asynchronous input with the CKIO signal.
4
ASYNC4
0
R/W
Asynchronous Input 4 0: The IOIS16 pin can be used for synchronous input with the CKIO signal. 1: The IOIS16 pin can be used for asynchronous input with the CKIO signal.
Rev. 1.0, 02/03, page 252 of 1294
Bit 3
Bit Name ASYNC3
Initial Value 0
R/W R/W
Description Asynchronous Input 3 0: The DREQ1 pin can be used for synchronous input with the CKIO signal. 1: The DREQ1 pin can be used for asynchronous input with the CKIO signal.
2
ASYNC2
0
R/W
Asynchronous Input 2 0: The DREQ0 pin can be used for synchronous input with the CKIO signal. 1: The DREQ0 pin can be used for asynchronous input with the CKIO signal.
1
ASYNC1
0
R/W
Asynchronous Input 1 0: The BREQ pin can be used for synchronous input with the CKIO signal. 1: The BREQ pin can be used for asynchronous input with the CKIO signal.
0
ASYNC0
0
R/W
Asynchronous Input 0 0: The RDY pin can be used for synchronous input with the CKIO signal. 1: The RDY pin can be used for asynchronous input with the CKIO signal.
T1 CKIO RDY (BCR4.ASYNC0 = 0)
Tw
Tw
Twe
T2
RDY (BCR4.ASYNC0 = 1)
Figure 10.4 Example of RDY Sampling Timing
Rev. 1.0, 02/03, page 253 of 1294
10.5.5
Wait Control Register 1 (WCR1)
WCR1 is a 32-bit readable/writable register that specifies the number of idle state insertion cycles for each area. With some types of memory, data bus drive does not go off immediately after the off-chip read signal goes off. As a result, there is a possibility of a data bus collision when consecutive memory accesses are performed on memory in different areas, or when a memory write is performed immediately after a read. In this LSI, idle cycles corresponding to the number of cycles set in WCR1 are automatically inserted if there is a possibility of this kind of data bus collision.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 DMA IW2 1 R/W 14 A3 IW2 1 R/W 29 28 DMA DMA IW1 IW0 1 1 R/W R/W 13 A3 IW1 1 R/W 12 A3 IW0 1 R/W 27 0 R 11 0 R 26 A6 IW2 1 R/W 10 A2 IW2 1 R/W 25 A6 IW1 1 R/W 9 A2 IW1 1 R/W 24 A6 IW0 1 R/W 8 A2 IW0 1 R/W 23 0 R 7 0 R 22 A5 IW2 1 R/W 6 A1 IW2 1 R/W 21 A5 IW1 1 R/W 5 A1 IW1 1 R/W 20 A5 IW0 1 R/W 4 A1 IW0 1 R/W 19 0 R 3 0 R 18 A4 IW2 1 R/W 2 A0 IW2 1 R/W 17 A4 IW1 1 R/W 1 A0 IW1 1 R/W 16 A4 IW0 1 R/W 0 A0 IW0 1 R/W
Bit 31
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
30 29 28
DMAIW2 DMAIW1 DMAIW0
1 1 1
R/W R/W R/W
DMAIW-DACK Device Inter-Cycle Idle Setting These bits specify the number of idle cycles between bus cycles to be inserted when switching from a device with DACK to another space, or from a read access to a write access on the same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual address transfer, inter-area idle cycles specified by the AnIW2 to AnIW0 bits are inserted. Reserved These bits are always read as 0. The write value should always be 0.
4n + 3
--
All 0
R
Rev. 1.0, 02/03, page 254 of 1294
Bit 4n + 2 4n + 1 4n
Bit Name AnlW2 AnlW1 AnlW0
Initial Value All 1 All 1 All 1
R/W R/W R/W R/W
Description Area n Inter-Cycle Idle Setting These bits specify the number of idle cycles between bus cycles to be inserted when switching from off-chip memory space area n to another space, or from a read access to a write access in the same space. For the type of idle cycles to be inserted, see table 10.7. 000: 001: 010: 011: 100: 101: 110: 111: Idle cycles to be inserted 0 1 2 3 6 9 12 15
Note: n = 0 to 6
Rev. 1.0, 02/03, page 255 of 1294
Table 10.7 Idle Insertion between Accesses
Following Cycle Same Area Read Preceding Cycle Read Write DMA read (memory device) DMA write (device memory) D D M M CPU DMA Write CPU M DMA M Different Area Read CPU DMA M M M M M M Write CPU DMA M M M M M M Same Area Different Area
MPX MPX Address Address Output Output M (1) *
2
M (1) M M (1)
D
D*
1
D
D
D
D
D (1)
DMA in the table indicates DMA single-address transfer. DMA dual-address transfer is in accordance with the CPU. M, D: Idle wait always inserted by WCR1 (M(1): One cycle inserted in MPX access even if WCR1 is cleared to 0) M: Idle cycles according to setting of AnIW2 to AnIW0 (areas 0 to 6) D: Idle cycles according to setting of DMAIW2 to DMAIW0 Notes: When synchronous DRAM is used in RAS down mode, bits DMAIW2 to DAMIW0 and bits A3IW2 to A3IW0 should be both 000. *1. Inserted when device is switched *2. On the MPX interface, a WCR1 idle wait may be inserted before an access (either read or write) to the same area after a write access. An example of idle wait insertion in accesses to the same area is shown below. (a) Synchronous DRAM set to RAS down mode (b) Synchronous DRAM accessed by on-chip DMAC Under above conditions (a) and (b), an idle wait may be inserted in a same-area access following an MPX interface write access, depending on the synchronous DRAM pipeline access situation. An idle wait is not inserted when the WCR1 setting is 0. The setting for the number of idle state cycles inserted after a power-on reset is the default value of 15 (the maximum value), so ensure that the optimum value is set.
Rev. 1.0, 02/03, page 256 of 1294
10.5.6
Wait Control Register 2 (WCR2)
WCR2 is a 32-bit readable/writable register that specifies the number of wait cycles to be inserted for each area. It also specifies the data access pitch when performing burst ROM memory access.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 R 0
A6W2 A6W1 A6W0 A6B2 A6B1 A6B0 A5W2 A5W1 A5W0 A5B2 A5B1 A5B0 A4W2 A4W1 A4W0 1 R/W 15 1 R/W 14 1 R/W 13 1 R/W 12 0 R 1 R/W 11 1 R/W 10 1 R/W 9 1 R/W 8 1 R/W 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1
A3W2 A3W1 A3W0 1 R/W 1 R/W 1 R/W
A2W2 A2W1 A2W0 A1W2 A1W1 A1W0 A0W2 A0W1 A0W0 A0B2 A0B1 A0B0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Bit 31 30 29
Bit Name A6W2 A6W1 A6W0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 6 Wait Control These bits specify the number of wait cycles to be inserted for area 6. For the case where an MPX interface setting is made, see table 10.7. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Rev. 1.0, 02/03, page 257 of 1294
Bit 28 27 26
Bit Name A6B2 A6B1 A6B0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 6 Burst Pitch These bits specify the number of wait cycles to be inserted for the second and following data accesses in burst transfer when area 6 is specified as burst ROM area. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 4 5 6 7 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
25 24 23
A5W2 A5W1 A5W0
1 1 1
R/W R/W R/W
Area 5 Wait Control These bits specify the number of wait cycles to be inserted for area 5. For the case where an MPX interface setting is made, see table 10.7. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Rev. 1.0, 02/03, page 258 of 1294
Bit 22 21 20
Bit Name A5B2 A5B1 A5B0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 5 Burst Pitch These bits specify the number of wait cycles to be inserted for the second and following data accesses in burst transfer when area 5 is specified as burst ROM area. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 4 5 6 7 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
19 18 17
A4W2 A4W1 A4W0
1 1 1
R/W R/W R/W
Area 4 Wait Control These bits specify the number of wait cycles to be inserted for area 4. For the case where an MPX interface setting is made, see table 10.7. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
16
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 259 of 1294
Bit 15 14 13
Bit Name A3W2 A3W1 A3W0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 3 Wait Control These bits specify the number of wait cycles to be inserted for area 3. An external wait input is available for SRAM and MPX interfaces and is not available for synchronous DRAM interface. For the case where an MPX interface setting is made, see table 10.7. * When SRAM interface is in use: Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: * 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
1
When synchronous DRAM interface is in use* : Synchronous DRAM CAS latency cycles Setting prohibited 1* 2 3 4* 5*
2 2 2
000: 001: 010: 011: 100: 101: 110: 111: 12 0 R
Setting prohibited Setting prohibited
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 260 of 1294
Bit 11 10 9
Bit Name A2W2 A2W1 A2W0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 2 Wait Control These bits specify the number of wait cycles to be inserted for area 2. An external wait input is available for SRAM and MPX interfaces and is not available for synchronous DRAM interface. * When SRAM interface is in use: Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: * 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
1
When synchronous DRAM interface is in use* : Synchronous DRAM CAS latency cycles Setting prohibited 1* 2* 3* 4* 5*
2 2 2 2 2
000: 001: 010: 011: 100: 101: 110: 111:
Setting prohibited Setting prohibited
Rev. 1.0, 02/03, page 261 of 1294
Bit 8 7 6
Bit Name A1W2 A1W1 A1W0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 1 Wait Control These bits specify the number of wait cycles to be inserted for area 1. For the case where an MPX interface setting is made, see table 10.8. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
5 4 3
A0W2 A0W1 A0W0
1 1 1
R/W R/W R/W
Area 0 Wait Control These bits specify the number of wait cycles to be inserted for area 0. For the case where an MPX interface setting is made, see table 10.8. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Rev. 1.0, 02/03, page 262 of 1294
Bit 2 1 0
Bit Name A0B2 A0B1 A0B0
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 0 Burst Pitch These bits specify the number of wait cycles to be inserted for the second and following data accesses in burst transfer when area 0 is specified as burst ROM area. Inserted wait cycles 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 4 5 6 7 RDY pin Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Notes: *1. External wait input is always ignored *2. Inhibited in RAS down mode
Table 10.8 MPX Interface Setting
Description Inserted Wait Cycles 1st Data AnW2 0 0 0 0 1 1 1 1 AnW1 0 0 1 1 0 0 1 1 AnW0 0 1 0 1 0 1 0 1 Read 1 1 2 3 1 1 2 3 Write 0 1 2 3 0 1 2 3 2nd Data and After 0 0 0 0 1 1 1 1 RDY Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Note: n = 0 to 6
Rev. 1.0, 02/03, page 263 of 1294
10.5.7
Wait Control Register 3 (WCR3)
WCR3 is a 32-bit readable/writable register that specifies the cycles to be inserted for each area during the address setup time before the read/write strobe is asserted and during the data-hold time after the write strobe is negated.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 29 0 R 13 28 0 R 12 27 0 R 11 0 R 26 25 24 23 0 R 22 21 20 19 18 17 16 A4 A4S0 A4H1 A4H0 RDH 0 1 1 1 R/W R/W R/W R/W 3 0 R 2 1 0
A6S0 A6H1 A6H0 1 R/W 1 R/W 1 R/W
A5S0 A5H1 A5H0 1 R/W 6 1 R/W 5 1 R/W 4
A3S0 A3H1 A3H0 1 R/W 1 R/W 1 R/W
10 9 8 7 A1 A2S0 A2H1 A2H0 RDH 1 1 1 1 R/W R/W R/W R/W
A1S0 A1H1 A1H0 1 R/W 1 R/W 1 R/W
A0S0 A0H1 A0H0 1 R/W 1 R/W 1 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 27, 23, 15, 11, 3 4n + 2 AnS0
All 1
R/W
Area n Write Strobe Setup Time Specifies the number of cycles to be inserted during the address setup time before the read/write strobe is asserted. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface: Cycles to be inserted during the setup time 0: 0 1: 1
Rev. 1.0, 02/03, page 264 of 1294
Bit 4n + 1 4n
Bit Name AnH1 AnH0
Initial Value All 1 All 1
R/W R/W R/W
Description Area n Data Hold Time For writing, specifies the number of cycles to be inserted during the data hold time after the write strobe is negated. For reading, specifies the number of cycles to be inserted during the data hold time after the data sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM interface: Cycles to be inserted during the data hold time 00: 01: 10: 11: 0 1 2 3
4m + 3 AmRDH
All 0
R/W
Read-Strobe Negate Timing For reading, these bits specify the timing for the negation of read strobe. These bits should be cleared to 0 when byte control SRAM interface is in use. See figure 10.11.
Note: n = 0 to 6; m = 1 and 4
10.5.8
Wait Control Register 4 (WCR4)
WCR4 is a 32-bit readable/writable register that specifies the negation period for the CS1 signal. Specifying bits CSH1 and CSH0 can insert the negation cycles from 0 to 3. The WCR4 setting is valid when the setting of the data hold time (A1H[1:0]) in WCR3 matches the setting of WCR4. When the settings of WCR3 and WCR4 do not match, correct operation is not guaranteed.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 16 0 R 0
CSH1 CSH0 0 R/W 0 R/W
Rev. 1.0, 02/03, page 265 of 1294
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
31 to 2
1 0
CSH1 CSH0
0 0
R/W R/W
CS Hold Cycle Setting Specifies the number of wait cycles to be inserted during data hold time. Wait cycles to be inserted 00: 01: 10: 11: 0 1 2 3
10.5.9
Memory Control Register (MCR)
MCR is a 32-bit readable/writable register that specifies RAS and CASS timing, burst control, address multiplexing, and refresh control for synchronous DRAM (areas 2 and 3). Write bits 31 to 3 when making the initial settings after a power-on reset and do not modify the settings from then onward. When writing to bits RFSH and RMODE, write the same values without changing other bits. When using synchronous DRAM, do not access areas 2 and 3 before register initialization is complete.
Bit: 31 RASD Initial value: R/W: Bit: 0 R/W 30 MR SET 0 R/W 29 28 27 26 0 R 25 0 R 9 0 R 24 0 R 8 SZ1 0 R/W 23 0 R 7 SZ0 0 R/W 22 0 R 21 20 19 18 0 R 17 16
TRC2 TRC1 TRC0 0 R/W 0 R/W 0 R/W
TPC2 TPC1 TPC0 0 R/W 0 R/W 0 R/W
RCD1 RCD0 0 R/W 0 R/W 0 0 R
15 14 13 12 11 10 TRWL TRWL TRWL TRAS TRAS TRAS 2 1 0 2 1 0 Initial value: 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W
6 5 4 3 2 1 RM AMX AMX2 AMX1 AMX0 RFSH ODE EXT 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 266 of 1294
Bit 31
Bit Name RASD
Initial Value 0
R/W R/W
Description RAS Down Sets RAS down mode. Do not set RAS down mode when specifying areas 2 and 3 as synchronous DRAM interface. 0: Normal mode 1: RAS down mode Note: When using synchronous DRAM in RAS down mode, set the DMAIW2 to DMAIW0 bits to 000 and A3IW2 to A3IW0 bits to 000.
30
MRSET
0
R/W
Mode Register Set Set this bit to 1 to make the mode register setting for synchronous DRAM. See the description of power-on sequence in section 10.6.4, (10) Synchronous DRAM Interface. 0: All-bank precharge 1: Mode register setting
29 28 27
TRC2 TRC1 TRC0
0 0 0
R/W R/W R/W
RAS Precharge Time after Refresh (Both auto- and self-refresh are available for synchronous DRAM) RAS precharge time immediately after refresh 000: 001: 010: 011: 100: 101: 110: 111: 0 3 6 9 12 15 18 21
26 to 22
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 267 of 1294
Bit 21 20 19
Bit Name TPC2 TPC1 TPC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description RAS Precharge Period When synchronous DRAM interface is in use, these bits specify the minimum number of cycles until the next bank active command is issued after precharging. RAS Precharge Time (SDRAM) 000: 001: 010: 011: 100: 101: 110: 111: 1* 2 3 4* 5* 6* 7* 8*
1 1 1 1 1 1
18
0
R
Reserved This bit is always read as 0. The write value should always be 0.
17 16
RCD1 RCD0
0 0
R/W R/W
RAS-CAS Delay When using the synchronous DRAM interface, specify ACTIVE to READ or WRITE delay in these bits. 00: Setting prohibited 01: 2 cycles 10: 3 cycles 11: 4 cycles*
1
Rev. 1.0, 02/03, page 268 of 1294
Bit 15 14 13
Bit Name TRWL2 TRWL1 TRWL0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Write Precharge Delay Specify the synchronous DRAM write precharge delay in these bits. In auto-precharge mode, specify the time after a write cycle before the next bank active command is issued. After a write cycle, the next active command is not issued for a period of TPC + TRWL. In RAS down mode, specify the time after a write cycle before the next precharge command is issued. After a write cycle, the next precharge command is not issued for a period of TRWL. This setting is valid only when synchronous DRAM interface is in use. For details on these bit settings and the period in which no command is issued, refer to section 33.3.3, Bus Timing. Write Precharge ACT Delay Time 000: 001: 010: 011: 100: 101: 110: 111: 1 2 3* 4* 5*
1 1 1
Setting prohibited Setting prohibited Setting prohibited
12 11 10
TRAS2 TRAS1 TRAS0
0 0 0
R/W R/W R/W
Refresh Period When the synchronous DRAM interface is in use, the 2 bank active command is not issued for a period of TRC* + TRAS after an auto-refresh command is issued. Command Issuance Gap after Synchronous DRAM Refresh 000: 001: 010: 011: 100: 101: 110: 111: 4 + TRC 5 + TRC 6 + TRC 7 + TRC 8 + TRC 9 + TRC 10 + TRC 11 + TRC
Rev. 1.0, 02/03, page 269 of 1294
Bit 9
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
8 7
SZ1 SZ0
0 0
R/W R/W
Memory Data Size These bits specify the bus width of synchronous DRAM. This setting has priority over the BCR2 register setting. Synchronous DRAM 00: 01: 10: 11: Setting prohibited Setting prohibited Setting prohibited 32 bits
6 5 4 3
AMXEXT AMX2 AMX1 AMX0
0 0 0 0
R/W R/W R/W R/W
Address Multiplexing These bits specify address multiplexing for synchronous DRAM. For details, refer to appendix D, Address Multiplexing for Synchronous DRAM. Synchronous DRAM structure example 0000: 1000: 0001: 1001: 0010: 0011: 0100: 0101: 0110: 1110: 0111 (512k x 16 bits x 2) x 2 (512k x 16 bits x 2) x 2 (1M x 8 bits x 2) x 4 (1M x 8 bits x 2) x 4 (1M x 16 bits x 4) x 2 (2M x 8 bits x 4) x 4 (512k x 32 bits x 4) x 1 (1M x 32 bits x 2) x 1 (4M x 4 bits x 4) x 8 (4M x 16 bits x 4) x 2 (256k x 32 bits x 2) x 1 Bank a[21]* a[20]* a[22]* a[21]*
3 3 3 3 3 3 3
a[23:22]* a[24:23]* a[22]*
3
a[22:21]* a[25:24]* a[25:24]* a[20]*
3
3 3
Other settings are prohibited. 2 RFSH 0 R/W Refresh Control Specifies refresh control. Selects whether refreshing is performed for synchronous DRAM. When the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. 0: Refresh is not performed 1: Refresh is performed
Rev. 1.0, 02/03, page 270 of 1294
Bit 1
Bit Name RMODE
Initial Value 0
R/W R/W
Description Refresh Mode Specifies whether normal refreshing or self-refreshing is performed when the RFSH bit is set to 1. When RFSH bit = 1 and RMODE = 0, auto-refreshing is performed for synchronous DRAM at the interval specified in refreshrelated registers RTCNT, RTCOR, and RTCSR. If a refresh request is issued during an off-chip bus cycle, the refresh cycle is executed when the bus cycle ends. When RFSH = 1 and RMODE =1, if a refresh request is issued during an off-chip bus cycle, the synchronous DRAM waits until the bus cycle ends before entering the self-refresh state. All refresh requests for memory in the self-refresh state are ignored. 0: Auto refresh (when RFSH = 1) 1: Self refresh (when RFSH = 1)
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Note:
*1. Inhibited in RAS down mode *2. Bits 29 to 27. RAS precharge period after refresh *3. a[x]: Off-chip address; not address pin
10.5.10 PCMCIA Control Register (PCR) PCR is a 16-bit readable/writable register that specifies the OE and WE signal assertion/negation timing for areas 5 and 6 specified as the PCMCIA interface. The OE and WE signal assertion width is specified by the wait control bits in WCR2.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A5 A5 A6 A6 A5 A5 A5 A6 A6 A6 A5 A5 A5 A6 A6 A6 PCW1 PCW0 PCW1 PCW0 TED2 TED1 TED0 TED2 TED1 TED0 TEH2 TEH1 TEH0 TEH2 TEH1 TEH0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Rev. 1.0, 02/03, page 271 of 1294
Bit 15 14
Bit Name
Initial Value
R/W R/W R/W
Description PCMCIA Wait A5 In a low-speed PCMCIA wait cycle, these bits specify the number of wait cycles to be added to the number of wait cycles specified by WCR2. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Wait cycles to be inserted 00: 01: 10: 11: 0 15 30 50
A5PCW1 0 A5PCW0 0
13 12
A6PCW1 0 A6PCW0 0
R/W R/W
PCMCIA Wait A6 In a low-speed PCMCIA wait cycle, these bits specify the number of wait cycles to be added to the number of wait cycles specified by WCR2. The setting of these bits is selected when the PCMCIA interface access TC bit is 1. Wait cycles to be inserted 00: 01: 10: 11: 0 15 30 50
11 10 9
A5TED2 A5TED1 A5TED0
0 0 0
R/W R/W R/W
Address-OE/WE Assertion Delay A5 These bits set the delay time from address output to OE/WE assertion in the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Wait cycles to be inserted 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15
Rev. 1.0, 02/03, page 272 of 1294
Bit 8 7 6
Bit Name A6TED2 A6TED1 A6TED0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Address-OE/WE Assertion Delay A6 These bits set the delay time from address output to OE/WE assertion in the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 1. Wait cycles to be inserted 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15
5 4 3
A5TEH2 A5TEH1 A5TEH0
0 0 0
R/W R/W R/W
OE/WE Negation-Address Delay A5 These bits set the address hold delay time after OE/WE negation in the connected PCMCIA interface. PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 0. Wait cycles to be inserted 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15
Rev. 1.0, 02/03, page 273 of 1294
Bit 2 1 0
Bit Name A6TEH2 A6TEH1 A6TEH0
Initial Value 0 0 0
R/W R/W R/W R/W
Description OE/WE Negation-Address Delay A6 These bits set the address hold delay time after OE/WE negation in the connected PCMCIA interface. The setting of these bits is selected when the PCMCIA interface access TC bit is 1. Wait cycles to be Inserted 000: 001: 010: 011: 100: 101: 110: 111: 0 1 2 3 6 9 12 15
10.5.11 Synchronous DRAM Mode Register (SDMR) SDMR is a 16-bit write-only virtual register that is written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3 synchronous DRAM. Settings for the SDMR register must be made before accessing synchronous DRAM.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: R/W:
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register, if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the synchronous DRAM mode register by performing a write to address X + Y. When the synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to A2 of this LSI, and A1 of the synchronous DRAM is connected to A3 of this LSI, the value actually written to the synchronous DRAM is the value of "X" shifted 2 bits to the right. For example, to write H'0230 to SDMR in area 2, arbitrary data is written to address H'FF90 0000 (address "Y") + H'08C0 (value "X") (= H'FF90 08C0). As a result, H'0230 is written to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
Rev. 1.0, 02/03, page 274 of 1294
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address H'FF94 0000 (address "Y") + H'08C0 (value "X") (= H'FF94 08C0). As a result, H'0230 is written to the SDMR register. The range of value "X" is H'0000 to H'0FFC. The lower 16 bits of the address are set in the synchronous DRAM mode register. The burst length is 4 and 8. Setting to SDMR writes into the following addresses in bytes.
Bus Width 32 Burst Length 4 CAS Latency 1 2 3 32 8 1 2 3 Area 2 H'FF90 0048 H'FF90 0088 H'FF90 00C8 H'FF90 004C H'FF90 008C H'FF90 00CC Area 3 H'FF94 0048 H'FF94 0088 H'FF94 00C8 H'FF94 004C H'FF94 008C H'FF94 00CC
For a 32-bit bus:
17 16 15 14 13 12 11 Address 0 0 0 0 0 0 0 10 0 9 0 8 7 6 5 4 BL2 3 BL1 2 BL0 1 0
LMODE2 LMODE1 LMODE0 WT
- 10 bits set when bus width is 32 bits LMODE: BL: WT: RAS-CAS latency Burst length Wrap type (0: Sequential) LMODE 000: Setting prohibited 001: 1 010: 2 011: 3 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
BL 000: Setting prohibited 001: Setting prohibited 010: 4 011: 8 100: Setting prohibited 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
Rev. 1.0, 02/03, page 275 of 1294
10.5.12 Refresh Timer Control/Status Register (RTCSR) RTCSR is a 16-bit readable/writable register that specifies the refresh cycle and whether interrupts are to be generated.
Bit: Initial value: R/W: 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 2 OVF 0 R/W 1 0
CMF CMIE CKS2 CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
OVIE LMTS 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W
Description Reserved These bits are always read as 0. For the write values, see section 10.7.3, Accessing Refresh Control Registers.
15 to 8
7
CMF
0
R/W
Compare-Match Flag Status flag that indicates a match between RTCNT and RTCOR values. 0: RTCNT and RTCOR values do not match [Clearing condition] When 0 is written to CMF 1: RTCNT and RTCOR values match [Setting condition] When RTCNT = RTCOR*
6
CMIE
0
R/W
Compare-Match Interrupt Enable Controls whether or not an interrupt request is enabled when the CMF bit is set to 1 in RTCSR. Do not set this bit to 1 when auto-refreshing is used. 0: Interrupt request by CMF disabled 1: Interrupt request by CMF enabled
Rev. 1.0, 02/03, page 276 of 1294
Bit 5 4 3
Bit Name CKS2 CKS1 CKS0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Clock Select Bits These bits select the input clock for RTCNT. The source clock is the off-chip bus clock (CKIO). The RTCNT count clock is obtained by dividing CKIO by the specified factor. 000: Clock input disabled 001: CKIO/4 010: CKIO/16 011: CKIO/64 100: CKIO/256 101: CKIO/1024 110: CKIO/2048 111: CKIO/4096
2
OVF
0
R/W
Refresh Count Overflow Flag Status flag that indicates that the number of refresh cycles in RFCR has exceeded the number specified by the LMTS bit in RTCSR. 0: RFCR has not overflowed the count limit indicated by LMTS [Clearing condition] When 0 is written to OVF 1: RFCR has overflowed the count limit specified by LMTS [Setting condition] When RFCR overflows the count limit specified by LMTS*
1
OVIE
0
R/W
Refresh Count Overflow Interrupt Enable Controls whether or not an interrupt request is enabled when the OVF bit is set to 1 in RTCSR. 0: Interrupt requests by OVF disabled 1: Interrupt requests by OVF enabled
0
LMTS
0
R/W
Refresh Count Overflow Limit Select Specifies the count limit to be compared with the RFCR value. If the RFCR value exceeds the value specified by LMTS, the OVF bit is set. 0: Count limit is 1024 1: Count limit is 512
Note: If 1 is written, the original value is retained.
Rev. 1.0, 02/03, page 277 of 1294
10.5.13 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable counter that is incremented by the input clock (selected by bits CKS2 to CKS0 in RTCSR). When the RTCNT value matches the RTCOR value, the CMF bit is set in RTCSR and the RTCNT value is cleared.
Bit: Initial value: R/W: 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
10.5.14
Refresh Time Constant Register (RTCOR)
RTCOR is a readable/writable register that specifies the upper limit of RTCNT. The RTCOR and RTCNT values (lower 8 bits) are constantly compared, and when they match, the CMF bit is set in RTCSR and the RTCNT value is cleared to 0. If the RFSH bit in MCR has been set to 1 and autorefresh has been selected as the refresh mode, a memory refresh cycle is generated when the CMF bit is set.
Bit: Initial value: R/W: 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
10.5.15 Refresh Count Register (RFCR) RFCR is a 10-bit readable/writable counter that counts the number of refresh cycles by being incremented each time the RTCOR and RTCNT values match. If the RFCR value exceeds the count limit specified by the LMTS bit in RTCSR, the OVF bit in RTCSR is set and the RFCR value is cleared.
Bit: Initial value: R/W: 15 0 14 0 13 0 12 0 11 0 10 0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 8 7 6 5 4 3 2 1 0
Rev. 1.0, 02/03, page 278 of 1294
10.5.16 Accessing Refresh Control Related Registers RTCSR, RTCNT, RTCOR, and RFCR require that a specific code be appended to the data when it is written to prevent data from being mistakenly overwritten by program overruns or other write operations. Perform reads and writes using the following methods: (1) Write to RTCSR, RTCNT, RTCOR, or RFCR When writing to RTCSR, RTCNT, RTCOR, and RFCR, use only word transfer instructions. They cannot be written to with byte transfer instructions. When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the write data in the lower byte. When writing to RFCR, place B'101001 in the top six bits and the write data in the remaining bits, as shown in figure 10.5.
15 RTCSR, RTCNT, RTCOR RFCR 1 15 1
14 13 0 1
12 0 12 0
11 0 11 0
10 1 10 1
9 0 9
8 1 8
7
6
5
4
3
2
1
0
Write data 7 6 5 4 3 2 1 0
14 13 0 1
Write data
Figure 10.5 Write to RTCSR, RTCNT, RTCOR, or RFCR (2) Read from RTCSR, RTCNT, RTCOR, or RFCR RTCSR, RTCNT, RTCOR, or RFCR should be read in 16-bit units. Each reserved bit is always read as 0.
Rev. 1.0, 02/03, page 279 of 1294
10.6
10.6.1
Operation
Endian/Access Size and Data Alignment
This LSI supports both big-endian mode, in which upper byte in a string of byte data is at an address 0, and little-endian mode, in which lower byte in a string of byte data is at an address 0. The mode is specified by the MD5 pin at a power-on reset by the RESET pin. When the MD5 pin is low, big-endian mode is specified, and when the MD5 pin is high, little-endian mode is specified. A data bus width of 8, 16, or 32 bits can be selected for the normal memory interface, 32 bits for the synchronous DRAM interface, and 8 or 16 bits for the PCMCIA interface. Data alignment is carried out according to the data bus width and endian mode of each device. Accordingly, when the data bus width is narrower than the access size, multiple bus cycles are automatically generated to reach the access size. In this case, access is performed by automatically incrementing addresses to the bus width. For example, when a long word access is performed at the area with an 8-bit bus width in the SRAM interface, each address is incremented one by one, and then access is performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed using wraparound on 32-byte boundary data. During these transfers, the bus is not released and refresh operation is not performed. In this LSI, data alignment and data length conversion between different interfaces is performed automatically. Quadword access is used only in transfer by the DMAC. The relationships between the endian mode, device data length, and access unit are shown in tables 10.9 to 10.14.
Rev. 1.0, 02/03, page 280 of 1294
Data Configuration
MSB Byte Data 7 to 0 LSB
MSB Word Data 15 to 8 Data 7 to 0
LSB
MSB Longword Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0
LSB
MSB Quadword Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8
LSB Data 7 to 0
Table 10.9 32-Bit Off-chip Device/Big-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte 4n 4n+1 4n+2 4n+3 Word 4n 4n+2 Longword Quadword 4n 8n 8n+4 1 1 1 1 1 1 1 1 2 Data 7 to 0 -- -- -- Data 15 to 8 -- Data 31 to 24 Data 63 to 56 Data 31 to 24 Data Bus D23 to D16 -- Data 7 to 0 -- -- Data 7 to 0 -- Data 23 to 16 Data 55 to 48 Data 23 to 16 D15 to D8D7 to D0 -- -- Data 7 to 0 -- -- Data 15 to 8 Data 15 to 8 -- -- -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, WE3 DQM3 Asserted Asserted Asserted Asserted Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 WE0, WE0 DQM0
Data Data 47 to 40 39 to 32 Data 15 to 8 Data 7 to 0
Rev. 1.0, 02/03, page 281 of 1294
Table 10.10 16-Bit Off-chip Device/Big-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte 2n 2n+1 Word Longword 2n 4n 4n+2 Quadword 8n 8n+2 8n+4 8n+6 1 1 1 1 2 1 2 3 4 -- -- -- -- -- -- -- -- -- Data Bus D23 to D16 -- -- -- -- -- -- -- -- -- D15 to D8D7 to D0 Data 7 to 0 -- Data 15 to 8 -- Data 7 to 0 Data 7 to 0 WE3, WE3 DQM3 Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE0, WE0 DQM0
Data Data 31 to 24 23 to 16 Data 15 to 8 Data 7 to 0
Data Data 63 to 56 55 to 48 Data Data 47 to 40 39 to 32 Data Data 31 to 24 23 to 16 Data 15 to 8 Data 7 to 0
Rev. 1.0, 02/03, page 282 of 1294
Table 10.11 8-Bit Off-chip Device/Big-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte Word n 2n 2n+1 Longword 4n 4n+1 4n+2 4n+3 Quadword 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data Bus D23 to D16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D15 to D8D7 to D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 WE3, WE3 DQM3 Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 WE0, WE0 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Rev. 1.0, 02/03, page 283 of 1294
Table 10.12 32-Bit Off-Chip Device/Little-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte 4n 4n+1 4n+2 4n+3 Word 4n 4n+2 Longword Quadword 4n 8n 8n+4 1 1 1 1 1 1 1 1 2 -- -- -- Data 7 to 0 -- Data 15 to 8 Data 31 to 24 Data 31 to 24 Data 63 to 56 Data Bus D23 to D16 -- -- Data 7 to 0 -- -- Data 7 to 0 Data 23 to 16 Data 23 to 16 Data 55 to 48 D15 to D8 D7 to D0 -- Data 7 to 0 -- -- Data 15 to 8 -- Data 15 to 8 Data 15 to 8 Data 47 to 40 Data 7 to 0 -- -- -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Data 39 to 32 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, WE3 DQM3 Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 WE0, WE0 DQM0 Asserted
Rev. 1.0, 02/03, page 284 of 1294
Table 10.13 16-Bit Off-Chip Device/Little-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte 2n 2n+1 Word Longword 2n 4n 4n+2 Quadword 8n 8n+2 8n+4 8n+6 1 1 1 1 2 1 2 3 4 -- -- -- -- -- -- -- -- -- Data Bus D23 to D16 -- -- -- -- -- -- -- -- -- D15 to D8 -- Data 7 to 0 Data 15 to 8 Data 15 to 8 D7 to D0 Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted WE3, WE3 DQM3 Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 WE0, WE0 DQM0 Asserted
Data Data 31 to 24 23 to 16 Data 15 to 8 Data 7 to 0
Data Data 31 to 24 23 to 16 Data Data 47 to 40 39 to 32 Data Data 63 to 56 55 to 48
Rev. 1.0, 02/03, page 285 of 1294
Table 10.14 8-Bit Off-Chip Device/Little-Endian Access and Data Alignment
Operation Access D31 to Size Address No. D24 Byte Word n 2n 2n+1 Longword 4n 4n+1 4n+2 4n+3 Quadword 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 1 1 2 1 2 3 4 1 2 3 4 5 6 7 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data Bus D23 to D16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D15 to D8D7 to D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 Data 39 to 32 Data 47 to 40 Data 55 to 48 Data 63 to 56 WE3, WE3 DQM3 Strobe Signals WE2, WE2 DQM2 WE1, WE1 DQM1 WE0, WE0 DQM0 Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted
Rev. 1.0, 02/03, page 286 of 1294
10.6.2
Areas
(1) Area 0 For area 0, off-chip address bits A28 to A26 are 000. The interfaces that can be set for this area are SRAM, MPX, and burst ROM. A bus width of 8, 16, or 32 bits is selectable with pins MD4 and MD3 at a power-on reset caused by the RESET pin. When area 0 is accessed, the CS0 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 15 wait cycles can be selected with bits A0W2 to A0W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected in the range of 2 to 9 according to the number of wait cycles. The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A0S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A0H1 and A0H0 within a range of 0 to 3 cycles. (2) Area 1 For area 1, off-chip address bits A28 to A26 are 001. The interfaces that can be set for this area are SRAM, MPX, and byte control SRAM. When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A1SZ1 and A1SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A1SZ1 and A1SZ0 in BCR2. When the byte control SRAM interface is in use, select a bus width of 16 or 32 bits. When area 1 is accessed, the CS1 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A1W2 to A1W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY).
Rev. 1.0, 02/03, page 287 of 1294
The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A1S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A1H1 and A1H0 within a range of 0 to 3 cycles. (3) Area 2 For area 2, off-chip address bits A28 to A26 are 010. The interfaces that can be set for this area are SRAM, MPX, and synchronous DRAM. When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A2SZ1 and A2SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A2SZ1 and A2SZ0 in BCR2. When the synchronous DRAM interface is in use, select 32 bits by the SZ bits in MCR. When area 2 is accessed, the CS2 signal is asserted. When the SRAM interface is in use, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A2W2 to A2W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A2S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A2H1 and A2H0 within a range of 0 to 3 cycles. When the synchronous DRAM interface is in use, the RAS, CAS, and RD/WR signals and byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed. Timing control for signals RAS, CAS, and data, and address multiplexing control, can be specified by MCR. (4) Area 3 For area 3, off-chip address bits A28 to A26 are 011. The interfaces that can be set for this area are SRAM, MPX, and synchronous DRAM. When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A3SZ1 and A3SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A3SZ1 and A3SZ0 in BCR2. When the synchronous DRAM interface is in use, select 32 bits by the SZ bits in MCR. When area 3 is accessed, the CS3 signal is asserted. When the SRAM interface is in use, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted.
Rev. 1.0, 02/03, page 288 of 1294
As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A3W2 to A3W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A3S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A3H1 and A3H0 within a range of 0 to 3 cycles. When the synchronous DRAM interface is in use, the RAS, CAS, and RD/WR signals and byte control signals DQM0 to DQM3 are asserted, and address multiplexing is performed. Timing control for signals RAS, CAS, and data, and address multiplexing control, can be specified by MCR. (5) Area 4 For area 4, off-chip address bits A28 to A26 are 100. The interfaces that can be set for this area are SRAM, MPX, and byte control SRAM. When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A4SZ1 and A4SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A4SZ1 and A4SZ0 in BCR2. When the byte control SRAM interface is in use, select a bus width of 16 or 32 bits. When area 4 is accessed, the CS4 signal is asserted. In addition, the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A4W2 to A4W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A4S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A4H1 and A4H0 within a range of 0 to 3 cycles. (6) Area 5 For area 5, off-chip address bits A28 to A26 are 101. The interfaces that can be set for this area are SRAM, MPX, burst ROM, and PCMCIA.
Rev. 1.0, 02/03, page 289 of 1294
When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A5SZ1 and A5SZ0 in BCR2. When the burst ROM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A5SZ1 and A5SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A5SZ1 and A5SZ0 in BCR2. When the PCMCIA interface is in use, select 8 or 16 bits by bits A5SZ1 and A5SZ0 in BCR2. When area 5 is accessed while the SRAM interface is in use, the CS5 signal is asserted. the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While the PCMCIA interface is in use, the CE1A and CE2A signals, the RD signal, which can be used as OE, the WE1, WE2, WE3, and WE0 signals, which can be used as WE, ICIORD, ICIOWR, and REG, respectively, are asserted. As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A5W2 to A5W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected in the range of 2 to 9 according to the number of wait cycles. The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A5S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A5H1 and A5H0 within a range of 0 to 3 cycles. For a PCMCIA interface, the setup time of the address, CE1A, and CE2A signals with respect to the read/write strobe can be specified by bits A5TED1 and A5TED0 in PCR within a range of 0 to 15 cycles. The hold time of the address, CE1A, and CE2A signals can be specified by bits A5TEH1 and A5TEH0 in PCR within a range of 0 to 15 cycles. The number of wait cycles can be specified by bits A5PCW1 and A5PCW0 within a range of 0 to 50 cycles. The number of wait cycles specified by PCR is added to the value specified by WCR2. (7) Area 6 For area 6, off-chip address bits A28 to A26 are 110. The interfaces that can be set for this area are SRAM, MPX, burst ROM, and PCMCIA. When the SRAM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A6SZ1 and A6SZ0 in BCR2. When the burst ROM interface is in use, a bus width of 8, 16, or 32 bits is selectable with bits A6SZ1 and A6SZ0 in BCR2. When the MPX interface is in use, a bus width of 32 bits should be selected by bits A6SZ1 and A6SZ0 in BCR2. When the PCMCIA interface is in use, select 8 or 16 bits by bits A6SZ1 and A6SZ0 in BCR2.
Rev. 1.0, 02/03, page 290 of 1294
When area 6 is accessed while the SRAM interface is in use, the CS6 signal is asserted. the RD signal, which can be used as OE, and write control signals WE0 to WE3 are asserted. While the PCMCIA interface is in use, the CE1B and CE2B signals, the RD signal, which can be used as OE, the WE1, WE2, WE3, and WE0 signals, which can be used as WE, ICIORD, ICIOWR, and REG, respectively, are asserted. As regards the number of bus cycles, 0 to 15 wait cycles is selectable with bits A6W2 to A6W0 in WCR2. In addition, any number of wait cycles can be inserted in each bus cycle by the external wait pin (RDY). When the burst ROM interface is in use, the number of bus cycles for burst transfer is selected in the range of 2 to 9 according to the number of wait cycles. The setup time of the address and CS signal with respect to the read/write strobe can be specified by bit A6S0 in WCR3 within a range of 0 to 1 cycle. The data-hold time of the address and CS signal with respect to the read/write strobe can be specified by bits A6H1 and A6H0 within a range of 0 to 3 cycles. The setup time of the address, CE1B, and CE2B signals with respect to the read/write strobe can be specified by bits A6TED1 and A6TED0 in PCR within a range of 0 to 15 cycles. The hold time of the address, CE1B, and CE2B signals can be specified by bits A6TEH1 and A6TEH0 in PCR within a range of 0 to 15 cycles. The number of wait cycles can be specified by bits A6PCW1 and A6PCW0 within a range of 0 to 50 cycles. The number of wait cycles specified by PCR is added to the value specified by WCR2. 10.6.3 SRAM Interface
(1) Basic Timing The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM connection. Figure 10.6 shows the basic timing of SRAM interface. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is asserted at the rising edge of the clock in the T1 state, and negated at the rising edge of the clock after the T2 state. Therefore, there is no negation period in the case of access at minimum pitch. When reading, specifying an access size is not needed. The output addresses on the address pins (A25 to A0) are correct, but since the access size is not specified, 32-bit data is always output when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use. When writing, only the WEn signal corresponding to the byte to be written is asserted. For details, see section 10.6.1, Endian/Access Size and Data Alignment.
Rev. 1.0, 02/03, page 291 of 1294
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width. The first access is performed on the data for which there was an access request, and the remaining accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not released during this transfer.
T1 CKIO A25-A0 CSn RD/WR RD D31-D0 (read) WEn D31-D0 (write) BS T2
RDY DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA)
SA: Single address DMA DA: Dual address DMA Note: For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn of the DMAC is cleared to 0.
Figure 10.6 Basic Timing of SRAM Interface
Rev. 1.0, 02/03, page 292 of 1294
Figures 10.7, 10.8, and 10.9 show examples of connection to 32-, 16-, and 8-bit data width SRAM.
128k x 8-bit SRAM
****
**** ****
This LSI A18 A2 CSn RD D31
****
****
D24 WE3 D23 D16 WE2 D15
****
**** ****
****
****
I/O0 WE
****
****
****
D0 WE0
****
I/O0 WE A16 A0 CS OE I/O7 I/O0 WE
**** **** **** ****
****
****
A16 A0 CS OE I/O7 I/O0 WE
Figure 10.7 Example of 32-Bit Data Width SRAM Connection
Rev. 1.0, 02/03, page 293 of 1294
****
****
D8 WE1 D7
A0 CS OE I/O7
****
****
A16
****
A0 CS OE I/O7
****
A16
This LSI A17
**** **** ****
128k x 8-bit SRAM
**** **** **** ****
A16 A0 CS OE I/O7
****
A1 CSn RD D15
****
D8 WE1 D7
****
I/O0 WE
****
****
D0 WE0
A16 A0 CS OE I/O7
****
I/O0 WE
Figure 10.8 Example of 16-Bit Data Width SRAM Connection
128k x 8-bit SRAM A16
**** **** ****
This LSI
A16 A0 CS OE I/O7
**** **** ****
A0 CSn RD D7
****
D0 WE0
I/O0 WE
Figure 10.9 Example of 8-Bit Data Width SRAM Connection
Rev. 1.0, 02/03, page 294 of 1294
****
(2) Wait State Control Wait-state insertion for the SRAM interface can be controlled by WCR2. If the wait-control bits for each area in WCR2 are not zero, a software wait is inserted in accordance with the wait-control bits. For details, see section 10.5.6, Wait Control Register 2 (WCR2). A specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait timing shown in figure 10.10.
T1 CKIO A25-A0 CSn RD/WR RD D31-D0 (read) WEn D31-D0 (write) Tw T2
BS
RDY DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA)
Note: For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn of the DMAC is cleared to 0.
Figure 10.10 SRAM Interface Wait Timing (Software Wait Only)
Rev. 1.0, 02/03, page 295 of 1294
When software wait insertion is specified by WCR2, the external wait input RDY signal is also sampled. RDY signal sampling is shown in figure 10.11. A single-wait cycle as a software wait is specified in figure 10.11. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the RDY signal has no effect if asserted in the T1 cycle or in the first Tw cycle. The RDY signal is sampled on the rising edge of the clock.
T1 CKIO
Tw
Twe
T2
A25-A0 CSn RD/WR RD (read) D31-D0 (read) WEn (write) D31-D0 (write)
BS
RDY DACKn (SA: IO memory) DACKn (SA: IO memory) DACKn (DA)
Note: For DACKn, an example is shown where the acknowledge level (AL) bit in CHCRn of the DMAC is cleared to 0.
Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal)
Rev. 1.0, 02/03, page 296 of 1294
(3) Read-Strobe Negate Timing When the SRAM interface is in use, timing for the negation of the strobe during read operations can be specified by the A1RDH and A4RDH bits in WCR3. When the byte control SRAM interface is in use, AnRDH should be cleared to 0.
TS1
T1
Tw
Tw
Tw
T2
TH1
TH2
CKIO
A25-A0
CSn
RD/WR * RD
D31-D0 BS
TS1: Setup wait AnS in WCR3 (0 to 1)
Tw: Access wait AnW in WCR2 (0 to 15)
TH1, TH2: Hold wait AnH in WCR3 (0 to 3)
Note: * Where the AnRDH bit is set to 1.
Figure 10.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting; AnS = 1, AnW = 011, AnH = 10)
Rev. 1.0, 02/03, page 297 of 1294
BS2, (4) DCK, BS2 and CS1 Timing when Setting Clock Division Register Figure 10.13 shows the SRAM read timing when the division ratio is set to CKIO/2 by DIV[1:0] in DCKDR.
TS1 CKIO A25-A0 CS1 RD/WR RD D31-D0 (read) BS DCK BS2 T1 Tw Tw Tw T2 TH1 TH2
BS2, Figure 10.13 DCK, BS2 and CS1 Timing when Reading SRAM Interface (DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3, CSH[1:0] in WCR4 = 10, Three Wait Cycles)
Rev. 1.0, 02/03, page 298 of 1294
Figure 10.14 shows the SRAM write timing when DCKDR is set to 1/2.
TS1 CKIO A25-A0 CS1 RD/WR WEn D31-D0 (write) BS DCK BS2 T1 Tw Tw Tw T2 TH1 TH2
BS2, Figure 10.14 DCK, BS2 and CS1 Timing when Writing to SRAM Interface (DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3, CSH[1:0] in WCR4 = 10, Three Wait Cycles)
Rev. 1.0, 02/03, page 299 of 1294
The negate timing for CS1 and RD should be set as follows:
Number of Inserted Wait Cycles during Data Holding 0 1 2 3 0 0 1 1
A1H[1:0] 0 1 0 1 0 0 1 1
CSH[1:0] 0 1 0 1
10.6.4
Synchronous DRAM Interface
(1) Synchronous DRAM Connection System Since synchronous DRAM is selectable with the CS signal, it can be connected to off-chip memory space areas 2 and 3 and share usage of RAS and other control signals. If bits DRAMTP2 to DRAMTP0 in BCR1 are 010, area 3 becomes a synchronous DRAM interface. If set to 011, areas 2 and 3 both become synchronous DRAM interfaces. This LSI supports burst read and burst write modes with a burst length of 4 as a synchronous DRAM operating mode. The data bus width is 32 bits, and the SZ bits in MCR must be set to 11. A 32-byte burst transfer is performed in a cache fill/copy-back cycle. For write operations in the write-through area and read/write operations in the non-cacheable area, 16-byte data is also read in a single read because the synchronous DRAM is accessed by burst read/write operations with a burst length of 4. Transfer of 16-byte data is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. This LSI also supports read and burst read and burst write modes with a burst length of 8 as a synchronous DRAM operating mode. The data bus width is 32 bits, and the SZ bits in MCR must be set to 11. A 32-byte burst transfer is performed in a cache fill/copy-back cycle. For write operations in the write-through area and read/write operations in the non-cacheable area, 32-byte data is also read in a single read because the synchronous DRAM is accessed by burst read/write operations with a burst length of 8. Transfer of 32-byte data is also performed in a single write, but DQMn is not asserted when unnecessary data is transferred. For details of setting a burst length of 8, refer to (11) Changing the Burst Length, in section 10.6.4. For details of burst length, refer to section 10.5.11, Synchronous DRAM Mode Register (SDMR), and (10) Power-on Sequence, in section 10.6.4.
Rev. 1.0, 02/03, page 300 of 1294
The control signals for connecting synchronous DRAM are RAS, CASS, RD/WR, CS2 or CS3, DQM0 to DQM3, and CKE. All signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and latched only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to multiple areas. CKE is negated (to low level) when the frequency is changed, when the clock is unstable during stopping of the clock or restarting of the clock supply, or when self-refreshing is performed. Otherwise, CKE is always asserted (to high level). RAS, CASS, RD/WR, and specific address signals specify commands for synchronous DRAM. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register setting (MRS). Bytes are specified by DQM0 to DQM3. A read/write is performed for the byte where the corresponding DQM signal is low. When the bus width is 32 bits in big-endian mode, DQM3 specifies an access to address 4n and DQM0 specifies an access to address 4n + 3. In littleendian mode, DQM3 specifies an access to address 4n + 3 and DQM0 specifies an access to address 4n. Figure 10.15 shows an example of the connection of 16M x 16-bit synchronous DRAMs.
512k x 16-bit x 2-bank synchronous DRAM A9-A0 CLK CKE CS RAS CAS WE I/O15-I/O0 DQMU DQML
This LSI A11-A2 CKIO CKE CS3 RAS RD RD/WR D31-D16 DQM3 DQM2
D15-D0 DQM1 DQM0
A9-A0 CLK CKE CS RAS CAS WE I/O15-I/O0 DQMU DQML
Figure 10.15 Connection Example of Synchronous DRAM with 32-Bit Data Width (Area 3)
Rev. 1.0, 02/03, page 301 of 1294
(2) Address Multiplexing Address multiplexing is performed so that synchronous DRAM can be connected without offchip multiplexing circuitry in accordance with the address multiplexing bits AMXEXT and AMX2 to AMX0 in MCR. Table 10.15 shows the relationship between the address multiplexing bits and the bits output on the address pins. The address signals output on address pins A25 to A18, A1, and A0 are not guaranteed. A0, which serves as the LSB of the synchronous DRAM address pin, specifies the longword address connected to this LSI. Therefore, be sure to first connect pin A0 of the synchronous DRAM to pin A2 of this LSI, and then connect pin A1 to pin A3. Table 10.15 Example of Correspondence between This LSI and Synchronous DRAM Address Pins (32-Bit Bus Width, AMX2 to AMX0 = 000, AMXEXT = 0)
Address Pin of This LSI RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used CAS Cycle A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 Not used Not used Synchronous DRAM Address Pin A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used
Function Select bank address BANK Address precharge setting Address
Rev. 1.0, 02/03, page 302 of 1294
(3) Burst Read The timing chart for a burst read is shown in figure 10.16. The example below assumes that two 512k x 16-bit x 2-bank synchronous DRAMs are connected, and a 32-bit data width is used. The burst length is 4. An ACTV command is output in the Tr cycle and then a READ command is issued in the Tcl cycle. After 4 cycles, a READA command is issued and the read data is fetched on the rising edge of the off-chip command clock (CKIO) from cycle Td1 to cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM, and no new access commands can be issued to the same bank during this waiting period. In this LSI, the number of Tpc cycles is determined based on the bits TPC2 to TPC0 in MCR that are specified, and no commands are issued for the synchronous DRAM during this period. The example in figure 10.16 shows the basic cycle. To connect slower synchronous DRAM, setting bits WCR2 and MCR can extend the cycle. The bits RCD1 and RCD0 in MCR can be used to specify the number of cycles from the ACTV command output cycle Tr to the READ command output cycle Tc1, with the values of 0 to 3 corresponding to 2 to 4 cycles, respectively. For 2 or more cycles, a Trw cycle, which issues an NOP command for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. Bits A2W2 to A2W0 and A3W2 to A3W0 in WCR2 can be used to specify the number of cycles from READ command output cycle Tc1 to the first read data latch cycle Td1 as 1 to 5 cycles independently for areas 2 and 3. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Rev. 1.0, 02/03, page 303 of 1294
Tr CKIO Bank Precharge-sel
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tpc
Row Row Row H/L c1 H/L c5
Address CSn RD/WR RAS CASS DQMn D31-D0 (read) BS CKE DACKn (SA: IO memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.16 Basic Timing for Synchronous DRAM Burst Read In a synchronous DRAM cycle, the BS signal is asserted for one cycle at the beginning of each data transfer cycle corresponding to a READ or READA command. When the data is accessed in the fill operation for a cache miss, the 64-bit boundary data including the missing data are first read by the initial READ command, and then the 16-byte boundary data including the missing data are read in wraparound mode. READA commands that are subsequently issued are used to read the 16 bytes of data, which is the remainder of the 32-byte boundary data. (4) Single Read The timing chart for a single read is shown in figure 10.17. In this LSI, since synchronous DRAM is set to burst read/burst write mode, read data continues to be output even after the required data has been received. To prevent data collisions, after the required data is read in cycle Td1, dummy read cycles Td2 to Td4 are performed, and this LSI waits for the end of the synchronous DRAM operation.
Rev. 1.0, 02/03, page 304 of 1294
There are 4 burst transfers during a read. In cache-through and other DMA read cycles, the BS signal is asserted and data is latched only in cycle Td1 of cycles Td1 to Td4. Such dummy cycles increase the memory access time and tend to reduce program execution speed and DMA transfer speed. It is important both to avoid access to unnecessary cachethrough areas and to use a data structure that allows data to be placed at a 32-byte boundary for transfer in 32-byte units when carrying out DMA transfer with synchronous DRAM specified as the source.
Tr CKIO Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Tpc
Bank
Precharge-sel
Row
Row
H/L c1
Address
CSn RD/WR RAS CASS DQMn
Row
D31-D0 (read)
c1
BS
CKE
DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.17 Basic Timing for Synchronous DRAM Single Read
Rev. 1.0, 02/03, page 305 of 1294
(5) Burst Write The timing chart for a burst write is shown in figure 10.18. In this LSI, a burst write occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT command is issued in cycle Tc1 following the Tr cycle where the ACTV command is output, and then 4 cycles later, the WRITA command is issued. In the write cycle, the write data is output at the same time as the write command. For the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle Tpc used in a read access, cycle Trwl is also added as a wait cycle until precharging is started following the write command for delaying issuance of a new command for the synchronous DRAM during this period. Bits TRWL2 to TRWL0 in MCR can be used to specify the number of Trwl cycles. Access is started from 16-byte boundary data, and 32-byte boundary data is written in wraparound mode. DACK is asserted two cycles before the data write cycle.
Tr CKIO Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
Bank
Precharge-sel
Row Row Row H/L c1 H/L c5
Address
CSn RD/WR RAS CASS DQMn
D31-D0 (write)
BS CKE
c1
c2
c3
c4
c5
c6
c7
c8
DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.18 Basic Timing for Synchronous DRAM Burst Write
Rev. 1.0, 02/03, page 306 of 1294
(6) Single Write The basic timing chart for single write access is shown in figure 10.19. In a single write operation, a WRITA command that performs auto-precharge is issued in cycle Tc1 following the Tr cycle where the ACTV command is output. In the write cycle, the write data is output at the same time as the write command. For the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the synchronous DRAM until precharging is completed. Consequently, in addition to the precharge wait cycle Tpc used in a read access, cycle Trwl is also added as a wait cycle until precharging is started following the write command for delaying issuance of a new command for the synchronous DRAM during this period. Bits TRWL2 to TRWL0 in MCR can be used to specify the number of Trwl cycles. DACK is asserted two cycles before the data write cycle. This LSI supports 4- or 8-burst-length read and write operations of synchronous DRAM. Dummy cycles are therefore generated even with single write operations.
Rev. 1.0, 02/03, page 307 of 1294
Tr CKIO Bank
Trw
Tc1
Tc2
Tc3
Tc4
Trw1
Trw1
Tpc
Row Row Row
Precharge-sel Address CSn RD/WR RAS CASS DQMn
H/L c1
D31-D0 (write)
c1
BS CKE DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.19 Basic Timing for Synchronous DRAM Single Write
Rev. 1.0, 02/03, page 308 of 1294
(7) RAS Down Mode The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, the read/write commands perform access using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately without issuing an ACTV command in the same way as in the DRAM RAS down state. Since the synchronous DRAM is internally divided into two or four banks, one row address in each bank can be activated. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, and then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRITA command. When RAS down mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. Bits TPC2 to TPC0 in MCR are used to determine the number of cycles between issuance of the PRE command and the ACTV command. There is a limit on the time tRAS that each bank can be kept in the active state. If execution of a program cannot guarantee that this time value can be observed so that an access to a different row address occurs by a cache miss, auto-refresh must be set and a refresh cycle must be used that is no more than the maximum value of tRAS. This makes it possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 10.20, a burst read cycle for the same row address in figure 10.21, and a burst read cycle for different row addresses in figure 10.22. Similarly, a burst write cycle without auto-precharge is shown in figure 10.23, a burst write cycle for the same row address in figure 10.24, and a burst write cycle for different row addresses in figure 10.25. When synchronous DRAM is read, there is a 2-cycle latency for the DQMn signal that specifies the bytes. As a result, when the READ command is issued in figure 10.20, if the Tc cycle is executed immediately, the DQMn signal is not specified for the cycle Td1 data output. Therefore, the CAS latency should not be set to 1.
Rev. 1.0, 02/03, page 309 of 1294
When RAS down mode is set, and if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 10.20 or 10.23, and repeats the cycle in figure 10.21 or 10.24. An access to a different area during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected, the bus cycle in figure 10.22 or 10.25 is executed instead of that in figure 10.21 or 10.24. In RAS down mode, a PALL command is also issued before a refresh cycle or before bus release due to bus arbitration.
Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 H/L c5 Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 Td5 Td6 Td7 Td8
D31-D0 (read)
c1
c2
c3
c4
c5
c6
c7
c8
BS CKE DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.20 Burst Read Timing
Rev. 1.0, 02/03, page 310 of 1294
Tc1 CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D31-D0 (read)
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
H/L c1 c5
H/L
c1
c2
c3
c4
c5
c6
c7
c8
BS CKE DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.21 Burst Read Timing (RAS Down, Same Row Address)
Rev. 1.0, 02/03, page 311 of 1294
Tpr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D31-D0 (read)
Tpc
Tr
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
Row Row Row c1 H/L c5 H/L
c1
c2
c3
c4
c5
c6
c7
c8
BS CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.22 Burst Read Timing (RAS Down, Different Row Addresses)
Rev. 1.0, 02/03, page 312 of 1294
Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
Row Row Row c1 H/L c5 H/L
D31-D0 (write) BS CKE DACKn (SA: IO memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.23 Burst Write Timing
Rev. 1.0, 02/03, page 313 of 1294
Tnop (Tnop) CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
H/L c1 c5
H/L
D31-D0 (write) BS CKE DACKn (SA: IO memory)
c1
c2
c3
c4
c5
c6
c7
c8
Single address DMA Normal write
Note:
The (Tnop) cycle is inserted only for SA-DMA. The DACKn signal is output as indicated by the solid line. In the case of a normal write, the (Tnop) cycle is deleted and the DACKn signal is output as indicated by the dotted line. For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.24 Burst Write Timing (Same Row Address)
Rev. 1.0, 02/03, page 314 of 1294
Tpr CKIO Bank Precharge-sel Adress CSn RD/WR RAS CASS DQMn
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
Row H/L Row Row c1 H/L c5 H/L
D31-D0 (Write) BS CKE DACKn (SA: IO memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.25 Burst Write Timing (Different Row Addresses) (8) Pipelined Access When the RASD bit in MCR is set to 1, pipelined access is performed for faster access to synchronous DRAM between an access by the CPU and an access by the DMAC or for consecutive accesses by the DMAC. Since synchronous DRAM is internally divided into two or four banks, after a READ or WRIT command is issued for one bank it is possible to issue a PRE, ACTV, or other command during the CAS latency cycle, data latch cycle, or data write cycle for shortening the access cycle. When a read access is followed by another read access to the same row address, after a READ command has been issued, another READ command is issued before the end of the data latch cycle so that read data is on the data bus continuously. When an access is made to another row address and a different bank, the PRE command or ACTV command can be issued during the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row addresses in the same bank, the PRE command cannot be issued until one cycle before the last data latch cycle. If a write access follows a read access, a PRE or ACTV command can be
Rev. 1.0, 02/03, page 315 of 1294
issued depending on the bank and row address, but since the write data is output at the same time as the WRIT command, the PRE, ACTV, and WRIT commands are issued so that one or two dummy cycles occur automatically on the data bus. Similarly, when a read access follows a write access, or a write access follows a write access, the PRE, ACTV, or READ command is issued during the data write cycle for the preceding access. However, a PRE command cannot be issued for different row addresses in the same bank, and so the PRE command is issued following the number of Trwl cycles specified by the TRWL bit in MCR after the end of the last data write cycle. Figure 10.26 shows a burst read cycle for different banks and row addresses from the preceding burst read cycle. Pipelined access is enabled only for consecutive access to area 3, and is aborted when there is an access to another area. Pipelined access is also aborted in the event of a refresh cycle, or bus release due to bus arbitration. The cases where pipelined access is available are shown in table 10.16. In this table, DMAC dual indicates transfer by DMAC dual address mode, and DMAC single indicates transfer by DMAC single address mode.
Tc1_A CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn D31-D0 (read) BS CKE a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 H/L c1_A H/L c5_A H/L c1_B H/L c5_B Tc1_B
Figure 10.26 Burst Read Cycle for Different Bank and Row Address From Preceding Burst Read Cycle
Rev. 1.0, 02/03, page 316 of 1294
Table 10.16 Availability of Pipelined Access for Cycles
Next Access CPU Previous Access CPU DMAC dual DMAC single Read Write Read Write Read Write Read X X X O O O Write X X X O O O DMAC Dual Read O O X O O O Write X X X X X X DMAC Single Read O O X O O O Write O O X O O O
O: Pipelined access available X: Pipelined access not available
(9) Refreshing The bus state controller is provided with a function for controlling refreshing of the synchronous DRAM. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period of time, both the RMODE bit and the RFSH bit can be set to 1 to activate self-refresh mode, which uses low power consumption for data retention. (a) Auto-Refreshing Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to CKS0 in RTCSR and the value set in RTCOR. Bits CKS2 to CKS0 and RTCOR should be set to satisfy the refresh interval specification for the synchronous DRAM that is used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, and then make the CKS2 to CKS0 setting last. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 10.27 shows the auto-refresh operation and figure 10.29 shows the synchronous DRAM auto-refresh timing. First, an REF command is issued in the TRr2 cycle. A new command is not output for the duration of (TRr cycles) + (number of cycles specified by bits TRAS2 to TRAS0 in MCR) + (number of cycles specified by bits TRC2 to TRC0 in MCR). Bits TRAS2 to TRAS0 and TRC2 to TRC0 must be set to satisfy the synchronous DRAM refresh cycle time specification (active-active command delay time).
Rev. 1.0, 02/03, page 317 of 1294
Auto-refreshing is performed in normal operation, in sleep mode, and at a manual reset. Also, if both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is performed after area 3.
RTCNT value RTCOR-1
RTCNT cleared to 0 when RTCNT = RTCOR
H'00000000 RTCSR.CKS2-0 Refresh request External bus = 000 000
Time
Refresh request cleared by start of refresh cycle Auto-refresh cycle
Figure 10.27 Auto-Refresh Operation
TRr1 CKIO TRr2 TRr3 TRr4 TRrw TRr5 Trc Trc Trc
CSn RD/WR RAS CASS DQMn
D31-D0
BS CKE
Figure 10.28 Synchronous DRAM Auto-Refresh Timing
Rev. 1.0, 02/03, page 318 of 1294
(b) Self-Refreshing Self-refresh mode is a type of software standby mode where the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the selfrefresh state. Self-refresh mode is canceled by clearing the RMODE bit to 0. After selfrefresh mode has been cancelled, the issuing of commands is prohibited for the number of cycles specified by bits TRC2 to TRC0 in MCR. Self-refresh timing is shown in figure 10.29. Settings must be made so that self-refresh cancellation and data retention are performed correctly and auto-refreshing is performed at the correct intervals. When selfrefreshing is activated from a state where auto-refreshing is set or when canceling software standby mode using a method other than a power-on reset, setting the RFSH bit to 1 and clearing the RMODE bit to 0 when self-refresh mode is cleared will restart auto-refreshing. If the transition from canceling self-refresh mode to starting auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value enables refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using this LSI software standby function and is maintained even after recovery from software standby mode using a method other than power-on reset. In the case of a power-on reset, the self-refresh state is cancelled since the bus state controller's registers are initialized. Self-refreshing is continued in sleep mode, in software standby mode, and at a manual reset.
Rev. 1.0, 02/03, page 319 of 1294
TRs1 CKIO
TRs2
TRs3
TRs4
TRs5
Trc
Trc
Trc
CSn RD/WR RAS CASS DQMn D31-D0 BS CKE
Figure 10.29 Synchronous DRAM Self-Refresh Timing (c) Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus cycles generated due to a smaller data bus width than the access size (such as when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back. Refresh operations are also deferred between read and write cycles during execution of a TAS instruction and between read and write cycles when DMAC dual address transfer is executed. If a refresh request occurs when the bus has been released by the bus arbitration function, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed correctly, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the BACK signal is negated (driven high). Therefore, correct refreshing can be performed by monitoring the BACK signal using a bus arbiter or bus master other than this LSI requesting the bus, and returning the bus to this LSI.
Rev. 1.0, 02/03, page 320 of 1294
(10) Power-On Sequence To use synchronous DRAM, the mode must first be set after power is supplied. To initialize synchronous DRAM correctly, the bus state controller registers must first be set, and then writing must be performed to the synchronous DRAM mode register. In the synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller operates so that the value X is written to the synchronous DRAM mode register by performing a write to address H'FF90 0000 + X for area 2 synchronous DRAM, and to address H'FF94 0000 + X for area 3 synchronous DRAM. In this operation, the data is ignored, but the mode write is performed as a byte-size access. To set burst read/burst write, CAS latency 1 to 3, wrap type = sequential, and burst length 4 or 8, which are supported by this LSI, arbitrary data is written in byte-size access to the following addresses.
Bus Width 32 Burst Length CAS Latency 4 1 2 3 32 8 1 2 3 Area 2 H'FF90 0048 H'FF90 0088 H'FF90 00C8 H'FF90 004C H'FF90 008C H'FF90 00CC Area 3 H'FF94 0048 H'FF94 0088 H'FF94 00C8 H'FF94 004C H'FF94 008C H'FF94 00CC
The MRSET bit in MCR selects whether a precharge all banks command or a mode register setting command is issued. The timing for the precharge all banks command is shown in figure 10.30(1), and the timing for the mode register setting command is shown in figure 10.30(2). Before setting the mode register, a 200-s idle time (this is required for the synchronous DRAM and varies depending on the memory manufacturer) after power is supplied must be guaranteed. There is no problem in making the precharge all banks setting immediately if the reset signal pulse width is greater than this idle time. First, a precharge all banks (PALL) command is issued in the TRp1 cycle by writing to address H'FF90 0000 + X or H'FF94 0000 + X while the MRSET bit in MCR is cleared to 0. Next, the number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is achieved automatically while performing various kinds of initialization after the auto-refresh setting is made, but a more accurate way is to change the RTCOR value only while these dummy cycles are being executed to set a short interval that generates refresh requests. With simple read or write access, the address counter in the synchronous DRAM used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After auto-refreshing has been executed at least the prescribed number of times, a mode register write command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and writing to address H'FF90 0000 + X or H'FF94 0000 + X.
Rev. 1.0, 02/03, page 321 of 1294
The synchronous DRAM mode register should be configured only once after power-on reset and before synchronous DRAM access, and the setting should not be changed once it is made.
TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 TMw5
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D31-D0 CKE
(High)
Figure 10.30(1) Synchronous DRAM Mode Write Timing (PALL)
Rev. 1.0, 02/03, page 322 of 1294
TRp1 CKIO
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
TMw5
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
D31-D0 CKE
(High)
Figure 10.30(2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
Rev. 1.0, 02/03, page 323 of 1294
(11) Changing the Burst Length When synchronous DRAM is connected to this LSI with a 32-bit memory bus width, a burst length of either 4 or 8 is specifiable with the SDBL bit in BCR3. For more details, see the description of the BCR3 register. (a) Burst Read Figure 10.31 is the timing chart for burst-read operations. In the example shown below, two synchronous DRAMs of 512k x 16 bits x 2 banks are assumed to be connected and used with a 32-bit data width and a burst length of 8. After the Tr cycle which outputs an ACTV command, a READA command is issued in cycle Tc1. During cycles Td1 to Td8, the read data are fetched at the rising edges of the off-chip command clock (CKIO). Tpc is the cycle used to wait for completion of auto-precharging, which is triggered by the READA command, in the synchronous DRAM. During this cycle, no new command that accesses the same bank can be issued. In this LSI, bits TPC2 to TPC0 in MCR are used to determine the number of Tpc cycles, and no commands are issued for the synchronous DRAM during these cycles. Figure 10.31 shows an example of the basic timing of a burst-read. To allow the connection of a lower-speed DRAM, the bits in WCR2 and MCR can be set to increase the number of cycles. Bits RCD1 and RCD0 in MCR can be used to specify the number of cycles from the ACTV command output cycle Tr to the READA command output cycle Tc1, where setting values of 1, 2, or 3 correspond to 2, 3, or 4 cycles, respectively. When two or more cycles are specified, the Trw cycle for issuing of NOP commands to the synchronous DRAM is inserted between the Tr and Tc cycles. Bits A2W2 to A2W0 and A3W2 to A3W0 in WCR2 can be used to set the number of cycles from the READA command output cycle Tc1 to cycle Td1 where the first read data is received. The number of cycles from 1 to 5 is specifiable independently for areas 2 and 3. Note that this number of cycles is equal to the number of CAS latency cycles of the synchronous DRAM.
Rev. 1.0, 02/03, page 324 of 1294
Tr CKIO Bank Precharge-sel Address
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tpc
Row Row Row
CSn RD/WR
RAS
CASS DQMn D31-D0 (read) BS CKE DACKn (SA: IO memory) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
c1
c2
c3
c4
c5
c6
c7
c8
Figure 10.31 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8) In a cycle of access to synchronous DRAM, the BS signal is asserted for one clock cycle at the beginning of a bus cycle. When the data is accessed in the fill operation for a cache miss, the 32-bit boundary data including the missing data are first read, and then the 32byte boundary data including the missing data are read in wraparound mode.
Rev. 1.0, 02/03, page 325 of 1294
(b) Burst Write Figure 10.32 is the timing chart for a burst-write operation with a burst length of 8. In this LSI, a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the DMAC occurs. In a burst-write operation, a WRITA command that performs auto precharging is issued during the Tc1 cycle after the Tr cycle where the ACTV command is output. During the write cycle, the write data is output simultaneously with the write command. For a write command with an auto precharge, since precharging of the relevant bank in the synchronous DRAM is performed after completion of the write command, no new command for the same bank can be issued until precharging has been completed. As a result, besides the precharge waiting cycle Tpc in read access, Trwl cycles are added to provide waiting time until precharging starts after the write command has been issued, and these Trwl cycles delay the issuing of new commands to the same bank. Bits TRWL2 to TRWL0 in MCR can be used to select the number of Trwl cycles. The 32-byte boundary data is written in wraparound mode.
Tr CKIO Bank Precharge-sel Address CSn RD/WR RAS CASS DQMn Row Row Row H/L c1 Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
D31-D0 (write) BS CKE DACKn (SA: IO memory)
c1
c2
c3
c4
c5
c6
c7
c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.32 Basic Timing of a Burst Write to Synchronous DRAM
Rev. 1.0, 02/03, page 326 of 1294
10.6.5
Burst ROM Interface
Setting bits A0BST2 to A0BST0, A5BST2 to A5BST0, and A6BST2 to A6BST0 in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed access to ROM that has a burst access function. The timing for burst access to burst ROM is shown in figure 10.33. No wait cycle is set. Basically, access is performed in the same way as for SRAM interface, but when the first cycle ends, only the address is changed, and then the next access is executed. When ROM having an 8-bit data width is connected, bits A0BST2 to A0BST0, A5BST2 to A5BST0, or A6BST2 to A6BST0 can be used to set the number of consecutive accesses to 4, 8, 16, or 32. When ROM having a 16-bit data width is connected, 4, 8, or 16 accesses can be set in the same way. When ROM having a 32-bit data width is connected, 4 or 8 accesses can be set. The RDY pin sampling is always performed when one or more wait cycles are set. The timing in this case is shown in figure 10.34. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait is specified at 0. The write operation for a burst ROM interface is performed as a SRAM interface. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the bus width that was set. The first access is performed on the data where there was an access request, and the remaining accesses are performed on the 32-byte boundary data. The bus is not released during this operation. Figure 10.35 shows the timing when the burst ROM is set and a setup/hold is specified by WCR3.
Rev. 1.0, 02/03, page 327 of 1294
T1 CKIO
A25-A5
TB2
TB1
TB2
TB1
TB2
TB1
T2
A4-A0
CSn RD/WR RD
D31-D0 (read)
BS
RDY
DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.33 Burst ROM Basic Access Timing
Rev. 1.0, 02/03, page 328 of 1294
T1 CKIO A25-A5
Tw
Twe
TB2
TB1
Tw
TB2
TB1
Tw
TB2
TB1
Tw
T2
A4-A0 CSn RD/WR RD D31-D0 (read) BS
RDY DACKn (SA: IO memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.34 Burst ROM Wait Access Timing
Rev. 1.0, 02/03, page 329 of 1294
TS1 CKIO A25-A5 A4-A0 CSn RD/WR RD D31-D0 (read) BS RDY DACKn (SA: IO memory)
T1
TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1 TB2 TH1 TS1 TB1
T2
TH1
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.35 Burst ROM Wait Access Timing 10.6.6 PCMCIA Interface
In this LSI, setting the A56PCM bit in BCR1 to 1 allows the bus interface for off-chip memory space areas 5 and 6 to become an IC memory card interface or I/O card interface as stipulated in JEIDA specification version 4.2 (PCMCIA2.1). Figure 10.36 shows an example of PCMCIA card connection to this LSI. To enable hot swapping of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a tri-state buffer must be connected between this LSI bus interface and the PCMCIA cards. Since operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface. When the MMU is on, PCMCIA interface memory space can be set in MMU page units, and there is a choice of 8-bit shared memory, 16-bit shared memory, 8-bit attribute memory, 16-bit attribute memory, 8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 6, Memory Management Unit (MMU), for details of the setting method. When the MMU is off, the memory space is always used for access in the setting of bits SA2 to SA0 in PTEA.
Rev. 1.0, 02/03, page 330 of 1294
SA2 0
SA1 0 1
SA0 0 1 0 1 0 1 0 1
Description Reserved (Setting prohibited) Dynamic I/O bus sizing 8-bit I/O space 16-bit I/O space 8-bit shared memory 16-bit shared memory 8-bit attribute memory 16-bit attribute memory
1
0 1
When the MMU is on, wait cycles in a bus access can be set in MMU page units. For details of the setting method, see section 6, Memory Management Unit (MMU). When the MMU is off (MMUCR.AT = 0), access is always performed according to the TC bit in PTEA. When the TC bit is cleared to 0, bits A5W2 to A5W0 in WCR2 and bits A5PCW1 to A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in PCR are selected. When TC is set to 1, bits A6W2 to A6W0 in WCR2 and bits A6PCW1 to A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0 in PCR are selected. Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. Bits AnPCW1 and AnPCW0 in PCR can be used to set the number of wait cycles as 0, 15, 30, or 50 to be inserted in a low-speed bus cycle. This value is added to the number of inserted wait cycles specified by WCR2. Bits AnTED2 to AnTED0 in PCR (with a setting range from 0 to 15) can be used to retain the RD and WE1 signal addresses and the CS, CE2A, CE2B, and REG setup times. Bits AnTEH2 to AnTEH0 in PCR (with a setting range from 0 to 15) can also be used to retain the RD and WE1 signal addresses and the CS, CE2A, CE2B, and REG data hold times. Bits A5IW2 to A5IW0 and A6IW2 to A6IW0 in WCR1 are used to set the number of wait cycles between cycles. The selected number of wait cycles between cycles depends only on the area accessed (area 5 or 6). When area 5 is accessed, bits A5IW2 to A5IW0 are selected, and when area 6 is accessed, bits A6IW2 to A6IW0 are selected. In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the bus width that was set. The first access is performed on the data where there was an access request, and the remaining accesses are performed on the 32-byte boundary data in wraparound mode. The bus is not released during this operation.
Rev. 1.0, 02/03, page 331 of 1294
Table 10.17 Relationship between Address and CE When Using PCMCIA Interface
Bus Width (Bits) 8 Read/ Write Read Access Odd/ Size (Bits)*1 Even 8 Even Odd 16 Even Even Odd Write 8 Even Odd 16 Even Even Odd 16 Read 8 Even Odd 16 Even Odd Write 8 Even Odd 16 Even Odd
IOIS16 Access CE2 * * * * * * * * * * * * * * * * * * -- -- First 1 1 1
CE1 0 0 0 0 -- 0 0 0 0 -- 0 1 0 -- 0 1 0 --
A0 0 1 0 1 -- 0 1 0 1 -- 0 1 0 -- 0 1 0 --
D15 to D8 Invalid Invalid Invalid Invalid -- Invalid Invalid Invalid Invalid -- Invalid Read data
D7 to D0 Read data Read data Lower read data Upper read data -- Write data Write data Lower write data Upper write data -- Read data Invalid
Second 1 -- -- -- First -- 1 1 1
Second 1 -- -- -- -- -- -- -- -- -- -- 1 0 0 -- 1 0 0 --
Upper read data Lower read data -- Invalid Write data -- Write data Invalid
Upper write data Lower write data -- --
Rev. 1.0, 02/03, page 332 of 1294
Bus Width (Bits)
Read/ Write
Access Odd/ Size (Bits)*1 Even 8 Even Odd 16 Even Odd
IOIS16 Access CE2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- First 1 0 0 -- 1 0 0 -- 1 0
CE1 0 1 0 -- 0 1 0 -- 0 1 0 0 0 -- 0 1 0 0 0 --
A0 0 1 0 -- 0 1 0 -- 0 1 1 0 1 -- 0 1 1 0 1 --
D15 to D8 Invalid Read data
D7 to D0 Read data Invalid
Dynamic Read bus sizing*2
Upper read data Lower read data -- Invalid Write data -- Write data Invalid
Write
8
Even Odd
16
Even Odd
Upper write data Lower write data -- Invalid Ignored Invalid Invalid Invalid -- Invalid Invalid Invalid -- Read data Invalid Read data Lower read data Upper read data -- Write data Write data Write data
Read
8
Even Odd Odd
Second 1 First 0
16
Even Even Odd
Second 1 -- -- First -- 1 0
Write
8
Even Odd Odd
Second 1 First 0
16
Even Even Odd
Upper write data Lower write data Invalid -- Upper write data --
Second 1 -- --
Notes: * Don't Care *1. In 32-bit/64-bit/32-byte transfer, the addresses are automatically divided into increments equal to the bus width, and the above accesses are repeated until the transfer data size is reached. *2. PCMCIA I/O card interface only
Rev. 1.0, 02/03, page 333 of 1294
A25-A0 D15-D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A D15-D8 G DIR G DIR D7-D0 G
A25-A0
D15-D0
PC card (memory I/O)
This LSI
CE1 CE2 RD WE1 ICIORD ICIOWR REG RDY IOIS16 Card detection circuit G OE WE/PGM (IORD) (IOWR) REG WAIT (IOIS16) CD1, CD2
A25-A0 G D7-D0 G DIR D15-D8 G DIR CE1 CE2 OE WE/PGM REG WAIT Card detection circuit CD1, CD2 D15-D0
PC card (memory I/O)
G
Figure 10.36 Example of PCMCIA Interface
Rev. 1.0, 02/03, page 334 of 1294
(1) Memory Card Interface Basic Timing Figure 10.37 shows the basic timing for the PCMCIA memory card interface, and figure 10.38 shows the wait timing for the PCMCIA memory card interface.
Tpcm1 Tpcm2
CKIO
A25-A0
CExx REG
RD/WR
RD (read)
D15-D0 (read)
WE1 (write)
D15-D0 (write)
BS
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.37 Basic Timing for PCMCIA Memory Card Interface
Rev. 1.0, 02/03, page 335 of 1294
Tpcm0 CKIO
Tpcm0w
Tpcm1
Tpcm1w Tpcm1w
Tpcm2
Tpcm2w
A25-A0
CExx REG
RD/WR
RD (read)
D15-D0 (read) WE1 (write)
D15-D0 (write)
BS
RDY
DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.38 Wait Timing for PCMCIA Memory Card Interface
Rev. 1.0, 02/03, page 336 of 1294
Common memory (64 Mbytes) Access by CS5 wait controller
Virtual address space 1 kbyte page IO 1 External I/O addresses
Virtual address space Common memory 1 Card 1 on CS5 Common memory 2 Attribute memory I/O space 1 I/O space 2
Access by CS6 wait controller
IO 1 IO 2
Attribute memory (64 Mbytes) . . .
1 kbyte page
IO 2 Different virtual pages mapped to the same physical page
Example of I/O spaces with different cycle times (less than 1 kbyte)
I/O space (64 Mbytes)
Card 2 on CS6 . . .
The page size can be 1 kbyte, 4 kbytes, 64 kbytes, or 1 Mbyte. Example of PCMCIA interface mapping
Figure 10.39 PCMCIA Space Allocation (2) I/O Card Interface Timing Figures 10.40 and 10.41 show the timing for the PCMCIA I/O card interface. When accessing a PCMCIA card as an I/O card interface, it is possible to perform dynamic sizing of the I/O bus width using the IOIS16 pin. With a 16-bit bus width selected, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, and this is automatically followed by a data access for the remaining 8 bits. Dynamic bus sizing is also performed for byte-size access to address 2n + 1. Figure 10.42 shows the basic timing for dynamic bus sizing.
Rev. 1.0, 02/03, page 337 of 1294
Tpci1
Tpci2
CKIO
A25-A0
CExx REG
RD/WR
ICIORD (read)
D15-D0 (read)
ICIOWR (write)
D15-D0 (write)
BS
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.40 Basic Timing for PCMCIA I/O Card Interface
Rev. 1.0, 02/03, page 338 of 1294
Tpci0 CKIO
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
A25-A0
CExx REG
RD/WR
ICIORD (read)
D15-D0 (read) ICIOWR (write)
D15-D0 (write)
BS
RDY
IOIS16
DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.41 Wait Timing for PCMCIA I/O Card Interface
Rev. 1.0, 02/03, page 339 of 1294
Tpci0 CKIO
Tpci
Tpci1w
Tpci2
Tpci2w
Tpci0
Tpci
Tpci1w
Tpci2
Tpci2w
A25-A1
A0 CExx REG RD/WR
ICIORD (read) D15-D0 (read) ICIOWR (write)
D15-D0 (write)
BS
RDY
IOIS16
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.42 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
Rev. 1.0, 02/03, page 340 of 1294
10.6.7
MPX Interface
If the MD6 pin is cleared to 0 at a power-on reset by the RESET pin, the MPX interface is selected for area 0. The MPX interface is selected for areas 1 to 6 by the MPX bit in BCR1 and bits MEMMODE, A4MPX, and A1MPX in BCR3. The MPX interface provides an address/data multiplex type bus protocol and allows easy connection with off-chip memory controller chips using a single 32-bit address/data multiplex bus. A bus cycle consists of an address phase and a data phase, with address information output to D25 to D0 and the access size output to D31 to D29 in the address phase. The BS signal is asserted for one cycle to indicate the address phase. The CSn signal is asserted at the rising edge in Tm1 and is negated after the end of the last data transfer in the data phase. Therefore, a negation cycle does not occur in the case of minimum pitch access. The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase. Therefore, an off-chip device for the MPX interface must internally store the address information and access size output in the address phase and perform data input/output for the data phase. For details of access sizes and data alignment, see section 10.6.1, Endian/Access Size and Data Alignment. Values output to address pins A25 to A20 are not guaranteed. In 32-byte transfer, a total of 32 bytes are transferred consecutively according the bus width that was set. The first access is performed on the data where there was an access request, and the remaining accesses are performed on 32-byte boundary data. If the access size exceeds the set bus width in this way, the address is output once, and then the burst access is performed with multiple continuous data cycles. The bus is not released during this operation.
D31 0 D30 0 1 1 x: Don't care x D29 0 1 0 1 x Access Size Byte Word Longword Quadword 32-byte burst
This LSI CKIO CSn BS RD RD/WR D31-D0 RDY
MPX device CLK CS BS FRAME WE I/O31-I/O0 RDY
Figure 10.43 Example of 32-Bit Data Width MPX Connection
Rev. 1.0, 02/03, page 341 of 1294
The MPX interface timing is shown below. When the MPX interface is used for areas 1 to 6, a bus size of 32 bits should be specified by BCR2. In wait control, waits can be specified by WCR2 and waits can be inserted by the RDY pin. In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to 0.
Tm1 CKIO RD/FRAME D31-D0 A D0 Tmd1w Tmd1
CSn RD/WR
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.44 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)
Rev. 1.0, 02/03, page 342 of 1294
Tm1
CKIO
Tmd1w
Tmd1w
Tmd1
RD/FRAME D31-D0 CSn RD/WR A D0
RDY BS
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.45 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted)
Rev. 1.0, 02/03, page 343 of 1294
Tm1 CKIO RD/FRAME D31-D0 CSn RD/WR A
Tmd1
D0
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.46 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait)
Rev. 1.0, 02/03, page 344 of 1294
Tm1 CKIO RD/FRAME D31-D0 CSn A
Tmd1w
Tmd1w
Tmd1
D0
RD/WR
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.47 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait Inserted)
Rev. 1.0, 02/03, page 345 of 1294
Tm1 CKIO RD/FRAME D31-D0 CSn RD/WR A
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
D1
D2
D3
D4
D5
D6
D7
D8
RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.48 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
Tm1 CKIO RD/FRAME D31-D0 CSn RD/WR A D1 D2 D3 D7 D8 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8
RDY BS DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.49 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.0, 02/03, page 346 of 1294
Tm1 CKIO RD/FRAME D31-D0 CSn RD/WR A
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
D1
D2
D3
D4
D5
D6
D7
D8
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.50 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer)
Tm1 CKIO RD/FRAME D31-D0 CSn RD/WR A D1 D2 D3 D7 D8 Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.51 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)
Rev. 1.0, 02/03, page 347 of 1294
Tm1 CKIO RD/FRAME D31-D0 A
Tmd1w
Tmd1
Tmd2
D0
D1
CSn RD/WR
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.52 MPX Interface Timing 9 (Burst Read Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 64-Bit Data Transfer)
Rev. 1.0, 02/03, page 348 of 1294
Tm1 CKIO
Tmd1w
Tmd1w
Tmd1
Tmd2
RD/FRAME D31-D0 CSn RD/WR A D0 D1
RDY BS
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.53 MPX Interface Timing 10 (Burst Read Cycle, AnW = 0, One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer)
Rev. 1.0, 02/03, page 349 of 1294
Tm1
CKIO RD/FRAME D31-D0 CSn RD/WR A
Tmd1
Tmd2
D0
D1
RDY
BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.54 MPX Interface Timing 11 (Burst Write Cycle, AnW = 0, No External Wait, 32-Bit Bus Width, 64-Bit Data Transfer)
Rev. 1.0, 02/03, page 350 of 1294
Tm1 CKIO RD/FRAME D31-D0 CSn A
Tmd1w
Tmd1w
Tmd1
Tmd2
D0
D1
RD/WR
RDY BS DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.55 MPX Interface Timing 12 (Burst Write Cycle, AnW = 1, One External Wait Inserted, 32-Bit Bus Width, 64-Bit Data Transfer) 10.6.8 Byte Control SRAM Interface
The byte control SRAM interface is a memory interface that outputs a byte select strobe (WEn) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having upper byte select strobe and lower byte select strobe functions such as UB and LB. Areas 1 and 4 can be specified as a byte control SRAM interface. However, when these areas are set to MPX mode, MPX mode has priority. The write timing for the byte control SRAM interface is identical to that of the normal SRAM interface. In read operations, on the other hand, the WEn pin timing is different. In a read access, only the WE signal for the byte being read is asserted. Assertion is synchronized with the falling edge of the CKIO clock in the same way as the WE signal, while negation is synchronized with the rising edge of the CKIO clock in the same way as the RD signal.
Rev. 1.0, 02/03, page 351 of 1294
32-byte transfer is performed consecutively for a total of 32 bytes according to the bus width that was set. The first access is performed on the data where there was an access request. The remaining accesses are performed on the 32-byte boundary data in wraparound mode. The bus is not released during this operation. Figure 10.56 shows an example of a byte control SRAM connection, and figures 10.57 to 10.59 show examples of byte control SRAM read cycles.
64k x 16-bit SRAM A15-A0 CS OE WE I/O15-I/O0 UB LB A15-A0 CS OE WE I/O15-I/O0 UB LB
This LSI
A18-A3 CSn RD RD/WR D31-D16 WE3 WE2
D15-D0 WE1 WE0
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.56 Example of 32-Bit Data Width Byte Control SRAM
Rev. 1.0, 02/03, page 352 of 1294
T1 CKIO
T2
A25-A0
CSn
RD/WR
RD
D31-D0 (read)
WEn
BS
RDY
DACKn (SA: IO memory)
DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.57 Byte Control SRAM Basic Read Cycle (No Wait)
Rev. 1.0, 02/03, page 353 of 1294
T1 CKIO
Tw
T2
A25-A0
CSn
RD/WR
RD
D31-D0 (read)
WEn
BS
RDY
DACKn (SA: IO memory)
DACKn (DA) Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.58 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
Rev. 1.0, 02/03, page 354 of 1294
T1 CKIO
Tw
Twe
T2
A25-A0
CSn
RD/WR
RD
D31-D0 (read)
WEn
BS
RDY
DACKn (SA: IO memory)
DACKn (DA)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.59 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External Wait)
Rev. 1.0, 02/03, page 355 of 1294
10.6.9
Waits between Access Cycles
A problem associated with higher operating frequencies for off-chip memory buses is that the data buffer turn-off after completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and resulting in lower reliability or malfunctions. To prevent this problem, this module provides a data collision prevention function. It stores the preceding access area and the type of read/write and inserts a wait cycle before the access cycle if there is a possibility of a bus collision when the next access is started. The process for wait cycle insertion consists of inserting idle cycles between access cycles as shown in section 10.5.5, Wait Control Register (WCR1). When this LSI performs consecutive write cycles, the data transfer direction is fixed (from this LSI to other memory), and there is no problem. Also, for read accesses to the same area, generally, data is output from the same data buffer, and no wait cycle is inserted. If bits AnIW2 to AnIW0 (n = 0 to 6) in WCR1 are used to set idle cycles between accesses, the number of inserted idle cycles is only the specified number of idle cycles minus the number of idle cycles specified by the bits. When bus arbitration is performed, the bus is released after wait cycles are inserted between cycles. In single address mode DMA transfer from an I/O device to memory, the I/O device speed determines the data on the bus. When a low-speed I/O device is used, a wait time equivalent to the output buffer turn-off time must be inserted between cycles. When a high-speed memory is used, the memory may be unable to run at full speed since insertion of waits between cycles may be required to adjust to the speed of a low-speed device for enabling DMA transfer. Waits between cycles can be specified with bits DMAIW2 to DMAIW0 in wait control register 1 (WCR1) for single address mode DMA transfer from an I/O device to memory. The number of waits that can be inserted should be in the range from 0 to 15. A number of waits specified by the DMAIW2 to DMAIW0 bits are inserted in single address DMA transfers to all areas. In dual address mode DMA transfer, the normal wait between cycles specified by bits AnIW2 to AnIW0 (n = 0 to 6) is inserted.
Rev. 1.0, 02/03, page 356 of 1294
T1 CKIO A25-A0
T2
Twait
T1
T2
Twait
T1
T2
CSm CSn
BS RD/WR
RD
D31-D0
Read from Area m space
Read from Area n space
Write to Area n space
Wait cycle insertion between access cycles specified for Area m
Wait cycle insertion between access cycles specified for Area n
Figure 10.60 Wait Cycles between Access Cycles 10.6.10 Bus Arbitration This LSI provides a bus arbitration function that allows an off-chip device to control the bus in response to a bus request. In normal operation, this LSI controls the bus, and it releases the bus to transfer the right to access the bus when an off-chip device issues a bus request. In the description below, an off-chip device that issues bus requests is referred to as a slave. This LSI has two internal bus masters: the CPU and DMAC. When synchronous DRAM is connected and refresh control is performed, the refresh request serves as the third bus master. Bus requests from off-chip devices are also added when this LSI is in master mode. If requests occur simultaneously, the priority from highest to lowest is based on the following order: bus request from an off-chip device, the refresh request, the DMAC, and the CPU. To prevent malfunctions of connected devices when the right to access the bus is transferred from master to slave, all bus control signals are negated before the bus is released. When the right of access to the bus is received, bus control signals switch from the negated level to start driving the bus. Since signals are driven at the same level by the master and slave transferring the right to access the bus, output buffer collisions can be avoided.
Rev. 1.0, 02/03, page 357 of 1294
The right of access to the bus is transferred at the end of bus cycles. When the bus release request signal (BREQ) is asserted, this LSI releases the bus as soon as the current bus cycle being executed ends and outputs the bus request acknowledge signal (BACK). However, the bus is not released during multiple bus cycles generated due to a smaller data bus width than the access size (such as when performing longword access to 8-bit bus width memory) or during a 32-byte transfer such as a cache fill or write-back. The bus is also not released between read and write cycles during execution of a TAS instruction, or between read and write cycles when DMAC dual address transfer is executed. When BREQ is negated, BACK is negated and use of the bus is resumed. When a refresh request is generated, this LSI performs a refresh operation as soon as the current bus cycle being executed ends. However, refresh operations are deferred during multiple bus cycles generated due to a smaller data bus width than the access size (such as when performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a cache fill or write-back. The refresh operation is also deferred between read and write cycles during execution of a TAS instruction, and between read and write cycles when DMAC dual address transfer is executed. Refresh operations are also deferred in the bus release state. Since the CPU in this LSI is connected to cache memory by a dedicated peripheral bus, the CPU can still read from cache memory when the bus is being used by another bus master inside or outside this LSI. When writing from the CPU, an off-chip write cycle is generated when writethrough has been set for the cache in this LSI, or when an access is made to a cache-off area. This results in a delay until the bus is returned. When this LSI wants to take back the bus in response to an internal memory refresh request, it negates BACK. A device that asserts the off-chip bus release request receives the BACK negation, and then negates BREQ to release the bus. In this way, the bus is returned to this LSI, and then processing is performed.
Rev. 1.0, 02/03, page 358 of 1294
CKIO BREQ BACK A25-A0 CSn RD/WR RD WEn D31-D0 HiZ Must be asserted for at least 2 cycles HiZ HiZ HiZ HiZ HiZ HiZ Must be negated within 2 cycles
Figure 10.61 Arbitration Sequence 10.6.11 Bus Release and Acquire Sequences This LSI controls the bus unless it receives a bus request. As soon as an assertion (low level) of the bus request signal (BREQ) is received from an off-chip device and the current bus cycle being executed ends, this LSI releases the bus and asserts (low level) the bus request acknowledge signal (BACK). If a bus request has not been issued due to a refresh request, this LSI receives the BREQ negation (high level) indicating that the slave has released the bus, and then negates (drives high) the BACK signal and resumes use of the bus. If a bus request is issued due to a refresh request in the bus release state, this LSI negates the bus request acknowledge signal (BACK) and then receives the BREQ negation indicating that the slave has released the bus, and resumes use of the bus. When the bus is released, all bus control output signals and input/output signals pertaining to the bus interface go to the high-impedance state except for CKE in the synchronous DRAM interface, BACK (bus request acknowledge) in bus arbitration, and DACK0 and DACK1 for DMA transfer control. For synchronous DRAM, a precharge command is issued for the active bank, and the bus is released after precharging is completed. The following is the specific bus release sequence. First, the bus request acknowledge signal is asserted at the rising edge of the clock. The address bus and data bus go to the high-impedance state in synchronization with the assertion of BACK. At the same time, the bus control signals (BS, CSn, RAS, WEn, RD, RD/WR, CE2A, and CE2B)
Rev. 1.0, 02/03, page 359 of 1294
go to the high-impedance state. These bus control signals are negated no later than one cycle before going to high-impedance. The bus request signal is sampled at the rising edge of the clock. The following is the specific bus reacquiring sequence from the slave. As soon as BREQ negation is detected at the rising edge of the clock, BACK is negated and the bus control signal driving is started from next rising edge of the clock. Driving of the address bus and data bus also starts at the same rising edge of the clock. The bus control signals are asserted and the bus cycle is actually started, at the earliest, at the next rising edge of the clock where the driving of the bus control signals was started. In order to reacquire the bus and start execution of a refresh operation or bus access, the BREQ signal must be negated for at least two cycles. If a refresh request is generated when BACK has been asserted and the bus has been released, the BACK signal is negated even while the BREQ signal is asserted to request a slave to release the bus. When this LSI is used in master mode with slaves designed independently by the user, consecutive bus accesses may be attempted to reduce the overhead due to arbitration. When connecting a slave where the total duration of consecutive accesses exceeds the refresh cycle, it should be designed so that the bus is released as soon as possible after negation of the BACK signal is detected.
10.7
10.7.1
Usage Notes
Refresh
Auto refresh operations are not carried out when this LSI enters software standby, hardware standby, or deep-sleep mode. If the memory system requires refresh operations, set the memory in the self-refresh state prior to making the transition to software standby, hardware standby, or deepsleep mode. 10.7.2 Bus Arbitration
The bus is not released when this LSI enters software standby or deep-sleep mode. In systems performing bus arbitration, clear the bus release request enable bit (BCR1.BREQEN) to 0 for the processor in master mode before making the transition to software standby or deep-sleep mode. Correct operation is not guaranteed when a transition is made to software standby mode or deepsleep mode with BCR1.BREQEN = 1.
Rev. 1.0, 02/03, page 360 of 1294
Section 11 Direct Memory Access Controller (DMAC)
This LSI includes an on-chip eight-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed data transfers among external devices equipped with DACK (DMA transfer end notification), external memories, memory-mapped external devices, and on-chip peripheral modules. Using the DMAC reduces the burden on the CPU and increases the operating efficiency of this LSI.
11.1
Features
The DMAC has the following features. * * * * * * * * * * * Number of channels: Eight channels Address space: Physical address space Selection of data length: 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length Maximum number of transfers: 16 M (16,777,216) transfers Selection of DMA mode: External request 2-channel mode or DMABRG mode 1 Selection of address mode: Single address mode* or dual address mode 2 3 Selection of transfer requests: External request* , requests from on-chip peripheral modules* , or auto-request Selection of bus mode: Cycle steal mode or burst mode Selection of priority order: Fixed priority mode or round robin mode Channel functions: Different transfer modes (address mode, bus mode, and transfer requests) can be set for each channel. Interrupt request: Interrupt request can be sent to the CPU on completion of data transfer.
Notes: *1. In DMABRG mode, only synchronous DRAM can be specified. *2. External request 2-channel mode: DREQ0 (corresponds to channel 0) and DREQ1 (corresponds to channel 1) DMABRG mode: DREQ0 to DREQ3 (can be set for all channels) *3.External request 2-channel mode: Transfer requests cannot be accepted from the LCDC, HAC, SSI, and USB. DMABRG mode: Transfer requests can be accepted from all on-chip peripheral modules with the DMA transfer request function. (Note that transfer requests from the LCDC, HAC, SSI, and USB can only be accepted in channel 0.)
Rev. 1.0, 02/03, page 361 of 1294
Figure 11.1 shows a block diagram of the DMAC.
DMAC module Count control DMAC register unit*1
Register control On-chip peripheral module*2
Peripheral bus
Activation control
DREQn*3
Transfer request priority control
DACKn*3 DRAKn*3
Transfer request acceptance control
DMABRG
Bus interface
32-byte data buffer Bus state controller Legend:
1. This unit has the following 55 registers.
DMAOR SAR 0 to 7 DAR 0 to 7 DMATCR 0 to 7 CHCR 0 to 7 DMARSRA DMARSRB DMAPCR DMABRGCR DMAATXSAR 0 and 1 DMAARXDAR 0 and 1 DMAATXTCR 0 and 1 DMAARXTCR 0 and 1 DMAACR0 and 1 DMAATXTCNT 0 and 1 DMAARXTCNT 0 and 1 DMAUSAR DMAUDAR DMAURWSZ DMAUCR DMARCR
External address/on-chip peripheral module address External bus
2. The following 14 on-chip peripheral modules can output DMA transfer requests.
SCIF 0 to 2 HSPI SIM MMCIF ADC : Serial communication interface 0 to 2 : Serial peripheral interface : Smartcard interface : Multimedia card interface : A/D converter
: DMA operation register : DMA source address registers 0 to 7 : DMA destination address registers 0 to 7 : DMA transfer count registers 0 to 7 : DMA channel control registers 0 to 7 : DMA request resource selection register A : DMA request resource selection register B : DMA pin control register : DMA BRG control register : DMA audio source address registers 0 and 1 : DMA audio destination address registers 0 and 1 : DMA audio transmit transfer count registers 0 and 1 : DMA audio receive transfer count registers 0 and 1 : DMA audio control registers 0 and 1 : DMA audio transmit transfer counters 0 and 1 : DMA audio receive transfer counters 0 and 1 : DMA USB source address registers 0 to 7 : DMA USB destination address register : DMA USB R/W size register : DMA USB control register : DMA request control register
The following registers are valid only in DMABRG mode.
The following modules can output DMA transfer requests to the DMABRG.
LCDC HAC 0 and 1 SSI 0 and 1 USB : LCD controller : Hitachi audio codec interface 0 and 1 : Serial sound interface 0 and 1 : USB host
3. n = 0 to 3
Figure 11.1 DMAC Block Diagram
Rev. 1.0, 02/03, page 362 of 1294
DMAC internal bus
Figure 11.2 shows a block diagram of the DMABRG. For data transfer in DMABRG mode between synchronous DRAM and the LCDC, HAC, SSI, or USB, the DMABRG performs a high-speed data transfer via the DMABRG internal FIFO (32-bit 16-stage) using DMAC channel 0. The DMABRG transfers a maximum of 32-byte data in a single transfer.
DMAC On-chip peripheral module HAC(0)/ SSI(0) HAC(1)/ SSI(1) HAC(0)/SSI(0) bridge bus HAC(1)/SSI(1) bridge bus DMABRG 16-stage 32-bit FIFO 16-stage 32-bit FIFO 16-stage 32-bit FIFO 16-stage 32-bit FIFO 16-stage 32-bit FIFO 16-stage 32-bit FIFO DMABRGCR DMAATXSAR0 DMAARXDAR0 DMAATXTCR0 DMAARXTCR0 16-stage 32-bit FIFO DMAACR0 DMAATXTCNT0 DMAARXTCNT0 DMAUSAR DMAUDAR DMAACR1 DMAATXTCNT1 DMAARXTCNT1 DMAURWSZ DMAUCR Bus state controller DMAATXSAR1 Transfer request priority control
USB
USB bridge bus
DMAATXTCR1 DMAARXTCR1
LCDC
LCDC bridge bus
External bus
Synchronous DRAM
Figure 11.2 DMABRG Block Diagram
Rev. 1.0, 02/03, page 363 of 1294
Peripheral bus
DMAARXDAR1
11.2
Input/Output Pins
Table 11.1 shows the DMAC pin configuration. Table 11.1 Pin Configuration
Pin Name DMA transfer request DREQ acceptance confirmation DREQ0 DRAK0 Abbreviation I/O DREQ0 DRAK0 Input Output Function DMA transfer request input from external device Notifies acceptance of DMA transfer request and start of execution to external device which has output 1 DREQ0* Strobe output to external device which has output DREQ0, regarding DMA transfer request DMA transfer request input from external device Notifies acceptance of DMA transfer request and start of execution to external device which has output 1 DREQ1* Strobe output to external device which has output DREQ1, regarding DMA transfer request DMA transfer request input from external device Notifies acceptance of DMA transfer request to external device which has 2 output DREQ2* Strobe output to external device which has output DREQ2, regarding DMA 2 transfer request* DMA transfer request input from external device
DMA transfer end notification DMA transfer request DREQ acceptance confirmation
DACK0
DACK0
Output
DREQ1 DRAK1
DREQ1 DRAK1
Input Output
DMA transfer end notification DMA transfer request DREQ acceptance confirmation DMA transfer end notification DMA transfer request
DACK1
DACK1
Output
DREQ2 DRAK2/
DREQ2 DRAK2
Input Output
DACK2
DACK2
Output
DREQ3
DREQ3
Input
Rev. 1.0, 02/03, page 364 of 1294
Pin Name DREQ acceptance confirmation DMA transfer end notification DRAK3/
Abbreviation I/O DRAK3 Output
Function Notifies acceptance of DMA transfer request to external device which has 3 output DREQ3* Strobe output to external device which has output DREQ3, regarding DMA 3 transfer request*
DACK3
DACK3
Output
Notes: *1. Pin DRAK0 or DRAK1 indicates the start of execution only in external request 2channel mode. *2. Pins DRAK2 and DACK2 are multiplexed. *3. Pins DRAK3 and DACK3 are multiplexed.
11.3
Register Descriptions
The DMAC has the following registers. For details of register addresses and register states during each process, see section 32, List of Registers. For details regarding the DMA pin control register (DMAPCR), see section 24.2.34, DMA Pin Control Register (DMAPCR), in section 24, Pin Function Controller (PFC). In later descriptions, channel numbers are not explicitly mentioned. Table 11.2 Register Configuration (1)
Sync Ch. 0 Register Name DMA source address register 0 Abbrev. SAR0 R/W R/W R/W P4 Address H'FFA0 0000 H'FFA0 0004 H'FFA0 0008 H'FFA0 000C H'FFA0 0010 H'FFA0 0014 H'FFA0 0018 H'FFA0 001C H'FFA0 0020 H'FFA0 0024 H'FFA0 0028 H'FFA0 002C Area 7 Address H'1FA0 0000 H'1FA0 0004 H'1FA0 0008 H'1FA0 000C H'1FA0 0010 H'1FA0 0014 H'1FA0 0018 H'1FA0 001C H'1FA0 0020 H'1FA0 0024 H'1FA0 0028 H'1FA0 002C Size 32 32 32 32 32 32 32 32 32 32 32 32 Clock Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck
DMA destination address register 0 DAR0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1
DMATCR0 R/W CHCR0 SAR1 R/W R/W R/W
DMA destination address register 1 DAR1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2
DMATCR1 R/W CHCR1 SAR2 R/W R/W R/W
DMA destination address register 2 DAR2 DMA transfer count register 2 DMA channel control register 2
DMATCR2 R/W CHCR2 R/W
Rev. 1.0, 02/03, page 365 of 1294
Sync Ch. 3 Register Name DMA source address register 3 Abbrev. SAR3 R/W R/W R/W P4 Address H'FFA0 0030 H'FFA0 0034 H'FFA0 0038 H'FFA0 003C H'FFA0 0050 H'FFA0 0054 H'FFA0 0058 H'FFA0 005C H'FFA0 0060 H'FFA0 0064 H'FFA0 0068 H'FFA0 006C H'FFA0 0070 H'FFA0 0074 H'FFA0 0078 H'FFA0 007C H'FFA0 0080 H'FFA0 0084 H'FFA0 0088 H'FFA0 008C H'FFA0 0040 H'FE09 0000 Area 7 Address H'1FA0 0030 H'1FA0 0034 H'1FA0 0038 H'1FA0 003C H'1FA0 0050 H'1FA0 0054 H'1FA0 0058 H'1FA0 005C H'1FA0 0060 H'1FA0 0064 H'1FA0 0068 H'1FA0 006C H'1FA0 0070 H'1FA0 0074 H'1FA0 0078 H'1FA0 007C H'1FA0 0080 H'1FA0 0084 H'1FA0 0088 H'1FA0 008C H'1FA0 0040 H'1E09 0000 Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Clock Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Pck
DMA destination address register 3 DAR3 DMA transfer count register 3 DMA channel control register 3 4 DMA source address register 4
DMATCR3 R/W CHCR3 SAR4 R/W R/W R/W
DMA destination address register 4 DAR4 DMA transfer count register 4 DMA channel control register 4 5 DMA source address register 5
DMATCR4 R/W CHCR4 SAR5 R/W R/W R/W
DMA destination address register 5 DAR5 DMA transfer count register 5 DMA channel control register 5 6 DMA source address register 6
DMATCR5 R/W CHCR5 SAR6 R/W R/W R/W
DMA destination address register 6 DAR6 DMA transfer count register 6 DMA channel control register 6 7 DMA source address register 7
DMATCR6 R/W CHCR6 SAR7 R/W R/W R/W
DMA destination address register 7 DAR7 DMA transfer count register 7 DMA channel control register 7
Common DMA operation register
DMATCR7 R/W CHCR7 DMAOR R/W R/W
DMA request resource selection register A DMA request resource selection register B DMA request control register
DMABRG DMA BRG control register
DMARSRA R/W
DMARSRB R/W
H'FE09 0004
H'1E09 0004
32
Pck
DMARCR DMABRG CR
R/W R/W
H'FE09 0008 H'FE3C 0000
H'1E09 0008 H'1E3C 0000
32 32
Pck Pck
DMA audio source address register 0 DMA audio destination address register 0 DMA audio transmit transfer count register 0
DMAATX SAR0 DMAARX DAR0 DMAATX TCR0
R/W
H'FE3C 0040
H'1E3C 0040
32
Pck
R/W
H'FE3C 0044
H'1E3C 0044
32
Pck
R/W
H'FE3C 0048
H'1E3C 0048
32
Pck
Rev. 1.0, 02/03, page 366 of 1294
Sync Ch. Register Name Abbrev. DMAARX TCR0 DMAACR0 R/W DMAATX TCNT0 DMAARX TCNT0 DMAATX SAR1 DMAARX DAR1 DMAATX TCR1 DMAARX TCR1 DMAACR1 R/W DMAATX TCNT1 DMAARX TCNT1 DMAUSAR R/W DMAUDAR R/W
DMAURWSZ R/W
R/W R/W
P4 Address H'FE3C 004C
Area 7 Address H'1E3C 004C
Size 32
Clock Pck
DMABRG DMA audio receive transfer count
register 0 DMA audio control register 0 DMA audio transmit transfer counter 0 DMA audio receive transfer counter 0 DMA audio source address register 1 DMA audio destination address register 1 DMA audio transmit transfer count register 1 DMA audio receive transfer count register 1 DMA audio control register 1 DMA audio transmit transfer counter 1 DMA audio receive transfer counter 1 DAM USB source address register DMA USB destination register DMA USB R/W size register DMA USB control register
H'FE3C 0050 H'FE3C 0054
H'1E3C 0050 H'1E3C 0054
32 32
Pck Pck
R
R
H'FE3C 0058
H'1E3C 0058
32
Pck
R/W
H'FE3C 0060
H'1E3C 0060
32
Pck
R/W
H'FE3C 0064
H'1E3C 0064
32
Pck
R/W
H'FE3C 0068
H'1E3C 0068
32
Pck
R/W
H'FE3C 006C
H'1E3C 006C
32
Pck
H'FE3C 0070 H'FE3C 0074
H'1E3C 0070 H'1E3C 0074
32 32
Pck Pck
R
R
H'FE3C 0078
H'1E3C 0078
32
Pck
H'FE3C 0080 H'FE3C 0084 H'FE3C 0088 H'FE3C 008C
H'1E3C 0080 H'1E3C 0084 H'1E3C 0088 H'1E3C 008C
32 32 32 32
Pck Pck Pck Pck
DMAUCR
R/W
Rev. 1.0, 02/03, page 367 of 1294
Table 11.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Ch. 0 Register Name DMA source address register 0 Abbrev. SAR0 H-UDI Undefined Undefined Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Sleep by Sleep Instruction/ by Standby by Software/ Each
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
DMA destination address register 0 DAR0 DMA transfer count register 0 DMA channel control register 0 1 DMA source address register 1
DMATCR0 Undefined CHCR0 SAR1 H'0000 0000 Undefined Undefined
DMA destination address register 1 DAR1 DMA transfer count register 1 DMA channel control register 1 2 DMA source address register 2
DMATCR1 Undefined CHCR1 SAR2 H'0000 0000 Undefined Undefined
DMA destination address register 2 DAR2 DMA transfer count register 2 DMA channel control register 2 3 DMA source address register 3
DMATCR2 Undefined CHCR2 SAR3 H'0000 0000 Undefined Undefined
DMA destination address register 3 DAR3 DMA transfer count register 3 DMA channel control register 3 4 DMA source address register 4
DMATCR3 Undefined CHCR3 SAR4 H'0000 0000 Undefined Undefined
DMA destination address register 4 DAR4 DMA transfer count register 4 DMA channel control register 4 5 DMA source address register 5
DMATCR4 Undefined CHCR4 SAR5 H'0000 0000 Undefined Undefined
DMA destination address register 5 DAR5 DMA transfer count register 5 DMA channel control register 5 6 DMA source address register 6
DMATCR5 Undefined CHCR5 SAR6 H'0000 0000 Undefined Undefined
DMA destination address register 6 DAR6 DMA transfer count register 6 DMA channel control register 6
DMATCR6 Undefined CHCR6 H'0000 0000
Rev. 1.0, 02/03, page 368 of 1294
Power-on Reset by RESET Pin/WDT/ Ch. 7 Register Name DMA source address register 7 Abbrev. SAR7 H-UDI Undefined Undefined
Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 Sleep by Sleep Instruction/ by
Standby by Software/ Each
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained
DMA destination address register 7 DAR7 DMA transfer count register 7 DMA channel control register 7
Common DMA operation register
DMATCR7 Undefined CHCR7 DMAOR H'0000 0000 H'0000 0000
DMA request resource selection register A DMA request resource selection register B DMA request control register
DMABRG DMA BRG control register
DMARSRA H'0000 0000
DMARSRB H'0000 0000
H'0000 0000
Retained
Retained
DMARCR DMABRG CR
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
Retained Retained
Retained Retained
DMA audio source address register 0 DMA audio destination address register 0 DMA audio transmit transfer count register 0 DMA audio receive transfer count register 0 DMA audio control register 0 DMA audio transmit transfer counter 0 DMA audio receive transfer counter 0 DMA audio source address register 1 DMA audio destination address register 1 DMA audio transmit transfer count register 1 DMA audio receive transfer count register 1
DMAATX SAR0 DMAARX DAR0 DMAATX TCR0 DMAARX TCR0
Undefined
Undefined
Retained
Retained
Undefined
Undefined
Retained
Retained
Undefined
Undefined
Retained
Retained
Undefined
Undefined
Retained
Retained
DMAACR0 H'0000 0000 DMAATX TCNT0 DMAARX TCNT0 DMAATX SAR1 DMAARX DAR1 DMAATX TCR1 DMAARX TCR1 Undefined Undefined Undefined Undefined Undefined Undefined
H'0000 0000 Undefined
Retained Retained
Retained Retained
Undefined
Retained
Retained
Undefined
Retained
Retained
Undefined
Retained
Retained
Undefined
Retained
Retained
Undefined
Retained
Retained
Rev. 1.0, 02/03, page 369 of 1294
Power-on Reset by RESET Pin/WDT/ Ch. Register Name Abbrev. H-UDI
Manual Reset by RESET Pin/WDT/ Multiple Exception H'0000 0000 Undefined Sleep by Sleep Instruction/ by
Standby by Software/ Each
Deep Sleep Hardware Module Retained Retained * Retained Retained
DMABRG DMA audio control register 1
DMAACR1 H'0000 0000 DMAATX TCNT1 DMAARX TCNT1 DMAUSAR H'0000 0000 DMAUDAR H'0000 0000
DMAURWSZ H'0000 0000
DMA audio transmit transfer counter 1 DMA audio receive transfer counter 1 DAM USB source address register DMA USB destination register DMA USB R/W size register DMA USB control register
Undefined
Undefined
Undefined
Retained
Retained
H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained
Retained Retained Retained Retained
DMAUCR
H'0000 0000
Note:
*
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin.
Rev. 1.0, 02/03, page 370 of 1294
11.3.1
DMA Source Address Register (SAR)
SAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer. During a DMA transfer, they indicate the next source address. In single address mode, the SAR value is ignored when an external device with DACK has been specified as the transfer source. A 16-bit, 32-bit, 64-bit, or 32-byte boundary address should be specified when performing a 16-bit, 32-bit, 64-bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R/W 15 R/W 30 R/W 14 R/W 29 R/W 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W
Notes: 1. Make the setting of bit 0, bits 1 and 0, bits 2 to 0, or bits 4 to 0 to match the boundary when specifying a 16-bit, 32-bit, 64-bit, or 32-byte boundary address, respectively. If an address is specified regardless of the boundary, an address error will be detected and the DMAC stops operation on all channels (AE (address error flag) bit in DMAOR is 1). The DMAC will also detect an address error and stop operation if an area 7 address is specified for a data transfer via the external bus or if an address for an on-chip peripheral module that does not exist is specified. 2. An external address is 29 bits long. Bits 31 to 29 in both SAR and DAR are not used in DMA transfers. Therefore, clearing bits 31 to 29 to 0 in both SAR and DAR is recommended. 11.3.2 DMA Destination Address Register (DAR)
DAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer. During a DMA transfer, they indicate the next destination address. In single address mode, the DAR value is ignored when a device with DACK has been specified as the transfer destination. A 16-bit, 32-bit, 64-bit, or 32-byte boundary address should be specified when performing a 16-bit, 32-bit, 64-bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will be detected and the DMAC will halt.
Rev. 1.0, 02/03, page 371 of 1294
Bit: Initial value: R/W: Bit: Initial value: R/W:
31 R/W 15 R/W
30 R/W 14 R/W
29 R/W 13 R/W
28 R/W 12 R/W
27 R/W 11 R/W
26 R/W 10 R/W
25 R/W 9 R/W
24 R/W 8 R/W
23 R/W 7 R/W
22 R/W 6 R/W
21 R/W 5 R/W
20 R/W 4 R/W
19 R/W 3 R/W
18 R/W 2 R/W
17 R/W 1 R/W
16 R/W 0 R/W
Notes: 1. Make the setting of bit 0, bits 1 and 0, bits 2 to 0, or bits 4 to 0 to match the boundary when specifying a 16-bit, 32-bit, 64-bit, or 32-byte boundary address, respectively. If an address is specified regardless of the boundary, an address error will be detected and the DMAC stops operation on all channels (AE (address error flag) bit in DMAOR is 1). The DMAC will also detect an address error and stop operation if an area 7 address is specified for a data transfer via the external bus or if an address for an on-chip peripheral module that does not exist is specified. 2. An external address is 29 bits long. Bits 31 to 29 in both SAR and DAR are not used in DMA transfers. Therefore, clearing bits 31 to 29 to 0 in both SAR and DAR is recommended. 11.3.3 DMA Transfer Count Register (DMATCR)
DMATCR is a 32-bit readable/writable register that specifies the transfer count for the corresponding channel. Specifying H'0000 0001 gives a transfer count of 1, while H'0000 0000 gives the maximum setting (16,777,216). During DMAC operation, the remaining number of transfers is shown. The upper eight bits of DMATCR are reserved. They are always read as 0 and the write value should always be 0.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W
0 R 15 R/W
0 R 14 R/W
0 R 13 R/W
0 R 12 R/W
0 R 11 R/W
0 R 10 R/W
0 R 9 R/W
0 R 8 R/W
Rev. 1.0, 02/03, page 372 of 1294
11.3.4
DMA Channel Control Register (CHCR)
CHCR is a 32-bit readable/writable register that specifies the operating mode and transfer method for each channel. Bits 31 to 28 and 27 to 24 are only valid when the source and destination addresses are in the CS5 or CS6 space and the relevant space has been specified as a PCMCIA interface space. In other cases, these bits should be cleared to 0.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 DTC 0 R/W 8 RS0 0 R/W 23 0 R 7 TM 0 R/W 22 0 R 6 TS2 0 R/W 21 0 R 5 TS1 0 R/W 20 0 R 4 19 DS 0 R/W 3 18 RL 0 R/W 2 IE 0 R/W 17 AM 0 R/W 1 TE 0 R/W 16 AL 0 R/W 0 DE 0 R/W
SSA2 SSA1 SSA0 0 R/W 15 DM1 0 R/W 0 R/W 14 DM0 0 R/W 0 R/W 13 SM1 0 R/W
STC DSA2 DSA1 DSA0 0 R/W 12 SM0 0 R/W 0 R/W 11 RS3 0 R/W 0 R/W 10 RS2 0 R/W 0 R/W 9 RS1 0 R/W
TS0 CHSET 0 R/W 0 R/W
Bit 31 30 29
Bit Name SSA2 SSA1 SSA0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Source Address Space Attribute Specification These bits specify the space attribute for the source address when accessing a PCMCIA interface area. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. 000: Reserved in PCMCIA access 001: Dynamic bus sizing I/O space 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space
Rev. 1.0, 02/03, page 373 of 1294
Bit 28
Bit Name STC
Initial Value 0
R/W R/W
Description Source Address Wait Control Select Specifies the CS5 or CS6 space wait cycle control for the source address when accessing a PCMCIA interface area. 0: CS5 space wait cycle selection Settings of bits A5W2 to A5W0 in WCR2 and bits A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in PCR are selected 1: CS6 space wait cycle selection Settings of bits A6W2 to A6W0 in WCR2 and bits A6PCW1 and A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0 in PCR are selected
27 26 25
DSA2 DSA1 DSA0
0 0 0
R/W R/W R/W
Destination Address Space Attribute Specification These bits specify the space attribute for the destination address when accessing a PCMCIA interface area. These bits are only valid in the case of page mapping to PCMCIA connected to areas 5 and 6. 000: Reserved in PCMCIA access 001: Dynamic bus sizing I/O space 010: 8-bit I/O space 011: 16-bit I/O space 100: 8-bit common memory space 101: 16-bit common memory space 110: 8-bit attribute memory space 111: 16-bit attribute memory space
Rev. 1.0, 02/03, page 374 of 1294
Bit 24
Bit Name DTC
Initial Value R/W 0 R/W
Description Destination Address Wait Control Select Specifies the CS5 or CS6 space wait cycle control for the destination address when accessing a PCMCIA interface area. 0: CS5 space wait cycle selection Settings of bits A5W2 to A5W0 in WCR2 and bits A5PCW1 and A5PCW0, A5TED2 to A5TED0, and A5TEH2 to A5TEH0 in PCR are selected 1: CS6 space wait cycle selection Settings of bits A6W2 to A6W0 in WCR2 and bits A6PCW1 and A6PCW0, A6TED2 to A6TED0, and A6TEH2 to A6TEH0 in PCR are selected
23 to 20
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
19
DS
0
R/W
DREQ Select Specifies either low level detection or falling edge detection as the sampling method for the DREQ pin. In external request 2-channel mode, this bit is valid only in CHCR0 and CHCR1. In DMABRG mode, this bit is valid in CHCR0 to CHCR7 and each of bits DS3 to DS0 in DMARCR should be specified to the same as this bit. 0: Low level detection 1: Falling edge detection Level detection burst mode when TM = 1 and DS = 0 Edge detection burst mode when TM = 1 and DS = 1
18
RL
0
R/W
Request Check Level Selects whether the DRAK signal that notifies an external device of the acceptance of DREQ is an active-high or active-low output. In external request 2-channel mode, this bit is valid only in CHCR0 and CHCR1. In DMABRG mode, this bit is invalid and the DRAK polarity is specified by bits RL3 to RL0 in DMARCR. 0: DRAK is an active-high output 1: DRAK is an active-low output
Rev. 1.0, 02/03, page 375 of 1294
Bit 17
Bit Name AM
Initial Value 0
R/W R/W
Description Acknowledge Mode In dual address mode, selects whether DACK is output in the data read cycle or write cycle. In single address mode, DACK is always output regardless of the setting of this bit. In external request 2-channel mode, this bit is valid only in CHCR0 and CHCR1. In DMABRG mode, this bit is valid in CHCR0 to CHCR7. 0: DACK is output in read cycles 1: DACK is output in write cycles
16
AL
0
R/W
Acknowledge Level Specifies the DACK signal as active-high or active-low. In external request 2-channel mode, this bit is valid only in CHCR0 and CHCR1. In DMABRG mode, this bit is invalid and the DACK polarity is specified by bits AL3 to AL0 in DMARCR. 0: Active-high output 1: Active-low output
15 14
DM1 DM0
0 0
R/W R/W
Destination Address Mode 1 and 0 These bits specify incrementing/decrementing of the DMA transfer destination address. The specification of these bits is ignored when data is transferred from external memory to an external device in single address mode. 00: Destination address fixed 01: Destination address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-byte burst transfer) 10: Destination address decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer, -8 in 64-bit transfer, -32 in 32-byte burst transfer) 11: Setting prohibited
Rev. 1.0, 02/03, page 376 of 1294
Bit 13 12
Bit Name SM1 SM0
Initial Value 0 0
R/W R/W R/W
Description Source Address Mode 1 and 0 These bits specify incrementing/decrementing of the DMA transfer source address. The specification of these bits is ignored when data is transferred from an external device to external memory in single address mode. 00: Source address fixed 01: Source address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-byte burst transfer) 10: Source address decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer, -8 in 64-bit transfer, -32 in 32-byte burst transfer) 11: Setting prohibited
11 10 9 8
RS3 RS2 RS1 RS0
0 0 0 0
R/W R/W R/W R/W
Resource Select 3 to 0 These bits specify the transfer request source. Setting bits DMS1 and DMS0 in DMAOR specifies the transfer request source in external request 2channel mode or DMABRG mode. See tables 11.3 and 11.4 for settings of bits RS3 to RS0. Transmit Mode Specifies the bus mode for transfer. 0: Cycle steal mode 1: Burst mode
7
TM
0
R/W
6 5 4
TS2 TS1 TS0
0 0 0
R/W R/W R/W
Transmit Size 2 to 0 These bits specify the transfer data size (access size). 000: Quadword size (64-bit) specification 001: Byte size (8-bit) specification 010: Word size (16-bit) specification 011: Longword size (32-bit) specification 100: 32-byte block transfer specification Other than above: Setting prohibited
Rev. 1.0, 02/03, page 377 of 1294
Bit 3
Bit Name CHSET
Initial Value 0
R/W R/W
Description Channel Setting When setting CHCR, 1 should always be written to this bit. However, this bit is always read as 0. Note: In DMABRG mode, writing 1 to this bit clears the internal state of the acceptance unit for external and DMABRG requests in the corresponding channel. This bit is invalid in external request 2-channel mode.
2
IE
0
R/W
Interrupt Enable When this bit is set to 1, an interrupt request (DMTE) is generated after completing a number of data transfers specified in DMATCR (when TE = 1). When a DMABRG request DMA transfer is executed in DMABRG mode, the DMTE0 signal cannot be generated. 0: Interrupt request is not generated after completing a number of transfers specified in DMATCR 1: Interrupt request is generated after completing a number of transfers specified in DMATCR
1
TE
0
R/W
Transfer End This bit is set to 1 after the number of transfers specified in DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated. If data transfer ends before this bit is set to 1 due to an NMI interrupt, address error, or clearing of the DE bit or the DME bit in DMAOR, etc., this bit is not set to 1. When this bit is 1, the transfer enabled state is not entered even if the DE bit is set to 1. 0: Number of transfers specified in DMATCR not completed [Clearing condition] When 0 is written to TE after reading TE = 1 1: Number of transfers specified in DMATCR completed
Rev. 1.0, 02/03, page 378 of 1294
Bit 0
Bit Name DE
Initial Value 0
R/W R/W
Description DMAC Enable Enables operation of the corresponding channel. When auto-request is specified by bits RS3 to RS0, setting this bit to 1 starts the transfer. When an external request or on-chip peripheral module request is generated, a transfer request after setting this bit to 1 starts the transfer. During a transfer, clearing this bit to 0 stops the transfer. The transfer enable state is not entered by setting this bit to 1 if the TE bit is set to 1, the DME bit in DMAOR is cleared to 0, or the NMIF or AE bit in DMAOR is set to 1. 0: Operation of corresponding channel is disabled 1: Operation of corresponding channel is enabled
Rev. 1.0, 02/03, page 379 of 1294
Table 11.3 External Request 2-Channel Mode (DMS[1:0] in DMAOR = 00)
Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 0 0 0 Bit 8: RS0 0 Description External request* Dual address mode External address space external address space Setting prohibited External request*
1 1
1 1 0
Single address mode External address space external device 1 External request*
1
Single address mode External device external address space 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Auto-request (external address space external address space) Auto-request (external address space on-chip peripheral module) Auto-request (on-chip peripheral module external address space) On-chip peripheral module request* * External address space on-chip peripheral module Setting prohibited Setting prohibited Setting prohibited Setting prohibited TMU channel 2 (input capture interrupt) External address space external address space TMU channel 2 (input capture interrupt) External address space on-chip peripheral module TMU channel 2 (input capture interrupt) On-chip peripheral module external address space On-chip peripheral module request* * On-chip peripheral module external address space
23 23
Notes: *1. External request specifications are valid only for channels 0 and 1. DREQ0 and DREQ1 correspond to channel 0 and channel 1, respectively. *2. DMARSRA and DMARSRB values should be specified in addition to setting this bit. *3. On-chip peripheral modules except for LCDC, HAC, SSI, USB, and TMU
Rev. 1.0, 02/03, page 380 of 1294
Table 11.4 DMABRG Mode (DMS[1:0] in DMAOR = 11)
Bit 11: Bit 10: Bit 9: RS3 RS2 RS1 0 0 0 Bit 8: RS0 0 Description External request* * Dual address mode External address space external address space Setting prohibited External request* * , DMABRG request* * 4 Single address mode* , External address space external device External request* * , DMABRG request* * 4 Single address mode* , External device external address space Auto-request (external address space external address space) Auto-request (external address space on-chip peripheral module) Auto-request (on-chip peripheral module external address space) On-chip peripheral module request* * External address space on-chip peripheral module Setting prohibited Setting prohibited Setting prohibited Setting prohibited TMU channel 2 (input capture interrupt) External address space external address space TMU channel 2 (input capture interrupt) External address space on-chip peripheral module TMU channel 2 (input capture interrupt) On-chip peripheral module external address space On-chip peripheral module request* * On-chip peripheral module external address space
25 25 12 23 12 23 12
1 1 0
1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Notes: *1. External requests can be accepted in all channels. DREQ0 to DREQ3 can be used. Note that the DREQ pin number and channel number do not match. *2. DMARSRA and DMARSRB values should be specified in addition to setting this bit. *3. DMABRG requests can only be accepted in channel 0. A DMABRG request is a transfer request from the LCDC, HAC(0)/(1), SSI(0)/(1), and USB. This bit is automatically set when a DMABRG request is issued. *4. Only single address mode for synchronous DRAM can be set. *5. On-chip peripheral modules except for LCDC, HAC, SSI, USB, and TMU.
Rev. 1.0, 02/03, page 381 of 1294
11.3.5
DMA Operation Register (DMAOR)
DMAOR is a 32-bit readable/writable register that specifies the DMA mode and channel priorities, and enables or disables DMA transfer.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 30 0 R 14 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 PR1 0 R/W 24 0 R 8 PR0 0 R/W 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 AE 0 R/W 17 0 R 1 NMIF 0 R/W 16 0 R 0 DME 0 R/W
DMS1 DMS0 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 16 --
15 14
DMS1 DMS0
0 0
R/W R/W
DMA Mode Select 1 and 0 These bits select the transfer mode. Set these bits when DMAOR.DME = 0. 00: External-request 2-channel mode 11: DMABRG mode* Other than above: Setting prohibited Note: * Make this setting when CHCR0 has its initial value of H'0000 0000.
13 to 10 --
All 0
R
Reserved These bits are always read as 0.The write value should always be 0.
9 8
PR1 PR0
0 0
R/W R/W
Priority Mode 1 and 0 These bits determine the order of priority for channel execution when transfer requests are made for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 01: CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 10: CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 11: Round robin mode
Rev. 1.0, 02/03, page 382 of 1294
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2
AE
0
R/W
Address Error Flag Indicates that an address error has occurred during DMA transfer. Setting this bit during data transfer will suspend transfers on all channels and generate an interrupt request (DMAE). The CPU cannot write 1 to this bit. Write AE=0 after reading AE=1 to clear this bit. 0: No address error, DMA transfer enabled [Clearing condition] When 0 is written to the AE bit after reading AE = 1 1: Address error, DMA transfer disabled [Setting condition] When an address error is caused by the DMAC
1
NMIF
0
R/W
NMI Flag Indicates that NMI has been input. It is possible to set this bit regardless of whether or not the DMAC is operating. Setting this bit during data transfer will suspend transfers on all channels. The CPU cannot write 1 to this bit. Write NMIF=0 after reading NMIF=1 to clear this bit. 0: No NMI input, DMA transfer enabled [Clearing condition] When 0 is written to NMIF after reading NMIF = 1 1: NMI input, DMA transfer disabled [Setting condition] When an NMI interrupt is generated
0
DME
0
R/W
DMAC Master Enable Enables activation of the entire DMAC. Setting the DME bit and the DE bit in CHCR for the corresponding channel to 1 will enable that channel for translfer. Clearing this bit during data transfer will suspend transfers on all channels. Even if the DME bit has been set to 1, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or when the NMIF or AE bit in DMAOR is 1. 0: Operation disabled on all channels 1: Operation enabled on all channels
Rev. 1.0, 02/03, page 383 of 1294
11.3.6
DMA Request Resource Selection Registers (DMARSRA, DMARSRB)
DMARSRA and DMARSRB are 32-bit readable/writable registers that specify the transfer request source for each channel, together with the RS bits in each CHCRn. When the channel is not used, or DMA transfer initiated by an auto-request or a TMU input capture interrupt is used, the DMARSR corresponding to that channel should be set to H'00. To resume a DMA transfer that has stopped due to an address error (AE = 1 in DMAOR) or an NMI interrupt (NMIF = 1 in DMAOR), re-specify this register value, regardless of whether or not a transfer request source to any channel has been changed, before specifying AE = 0 in DMAOR or NMIF = 0 in DMAOR. * DMARSRA
31 CH0 WEN Initial value: 0 R/W: R/W 15 CH2 WEN Initial value: 0 R/W: R/W Bit: Bit: 30 CH0 RS6 0 R/W 14 CH2 RS6 0 R/W 29 CH0 RS5 0 R/W 13 CH2 RS5 0 R/W 28 CH0 RS4 0 R/W 12 CH2 RS4 0 R/W 27 CH0 RS3 0 R/W 11 CH2 RS3 0 R/W 26 CH0 RS2 0 R/W 10 CH2 RS2 0 R/W 25 CH0 RS1 0 R/W 9 CH2 RS1 0 R/W 24 CH0 RS0 0 R/W 8 CH2 RS0 0 R/W 23 CH1 WEN 0 R/W 7 CH3 WEN 0 R/W 22 CH1 RS6 0 R/W 6 CH3 RS6 0 R/W 21 CH1 RS5 0 R/W 5 CH3 RS5 0 R/W 20 CH1 RS4 0 R/W 4 CH3 RS4 0 R/W 19 CH1 RS3 0 R/W 3 CH3 RS3 0 R/W 18 CH1 RS2 0 R/W 2 CH3 RS2 0 R/W 17 CH1 RS1 0 R/W 1 CH3 RS1 0 R/W 16 CH1 RS0 0 R/W 0 CH3 RS0 0 R/W
* DMARSRB
31 CH4 WEN Initial value: 0 R/W: R/W 15 CH6 WEN Initial value: 0 R/W: R/W Bit: Bit: 30 CH4 RS6 0 R/W 14 CH6 RS6 0 R/W 29 CH4 RS5 0 R/W 13 CH6 RS5 0 R/W 28 CH4 RS4 0 R/W 12 CH6 RS4 0 R/W 27 CH4 RS3 0 R/W 11 CH6 RS3 0 R/W 26 CH4 RS2 0 R/W 10 CH6 RS2 0 R/W 25 CH4 RS1 0 R/W 9 CH6 RS1 0 R/W 24 CH4 RS0 0 R/W 8 CH6 RS0 0 R/W 23 CH5 WEN 0 R/W 7 CH7 WEN 0 R/W 22 CH5 RS6 0 R/W 6 CH7 RS6 0 R/W 21 CH5 RS5 0 R/W 5 CH7 RS5 0 R/W 20 CH5 RS4 0 R/W 4 CH7 RS4 0 R/W 19 CH5 RS3 0 R/W 3 CH7 RS3 0 R/W 18 CH5 RS2 0 R/W 2 CH7 RS2 0 R/W 17 CH5 RS1 0 R/W 1 CH7 RS1 0 R/W 16 CH5 RS0 0 R/W 0 CH7 RS0 0 R/W
Rev. 1.0, 02/03, page 384 of 1294
DMARSRA
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name CH0WEN CH0RS6 CH0RS5 CH0RS4 CH0RS3 CH0RS2 CH0RS1 CH0RS0 CH1WEN CH1RS6 CH1RS5 CH1RS4 CH1RS3 CH1RS2 CH1RS1 CH1RS0 CH2WEN CH2RS6 CH2RS5 CH2RS4 CH2RS3 CH2RS2 CH2RS1 CH2RS0 CH3WEN CH3RS6 CH3RS5 CH3RS4 CH3RS3 CH3RS2 CH3RS1 CH3RS0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits CHnRS6 to CHnRS0 specify transfer request sources to each channel. DMARSRA bits are allocated to channels 0 to 3. When writing to the CHnRS6 to CHnRS0 bits for each channel, simultaneously write 1 to the CHnWEN bit. Clearing the CHnWEN bit to 0 will not change the values in the CHnRS6 to CHnRS0 bits of each channel and retain the previous values. The CHnWEN bit is writeenabled, but it does not retain the written value and is always read as 0. CHnRS[6:0] H'00: Unused or auto-request, TMU input capture interrupt H'10: DREQ0*1 H'11: DREQ1*1 H'12: DREQ2*1 H'13: DREQ3*1 H'14: DMABRG (LCDC reception, USB transmission/reception, HAC transmission/reception, SSI transmission/reception)*1*2 H'20: SCIF(0) Transmit-data-empty H'21: SCIF(0) Receive-data-full H'22: SCIF(1) Transmit-data-empty H'23: SCIF(1) Receive-data-full H'24: SCIF(2) Transmit-data-empty H'25: SCIF(2) Receive-data-full H'26: HSPI Transmit data H'27: HSPI Receive data H'28: SIM Transmit data empty H'29: SIM Receive-data-full H'2B: MMC FIFO ready H'2C: ADC AD conversion end data transfer H'2D: Setting prohibited H'2E: Setting prohibited H'7F: --*3 Other than above: Setting prohibited
Rev. 1.0, 02/03, page 385 of 1294
Notes: *1. This setting is valid only in DMABRG mode. In external request 2-channel mode, DREQ0 or DREQ1 can be accepted (only for channel 0 or 1) regardless of this setting. *2. The DMABRG settings are valid only in channel 0. In DMABRG mode, when selecting channel 0 transfer request source in DMABRG, don't change the channel 0 transfer request source after the DMABRG DMA transfer starts. Normal operation is not guaranteed if the transfer request source is changed. *3. Use this setting when the DMA transfer is complete with the request in DMAC retained (DMARCR.REXn = 1). See (3) Notes on Ending Transfer in section 11.4.6, Ending DMA Transfer.
Note: n = 0 to 3
Rev. 1.0, 02/03, page 386 of 1294
DMARSRB
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name CH4WEN CH4RS6 CH4RS5 CH4RS4 CH4RS3 CH4RS2 CH4RS1 CH4RS0 CH5WEN CH5RS6 CH5RS5 CH5RS4 CH5RS3 CH5RS2 CH5RS1 CH5RS0 CH6WEN CH6RS6 CH6RS5 CH6RS4 CH6RS3 CH6RS2 CH6RS1 CH6RS0 CH7WEN CH7RS6 CH7RS5 CH7RS4 CH7RS3 CH7RS2 CH7RS1 CH7RS0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/(W) R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/W R/W R/W R/(W) R/(W) R/W R/(W) R/W R/W R/W R/W R/W R/W R/W R/(W) R/W R/W R/W R/W R/(W) R/(W) R/W Description CHnRS6 to CHnRS0 specify transfer request sources to each channel. DMARSRB bits are allocated to channels 0 to 3. When writing to the CHnRS6 to CHnRS0 bits for each channel, simultaneously write 1 to the CHnWEN bit. Clearing the CHnWEN bit to 0 will not change the values in the CHnRS6 to CHnRS0 bits of each channel and retain the previous values. The CHnWEN bit is write-enabled, but it does not retain the written value and is always read as 0. CHnRS[6:0] H'00: Unused or auto-request, TMU input capture interrupt H'10: DREQ0*1 H'11: DREQ1*1 H'12: DREQ2*1 H'13: DREQ3*1 H'20: SCIF(0) Transmit-data-empty H'21: SCIF(0) Receive-data-full H'22: SCIF(1) Transmit-data-empty H'23: SCIF(1) Receive-data-full H'24: SCIF(2) Transmit-data-empty H'25: SCIF(2) Receive-data-full H'26: HSPI Transmit data H'27: HSPI Receive data H'28: SIM Transmit data empty H'29: SIM Receive-data-full H'2B: MMC FIFO ready H'2C: ADC AD conversion end data transfer H'2D: Setting prohibited H'2E: Setting prohibited H'7F: --*2 Other than above: Setting prohibited Note:*1 This setting is valid only in DMABRG mode. It is invalid in external request 2-channel mode (channels 2 to 7 cannot accept external requests). *2 Use this setting when the DMA transfer is complete with the request in DMAC retained (DMARCR.REXn = 1). See (3) Notes on Ending Transfer in section 11.4.6, Ending DMA Transfer.
Note: n = 4 to 7
Rev. 1.0, 02/03, page 387 of 1294
11.3.7
DMA Pin Control Register (DMAPCR)
Refer to section 24.2.34, DMA Pin Control Register (DMAPCR), in section 24, Pin Function Controller (PFC) for details regarding DMAPCR. 11.3.8 DMA Request Control Register (DMARCR)
DMARCR is a 32-bit readable/writable register that switches between DRAK2 and DACK2 and between DRAK3 and DACK3 in DMABRG mode, selects the interrupt level for DRAK and DACK, detects DREQ0 to DREQ3, and specifies the acceptance priority of requests from DREQ0 to DREQ3 and DMABRG. The numbers 0, 1, 2, and 3 in the bit names of DS, RL and AL correspond to DREQ0, DREQ1, DREQ2, and DREQ3 (channel numbers are not indicated). This DMARCR setting is invalid in external request 2-channel mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 R/A2 0 R/W 6 DS1 0 R/W 21 0 R 5 RL1 0 R/W 20 0 R 4 AL1 0 R/W 19 0 R 3 0 R 18 0 R 2 DS0 0 R/W 17 16
REX7 REX6 REX5 REX4 REX3 REX2 REX1 REX0 R/A3 0 R 15 0 R 0 R 14 DS3 0 R/W 0 R 13 RL3 0 R/W 0 R 12 AL3 0 R/W 0 R 11 0 R 0 R 10 DS2 0 R/W 0 R 9 RL2 0 R/W 0 R 8 AL2 0 R/W 0 R/W 7 0 R
RPR1 RPR0 0 R/W 1 RL0 0 R/W 0 R/W 0 AL0 0 R/W
Bit 31
Bit Name REX7
Initial Value 0
R/W R
Description Channel 7 Request Reception* *
47
0: Channel 7 does not accept a transfer request 1: Channel 7 accepts a transfer request 30 REX6 0 R Channel 6 Request Reception* *
47
0: Channel 6 does not accept a transfer request 1: Channel 6 accepts a transfer request 29 REX5 0 R Channel 5 Request Reception* *
47
0: Channel 5 does not accept a transfer request 1: Channel 5 accepts a transfer request 28 REX4 0 R Channel 4 Request Reception* *
47
0: Channel 4 does not accept a transfer request 1: Channel 4 accepts a transfer request 27 REX3 0 R Channel 3 Request Reception* *
47
0: Channel 3 does not accept a transfer request 1: Channel 3 accepts a transfer request
Rev. 1.0, 02/03, page 388 of 1294
Bit 26
Bit Name REX2
Initial Value 0
R/W R
Description Channel 2 Request Reception* *
47
0: Channel 2 does not accept a transfer request 1: Channel 2 accepts a transfer request 25 REX1 0 R Channel 1 request Reception* * *
457
0: Channel 1 does not accept a transfer request 1: Channel 1 accepts a transfer request 24 REX0 0 R Channel 0 Request Reception* * *
467
0: Channel 0 does not accept a transfer request 1: Channel 0 accepts a transfer request 23 R/A3 0 R/W DRAK3/DACK3 Select 0: Outputs DRAK3 1: Outputs DACK3 22 R/A2 0 R/W DRAK2/DACK2 Select 0: Outputs DRAK2 1: Outputs DACK2 21 to 18 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17 16 RPR1 RPR0 0 0 R/W R/W Request Priority 1 and 0 Select the request priority order. 00: DMABRG* > DREQ0 > DREQ1 > DREQ2 > DREQ3 01: DMABRG* > DREQ0 > DREQ1 > DREQ2 > DREQ3 10: DREQ0 > DMABRG* > DREQ1 > DREQ2 > DREQ3 11: Round-robin (Initial setting: DMABRG* > DREQ0 > DREQ1 > DREQ2 > DREQ3) Note: Setting RPR[1:0] = 01 will make all channels disabled to receive a transfer request from on-chip peripheral modules except for LCDC, HAC, SSI, USB, and TMU or an external request (DREQ), after having accepted a DMABRG request (REX0 = 1). When the DMABRG request is cleared (REX0 = 0), transfer requests are acceptable.
1 1 1 1
Rev. 1.0, 02/03, page 389 of 1294
Bit 15
Bit Name --
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
14
DS3
0
R/W
DREQ3 Select 0: Low-level detection 1: Falling-edge detection
13
RL3
0
R/W
Request Check Level 3 0: DRAK3 high-active 1: DRAK3 low-active
12
AL3
0
R/W
Acknowledge Level 3 0: DACK3 high-active 1: DACK3 low-active
11
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10
DS2
0
R/W
DREQ2 Select 0: Low-level detection 1: Falling-edge detection
9
RL2
0
R/W
Request Check Level 2 0: DRAK2 high-active 1: DRAK2 low-active
8
AL2
0
R/W
Acknowledge Level 2 0: DACK2 high-active 1: DACK2 low-active
7
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6
DS1
0
R/W
DREQ1 Select 0: Low-level detection 1: Falling-edge detection
5
RL1
0
R/W
Request Check Level 1 0: DRAK1 high-active 1: DRAK1 low-active
Rev. 1.0, 02/03, page 390 of 1294
Bit 4
Bit Name AL1
Initial Value 0
R/W R/W
Description Acknowledge Level 1 0: DACK1 high-active 1: DACK1 low-active
3
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2
DS0
0
R/W
DREQ0 Select 0: Low-level detection 1: Falling-edge detection
1
RL0
0
R/W
Request Check Level 0 0: DRAK0 high-active 1: DRAK0 low-active
0
AL0
0
R/W
Acknowledge Level 0 0: DACK0 high-active 1: DACK0 low-active
Notes: *1. Internal priority of the DMABRG: LCDC > A-B-C-D* * > USB *2. A = HAC(0)/SSI(0) transmission, B = HAC(0)/SSI(0) reception, C = HAC(1)/SSI(1) transmission, and D = HAC(1)/SSI(1) reception *3. A-B-C-D is the round-robin method. *4. This bit is not set to 1 when TMU channel 2 (input capture interrupt) or auto-request has been accepted. *5. This bit is not set to 1 when DREQ1 is accepted in external request 2-channel mode. *6. This bit is not set to 1 when DREQ0 is accepted in external request 2-channel mode. *7. An address error (DMAOR.AE=1) or an NMI interrupt (DMAOR.NMIF=1) may result in REXn=1 although the corresponding channel accepts a DMA transfer request. For details of an address error or NMI interrupt, refer to (2) Ending Transfer Simultaneously on All Channels, in section 11.4.6 Ending DMA Transfer.
23
11.3.9
DMA BRG Control Register (DMABRGCR)
DMABRGCR is a 32-bit readable/writable register that has enable bits which generate HAC, SSI, and USB interrupts, and flags which indicate interrupts that have been generated.
Bit: 31 A1R XHE 0 R/W 15 Initial value: R/W: 0 R 30 A1R XEE 0 R/W 14 0 R 29 A1T XHE 0 R/W 13 0 R 28 A1T XEE 0 R/W 12 0 R 27 A0R XHE 0 R/W 11 0 R 26 A0R XEE 0 R/W 10 0 R 25 A0T XHE 0 R/W 9 UAE 0 R/W 24 A0T XEE 0 R/W 8 UTE 0 R/W 23 A1R XHF 0 R/W 7 0 R 22 A1R XEF 0 R/W 6 0 R 21 A1T XHF 0 R/W 5 0 R 20 A1T XEF 0 R/W 4 0 R 19 A0R XHF 0 R/W 3 0 R 18 A0R XEF 0 R/W 2 0 R 17 A0T XHF 0 R/W 1 UAF 0 R/W 16 A0T XEF 0 R/W 0 UTF 0 R/W
Initial value: R/W: Bit:
Rev. 1.0, 02/03, page 391 of 1294
Bit 31
Bit Name A1RXHE
Initial Value 0
R/W R/W
Description HAC(1)/SSI(1) Receive Side Half Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
30
A1RXEE
0
R/W
HAC(1)/SSI(1) Receive Side All Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
29
A1TXHE
0
R/W
HAC(1)/SSI(1) Transmit Side Half Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
28
A1TXEE
0
R/W
HAC(1)/SSI(1) Transmit Side All Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
27
A0RXHE
0
R/W
HAC(0)/SSI(0) Receive Side Half Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
26
A0RXEE
0
R/W
HAC(0)/SSI(0) Receive Side All Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
25
A0TXHE
0
R/W
HAC(0)/SSI(0) Transmit Side Half Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
24
A0TXEE
0
R/W
HAC(0)/SSI(0) Transmit Side All Data Transfer End Interrupt Enable 0: Disabled 1: Enabled
Rev. 1.0, 02/03, page 392 of 1294
Bit 23
Bit Name A1RXHF
Initial Value 0
R/W R/W
Description HAC(1)/SSI(1) Receive Side Half Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A1RXHF after reading A1RXHF = 1 1: An interrupt has occurred.
22
A1RXEF
0
R/W
HAC(1)/SSI(1) Receive Side All Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A1RXEF after reading A1RXEF = 1 1: An interrupt has occurred.
21
A1TXHF
0
R/W
HAC(1)/SSI(1) Transmit Side Half Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A1TXHF after reading A1TXHF = 1 1: An interrupt has occurred.
20
A1TXEF
0
R/W
HAC(1)/SSI(1) Transmit Side All Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A1TXEF after reading A1TXEF = 1 1: An interrupt has occurred.
19
A0RXHF
0
R/W
HAC(0)/SSI(0) Receive Side Half Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A0RXHF after reading A0RXHF = 1 1: An interrupt has occurred.
Rev. 1.0, 02/03, page 393 of 1294
Bit 18
Bit Name A0RXEF
Initial Value 0
R/W R/W
Description HAC(0)/SSI(0) Receive Side All Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A0RXEF after reading A0RXEF = 1 1: An interrupt has occurred.
17
A0TXHF
0
R/W
HAC(0)/SSI(0) Transmit Side Half Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A0TXHF after reading A0TXHF = 1 1: An interrupt has occurred.
16
A0TXEF
0
R/W
HAC(0)/SSI(0) Transmit Side All Data Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to A0TXEF after reading A0TXEF = 1 1: An interrupt has occurred.
15 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9
UAE
0
R/W
USB Address Error Interrupt Enable 0: Disabled 1: Enabled
8
UTE
0
R/W
USB Transfer End Interrupt Enable 0: Disabled 1: Enabled
7 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
UAF
0
R/W
USB Address Error Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to UAF after reading UAF = 1 1: An interrupt has occurred.
Rev. 1.0, 02/03, page 394 of 1294
Bit 0
Bit Name UTF
Initial Value 0
R/W R/W
Description USB Transfer End Interrupt Flag 0: An interrupt has not occurred. [Clearing condition] When 0 is written to UTF after reading UTF = 1 1: An interrupt has occurred.
11.3.10 DMA Audio Source Address Register (DMAATXSAR) DMAATXSAR is a 32-bit readable/writable register that specifies the source start address of a DMA transfer from synchronous DRAM to the HAC or SSI codec. DMAATXSAR0 corresponds to HAC(0) or SSI(0) and DMAATXSAR1 corresponds to HAC(1) or SSI(1). During a DMA transfer, the register value is not modified.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R/W 30 R 14 R/W 29 R 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R 16 R/W 0 R
11.3.11 DMA Audio Destination Address Register (DMAARXDAR) DMAARXDAR is a 32-bit readable/writable register that specifies the destination start address of a DMA transfer from the HAC or SSI codec to synchronous DRAM. DMAARXDAR0 corresponds to HAC(0) or SSI(0) and DMAARXDAR1 corresponds to HAC(1) or SSI(1). During a DMA transfer, the register value is not modified.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R/W 30 R 14 R/W 29 R 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R 16 R/W 0 R
Rev. 1.0, 02/03, page 395 of 1294
11.3.12 DMA Audio Transmit Transfer Count Register (DMAATXTCR) DMAATXTCR is a 32-bit readable/writable register that specifies the number of bytes of source audio data transferred in a DMA transfer to the HAC or SSI codec. DMAATXTCR0 corresponds to HAC(0) or SSI(0) and DMAATXTCR1 corresponds to HAC(1) or SSI(1). During a DMA transfer the register value is not modified. This register should be set from H'0000 0004 to H'03FF FFFC (bits 31 to 26, 1, and 0 are fixed at 0). Do not set H'0000 0000. Normal operation is not guaranteed when H'0000 0000 is set.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R/W 30 R 14 R/W 29 R 13 R/W 28 R 12 R/W 27 R 11 R/W 26 R 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R 16 R/W 0 R
11.3.13 DMA Audio Receive Transfer Count Register (DMAARXTCR) DMAARXTCR is a 32-bit readable/writable register that specifies the number of bytes of received audio data transferred in a DMA transfer from the HAC or SSI codec. DMAARXTCR0 corresponds to HAC(0) or SSI(0) and DMAARXTCR1 corresponds to HAC(1) or SSI(1). During a DMA transfer the register value is not modified. This register should be set from H'0000 0004 to H'03FF FFFC (bits 31 to 26, 1, and 0 are fixed at 0). Do not set H'0000 0000. Normal operation is not guaranteed when H'0000 0000 is set.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R/W 30 R 14 R/W 29 R 13 R/W 28 R 12 R/W 27 R 11 R/W 26 R 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R 16 R/W 0 R
Rev. 1.0, 02/03, page 396 of 1294
11.3.14 DMA Audio Control Register (DMAACR) DMAACR is a 32-bit readable/writable register that specifies the DMA operating mode of the HAC or SSI codec. DMAACR0 corresponds to HAC(0) or SSI(0) and DMAACR1 corresponds to HAC(1) or SSI(1).
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 24 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 RAR 0 R/W 2 TAR 0 R/W 17 RDS 0 R/W 1 TDS 0 R/W 16 RDE 0 R/W 0 TDE 0 R/W
RAM1 RAM0 0 R/W 9 0 R/W 8
TAM1 TAM0 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 26
25 24
RAM1 RAM0
0 0
R/W R/W
Receive Data Alignment Setting These bits specify the data alignment method for writing receive data to an external memory. For details of the data alignment method for the receive slot data and external bus, see table 11.5 (1). 00: Alignment control is not performed 01: Longword data is transferred as four byte-data 10: Longword data is transferred as two word-data 11: Setting prohibited
23 to 19
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
18
RAR
0
R/W
DMA Auto Reload Setting Specifies the use or unuse of auto address reload to continue a DMA transfer when the number of bytes in the receive DMA transfer reaches the number of transfer bytes specified by DMAARXTCRn. 0: Address of receive DMA not auto reloaded 1: Address of receive DMA auto reloaded
Rev. 1.0, 02/03, page 397 of 1294
Bit 17
Bit Name RDS
Initial Value 0
R/W R/W
Description HAC/SSI Receive DMA Termination Setting this bit to 1 forcibly terminates the receive DMA transfer. * When writing 0: Write operation is ignored 1: Receive DMA transfer is forcibly terminated * When reading 0: Transfer is completed 1: Transfer is being performed
16
RDE
0
R/W
HAC/SSI Receive DMA Transfer Activation Control Controls the receive DMA transfer activation. Write operation is ignored during transfer. To reactivate a receive DMA transfer, read this bit as 0 and then write 1 to it. * When writing 0: Write operation is ignored 1: Receive DMA transfer is activated * When reading 0: Transfer is completed 1: Transfer is being performed
15 to 10
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
9 8
TAM1 TAM0
0 0
R/W R/W
Transmit Data Alignment Setting These bits specify the data alignment method for reading transmit data from an external memory. For details of the data alignment method for the transmit slot data and external bus, see Table 11.5 (2). 00: Alignment control is not performed 01: A longword is transferred as four bytes 10: A longword is transferred as two words 11: Setting prohibited
7 to 3
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 398 of 1294
Bit 2
Bit Name TAR
Initial Value 0
R/W R/W
Description HAC/SSI Transmit DMA Auto Reload Setting Specifies the use or unuse of auto address reload to continue a DMA transfer when the number of bytes in the transmit DMA transfer reaches the number of transfer bytes specified by DMAARXTCRn. 0: Address of transmit DMA not auto reloaded 1: Address of transmit DMA auto reloaded
1
TDS
0
R/W
HAC/SSI Transmit DMA Termination Setting this bit to 1 forcibly terminates a transmit DMA transfer. * When writing 0: Write operation is ignored 1: Transmit DMA transfer is forcibly terminated * When reading 0: Transfer is completed 1: Transfer is being performed
0
TDE
0
R/W
HAC/SSI Transmit DMA Transfer Activation Control Controls the transmit DMA transfer activation. Write operation is ignored during transfer. To reactivate a transmit DMA transfer, read this bit as 0 and then write 1 to it. * When writing 0: Write operation is ignored 1: Transmit DMA transfer is activated * When reading 0: Transfer is completed 1: Transfer is being performed
Rev. 1.0, 02/03, page 399 of 1294
Table 11.5 (1)
Data Alignment for Receive Slot Data and External Bus
Data Bus Slot Data 31 to 23 to 15 to 7 to 24 16 8 0 D3 D3 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0
RAM1 RAM0 Size 0 0 1 0 1 0 No Alignment (One longword) Longword (four bytes) Longword (two words)
31 to 23 to 15 to 7 to 24 16 8 0 D3 D0 D1 D2 D1 D0 D1 D2 D3 D0 D3 D2
Table 11.5 (2)
Data Alignment for Transmit Slot Data and External Bus
Data Bus Slot Data 31 to 23 to 15 to 7 to 24 16 8 0 D3 D0 D1 D2 D1 D0 D1 D2 D3 D0 D3 D2
TAM1 TAM0 Size 0 0 1 0 1 0 No Alignment (One longword) Longword (four bytes) Longword (two words)
31 to 23 to 15 to 7 to 24 16 8 0 D3 D3 D3 D2 D2 D2 D1 D1 D1 D0 D0 D0
11.3.15 DMA Audio Transmit Transfer Counter (DMAATXTCNT) DMAATXTCNT is a 32-bit read-only register that indicates the number of bytes remaining to be transferred in the transfer bytes specified by DMAATXTCR. This register is write-prohibited. DMAATXTCNT0 corresponds to HAC(0) or SSI(0) and DMAATXTCNT1 corresponds to HAC(1) or SSI(1). Writing 1 to the TDE bit in DMAACR sets the DMAATXTCR value in this register. On forced termination, the number of transfer bytes remaining at that time is indicated.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 23 R 7 R 22 R 6 R 21 R 5 R 20 R 4 R 19 R 3 R 18 R 2 R 17 R 1 R 16 R 0 R
11.3.16 DMA Audio Receive Transfer Counter (DMAARXTCNT) DMAARXTCNT is a 32-bit read-only register that indicates the number of remaining bytes of transfer bytes specified by DMAARXTCR. This register is write-prohibited. DMAARXTCNT0 corresponds to HAC(0) or SSI(0) and DMAARXTCNT1 corresponds to HAC(1) or SSI(1).
Rev. 1.0, 02/03, page 400 of 1294
Writing 1 to the RDE bit in DMAACR sets the DMAARXTCR value in this register. On forced termination, the number of transfer bytes remaining at that time is indicated.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 23 R 7 R 22 R 6 R 21 R 5 R 20 R 4 R 19 R 3 R 18 R 2 R 17 R 1 R 16 R 0 R
11.3.17 DMA USB Source Address Register (DMAUSAR) DMAUSAR is a 32-bit readable/writable register that specifies the source address of a DMA transfer. The settings in this register are valid only for the DMA transfer between the USB internal shared memory (hereafter referred to as shared memory) and synchronous DRAM. During USB DMA transfer, the register value can be read but cannot be modified. The address should be specified as a 32-bit boundary. Specify this register value as a synchronous DRAM address for a DMA transfer from synchronous DRAM to the shared memory, and as a shared memory address for a transfer from the shared memory to synchronous DRAM. In the case of a transfer from the shared memory to synchronous DRAM, the address should be within the transfer source, that is the shared memory area (H'FE34 1000 to H'FE34 2FFC). When an address outside of this area is specified, the DMAC detects a USB address error and terminates the USB DMA transfer.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
11.3.18 DMA USB Destination Address Register (DMAUDAR) DMAUDAR is a 32-bit readable/writable register that specifies the destination address of a DMA transfer. The settings in this register are valid only for the DMA transfer between the shared memory and synchronous DRAM. During USB DMA transfer, the register value can be read but cannot be modified. The address should be specified as a 32-bit boundary.
Rev. 1.0, 02/03, page 401 of 1294
Specify this register value as a shared memory address for a DMA transfer from synchronous DRAM to the shared memory, and as a synchronous DRAM address for a transfer from the shared memory to synchronous DRAM. In the case of a transfer from synchronous DRAM to the shared memory, the address should be within the transfer destination, that is the shared memory area (H'FE34 1000 to H'FE34 2FFC). When an address outside of this area is specified, the DMAC detects a USB address error and terminates the USB DMA transfer.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R
0 R
11.3.19 DMA USB R/W Size Register (DMAURWSZ) DMAURWSZ is a 32-bit readable/writable register that specifies the transfer direction and data size. During USB DMA transfer, the register value can be read but cannot be modified.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 SZ8 0 R/W 23 0 R 7 SZ7 0 R/W 22 0 R 6 SZ6 0 R/W 21 0 R 5 SZ5 0 R/W 20 0 R 4 SZ4 0 R/W 19 0 R 3 SZ3 0 R/W 18 0 R 2 SZ2 0 R/W 17 0 R 1 SZ1 0 R/W 16 RW 0 R/W 0 SZ0 0 R/W
SZ12 SZ11 0 R/W 0 R/W
SZ10 SZ9 0 R/W 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 17
16
RW
0
R/W
Transfer Direction 0: Specifies a DMA transfer from synchronous DRAM to the shared memory 1: Specifies a DMA transfer from the shared memory to synchronous DRAM
15 to 13
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 402 of 1294
Bit 12 to 0
Bit Name SZ12 to SZ0
Initial Value All 0
R/W R/W
Description Transfer Data Size Specifies the number of bytes to be transferred in a USB DMA transfer. Up to 8191 bytes can be specified. Setting these bits as as H'0000 (SZ[12:0]=H'0000) will not perform transfer, but setting the START bit in DMAUCR to 1 sets the UTF bit in DMABRGCR to 1.
11.3.20 DMA USB Control Register (DMAUCR) DMAUCR is a 32-bit readable/writable register that specifies the start of USB DMA transfer between the shared memory and synchronous DRAM, and the data alignment mode. The setting of the data alignment mode is also valid for accesses to the USB from the CPU. For details of the data alignment mode, see section 11.6.13, USB Endian Conversion Function.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 16
CVRT1CVRT0 0 R/W 1 START 0 R/W 0 R/W 0 0 R
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 18
17 16
CVRT1 CVRT0
0 0
R/W R/W
Alignment Mode 00: Alignment is not performed 01: Byte boundary mode 10: Longword/word boundary mode 11: Setting prohibited
15 to 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 403 of 1294
Bit 1
Bit Name START
Initial Value 0
R/W R/W
Description DMA Transfer Start Setting this bit to 1 starts a USB DMA transfer. When the USB DMA transfer is completed, this bit is automatically cleared to 0. * When writing 0: Invalid 1: Starts a USB DMA transfer * When reading 0: USB DMA transfer is stopped 1: USB DMA transfer is being performed
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
11.4
Operation
When a DMA transfer request is issued, the DMAC starts the transfer according to the predetermined channel priority order. It ends the transfer when the transfer end conditions are satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. There are two modes for DMA transfer: single address mode and dual address mode. Either burst mode or cycle steal mode can be selected as the bus mode. 11.4.1 DMA Transfer Procedure
After the desired transfer conditions have been set in SAR, DAR, DMATCR, CHCR, DMAOR, DMARCR, DMARSRA, and DMARSRB, the DMAC transfers data according to the following procedure: 1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0). 2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one transfer unit of data (determined by bits TS2 to TS0). In auto-request mode, the transfer begins automatically when the DE and DME bits are set to 1. The DMATCR value is decremented by 1 for each transfer. The actual transfer flow depends on the address mode and bus mode. 3. When the specified number of transfers have been completed (when the DMATCR value reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, the DMAC sends a DMTE interrupt request to the CPU. 4. If a DMAC address error or NMI interrupt occurs, the DMAC suspends the transfer. It also suspends the transfer when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event of an address error, the DMAC issues a forced DMAE interrupt request to the CPU. For details of DMA transfer end and suspension, see section 11.4.6, Ending DMA Transfer.
Rev. 1.0, 02/03, page 404 of 1294
Figure 11.3 shows a flowchart of the DMA transfer procedure.
Start
Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR, DMARCR, DMARSRA, DMARSRB)
DE, DME = 1? Yes Illegal address check (reflected in AE bit)
No
*4
NMIF, AE, TE = 0? Yes Transfer request issued? *1 Yes Transfer (1 transfer unit) DMATCR - 1 DMATCR Update SAR, DAR
No
*2 No *3 Bus mode, transfer request mode, DREQ detection method
DMATCR = 0? Yes
No
NMIF or AE = 1 or DE = 0 or DME = 0? Yes Transfer suspended
No
DMTE interrupt request (when IE = 1)
NMIF or AE = 1 or DE = 0 or DME = 0? Yes End of transfer
No
Normal end
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and DME bits are set to 1. 2. DREQ level detection (external request) in burst mode, or cycle steal mode. 3. DREQ edge detection (external request) in burst mode, or auto-request mode in burst mode. 4. An illegal address is detected by comparing bits TS2-TS0 in CHCRn with SARn and DARn.
Figure 11.3 DMAC Transfer Flowchart
Rev. 1.0, 02/03, page 405 of 1294
11.4.2
DMA Transfer Requests
DMA transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. The transfer request mode is selected by bits RS3 to RS0 in CHCR0 to CHCR7 and settings of DMARSRA and DMARSRB. (1) Auto-Request Mode The DMAC can automatically generate a transfer request signal internally in Auto-Request Mode when receiving no transfer request signal from an external source, as in a memory-tomemory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer. Setting the DE bit in CHCR of the channel to be used and the DME bit in DMAOR to 1 starts the transfer. However, the TE bit in CHCR of the channel to be used and the NMIF and AE bits in DMAOR must all be 0. (2) External Request Mode In this mode, the DMAC performs a transfer in response to a transfer request signal (DREQ) from an external device. Select one of the modes shown in table 11.6 according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0), transfer starts when DREQ is input. The DS bits in CHCR0 to CHCR7 and bits DS3 to DS0 in DMARCR are used to select either falling edge detection or low level detection of the DREQ signal (level detection with DS = 0, edge detection with DS = 1). The source of the transfer request does not have to be the data transfer source or destination. Table 11.6 Selecting External Request Mode with RS Bits
RS3 0 RS2 0 RS1 0 RS0 0 Address Mode Dual address mode Transfer Source External memory, memory-mapped external device, or on-chip peripheral module External memory or memory-mapped external device External device with DACK Transfer Destination External memory, memory-mapped external device, or on-chip peripheral module External device with DACK External memory or memory-mapped external device
1
0
Single address mode Single address mode
1
Rev. 1.0, 02/03, page 406 of 1294
* External request acceptance conditions 1. When at least either of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF, DMAOR.AE, and CHCR.TE are all 0, the DMAC will hold an input external request (DREQ: edge detection) until DMA transfer is either executed or canceled. Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, NMIF = 0, AE = 0, TE = 0). If an external request (DREQ) is input while DMA transfer is enabled (DME = 1, DE = 1, NMIF = 0, AE = 0, TE = 0), DMA transfer is started. An external request (DREQ) will be ignored if it is input with TE = 1, NMIF = 1, or AE = 1 during a power-on reset or manual reset, in deep sleep mode or standby mode, or while the DMAC is in the module standby state. Write 1 to CHCRn or CHSET or re-specify the channel resource in DMARSRA or DMARSRB before enabling DMAC transfer in order to resume DMA transfer in DMABRG mode. A previously input external request will be canceled by the occurrence of an NMI interrupt (NMIF = 1) or address error (AE = 1), or by a power-on reset or manual reset. In this LSI, it is possible to cancel a previously input external request (DREQ). In external request 2-channel mode, drive the DREQ pin high after clearing the DS bit in CHCRn to 0. In DMABRG mode, set the CHSET bit in CHCRn to 1.
2. 3.
4.
* Usage Notes The DMAC detects an external request (DREQ) at a low level or falling edge. Ensure to hold the external request (DREQ) signal high when there is no DMA transfer request from an external device after a power-on reset or manual reset. When DMA transfer is resumed, check whether a DMA transfer request is being held. (3) On-Chip Peripheral Module Request Mode In this mode, the DMAC performs a transfer in response to a transfer request signal (interrupt request signal) from an on-chip peripheral module. To output a transfer request from an on-chip peripheral module, set the DMA transfer request enable bit for that module.
Rev. 1.0, 02/03, page 407 of 1294
11.4.3
Channel Priorities
Receiveing simultaneous transfer requests on two or more channels, the DMAC selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. The mode is selected with priority bits PR1 and PR0 in DMAOR. (1) Fixed Mode In this mode, the relative channel priorities remain fixed. The following priority orders are available in fixed mode: * CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 * CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1 * CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7 Select one of these priority orders by setting the PR1 and PR0 bits in DMAOR. (2) Round Robin Mode In round robin mode, each time the transfer of one transfer unit (byte, word, longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest priority level. This is illustrated in figure 11.4. The order of priority in round robin mode immediately after a reset is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If no transfer request is accepted for any channel during DMA transfer, the priority order becomes CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7.
Rev. 1.0, 02/03, page 408 of 1294
Transfer on channel 0 Channel 0 is given the lowest priority.
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order after transfer CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH0
Transfer on channel 1 When channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously.
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order after transfer
CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH0 > CH1
Transfer on channel 2 When channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. If there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3, 4, 5, 6, 7, and 0 are simultaneously shifted down.
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Figure 11.4 Round Robin Mode
CH3 > CH4 > CH5 > CH6 > CH7 > CH0 > CH1 > CH2 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Priority order after transfer
Priority after transfer due to issuance of a transfer request for channel 1 only.
CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH0 > CH1
Transfer on channel 7 No change in priority order
Initial priority order
Rev. 1.0, 02/03, page 409 of 1294
Priority order after transfer CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
Figure 11.5 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 generates a transfer request during a transfer on channel 0. The operation of the DMAC in this case is as follows. 1. Transfer requests are issued simultaneously for channels 0 and 3. 2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. The channel 3 transfer is started. 8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority.
Rev. 1.0, 02/03, page 410 of 1294
Transfer request 1. Issued for channels 0 and 3 3. Issued for channel 1
Channel waiting
DMAC operation
Channel priority order
3
2. Start of channel 0 transfer
0>1>2>3>4>5>6>7
Change of priority order 1, 3 4. End of channel 0 transfer 1>2>3>4>5>6>7>0
5. Start of channel 1 transfer
3
6. End of channel 1 transfer
Change of priority order
2>3>4>5>6>7>0>1
7. Start of channel 3 transfer None Change of priority order 8. End of channel 3 transfer 4>5>6>7>0>1>2>3
Figure 11.5 Example of Changes in Priority Order in Round Robin Mode 11.4.4 Types of DMA Transfer
The DMAC supports the types of transfer shown in table 11.7. It can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. The actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode.
Rev. 1.0, 02/03, page 411 of 1294
Table 11.7 Supported DMA Transfers
Transfer Destination Transfer Source External device with DACK External memory Memory-mapped external device On-chip peripheral module External Device with DACK Not available Single address mode Single address mode Not available External Memory Single address mode Dual address mode Dual address mode Dual address mode Memory-Mapped External Device Single address mode On-Chip Peripheral Module Not available
Dual address mode Dual address mode Dual address mode Dual address mode Dual address mode Not available
(1) Address Modes * Single Address Mode In single address mode, both the transfer source and the transfer destination are external; one is accessed by the DACK signal and the other by an address. In this mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the external device strobe signal (DACK) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. Figure 11.6 shows an example of a transfer between external memory and an external device with DACK in which the external device outputs data to the data bus and that data is written to external memory in the same bus cycle.
External address bus This LSI DMAC External memory External data bus
External device with DACK DACK DREQ : Data flow
Figure 11.6 Data Flow in Single Address Mode
Rev. 1.0, 02/03, page 412 of 1294
Two types of transfer are available in single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. Only the external request signal (DREQ) is used in both of these cases. Figure 11.7 shows the transfer timing for single address mode. The access timing depends on the type of external memory. For details, see the descriptions of the memory interfaces in section 10, Bus State Controller (BSC).
CKIO A28-A0 CSn D31-D0 DACK WE Data output from external device with DACK DACK signal to external device with DACK WE signal to external memory space Address output to external memory space
(a) From external device with DACK to external memory space
CKIO A28-A0 CSn D31-D0 RD DACK Data output from external memory space RD signal to external memory space DACK signal to external device with DACK (b) From external memory space to external device with DACK Address output to external memory space
Figure 11.7 DMA Transfer Timing in Single Address Mode * Dual Address Mode Dual address mode is used to access both the transfer source and the transfer destination by address. The transfer source and destination can be either on-chip peripheral module or external address. Even if the operand cache is used in RAM mode, the RAM cannot be set as the transfer source or transfer destination.
Rev. 1.0, 02/03, page 413 of 1294
Since in dual address mode, data corresponding to the size specified by the TS bit in CHCRn is read from the transfer source in the data read cycle and is written to the transfer destination in the data write cycle, it is transferred in two bus cycles. In this process, the transfer data is temporarily stored in the data buffer in the bus state controller (BSC). In a transfer between external memories such as that shown in figure 11.8, data is read from external memory into the BSC's data buffer in the read cycle, then written to the other external memory in the write cycle. Figure 11.9 shows the timing for this operation. The DACK output timing is the same as that of CSn in a read or write cycle specified by the AM bit in CHCRn.
SAR
Memory
Address bus
DMAC DAR
Data bus
Transfer source module Transfer destination module
BSC
Data buffer
Taking the SAR value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the bus state controller (BSC). 1st bus cycle
SAR
Memory
Address bus
DMAC DAR
Data bus
Transfer source module Transfer destination module
BSC
Data buffer
Taking the DAR value as the address, the data stored in the BSC's data buffer is written to the transfer destination module. 2nd bus cycle
Figure 11.8 Operation in Dual Address Mode
Rev. 1.0, 02/03, page 414 of 1294
CKIO
A26-A0 CSn D31-D0 RD WE DACK
Transfer source address
Transfer destination address
Data read cycle (1st cycle)
Data write cycle (2nd cycle)
Transfer from external memory space to external memory space
Figure 11.9 Example of Transfer Timing in Dual Address Mode (2) Bus Modes There are two bus modes: cycle steal mode and burst mode. The bus mode is selected for each channel with the TM bit in CHCR0 to CHCR7. * Cycle Steal Mode In cycle steal mode, the DMAC releases the bus to the CPU at the end of each transfer-unit (8bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer. At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end condition is satisfied. In cycle steal mode, areas for transfer has no limitation by the settings of transfer request source, transfer source, and transfer destination. Figure 11.10 shows an example of DMA transfer timing in cycle steal mode. The following transfer conditions are used in this example: * Dual address mode * DREQ level detection
Rev. 1.0, 02/03, page 415 of 1294
DREQ Bus returned to CPU Bus cycle CPU CPU CPU DMAC Read DMAC Write CPU DMAC Read DMAC Write CPU CPU
Figure 11.10 Example of DMA Transfer in Cycle Steal Mode * Burst Mode In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data continuously until the transfer end condition is satisfied. With DREQ low level detection in external request mode, however, when DREQ is driven high the bus passes to another bus master after the end of the DMAC transfer request that has already been accepted, even if the transfer end condition has not been satisfied. Figure 11.11 shows an example of DMA transfer timing in burst mode. The following transfer conditions are used in this example: * Single address mode * DREQ level detection (DS = 0 and TM = 1 in CHCRn, external request 2-channel mode) Note: Specify DREQ edge detection when performing burst transfer in DMABRG mode. Operations in burst mode with DREQ level detection in DMABRG mode are the same as those in cycle steal mode.
DREQ Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Figure 11.11 Example of DMA Transfer in Burst Mode (3) Relationship between DMA Transfer Type, Request Mode, and Bus Mode Table 11.8 shows the relationship between the type of DMA transfer, the request mode, and the bus mode.
Rev. 1.0, 02/03, page 416 of 1294
Table 11.8 Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Address Mode Single Type of Transfer External device with DACK and external memory External device with DACK and memory-mapped external device Dual External memory and external memory External memory and memory-mapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Legend 32B: B: C: Internal: 32-byte burst transfer Burst Cycle steal Auto-request and on-chip peripheral module request Request Mode External External Internal* , 5 external* Internal* , 5 external* Internal* , 5 external* Internal* Internal*
2 1 1 1
Bus Mode B/C B/C B/C B/C B/C B/C* B/C*
3
Transfer Size (Bits) 8/16/32/64/32B 8/16/32/64/32B 8/16/32/64/32B 8/16/32/64/32B 8/16/32/64/32B 8/16/32/64* 8/16/32/64*
4
2
3
4
External: External request
Notes: *1. External request, auto-request, or on-chip peripheral module request possible. *2. Auto-request or on-chip peripheral module request possible. *3. Only cycle steal mode when the transfer request source is an on-chip peripheral module other than the DMABRG. *4. Access size permitted for the on-chip peripheral module register that is the transfer source or transfer destination. *5. See tables 11.9 (1) and 11.9 (2) for the transfer sources and transfer destinations in DMA transfer by means of an external request.
* External Request 2-Channel Mode Table 11.9 (1) shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request in external request 2channel mode supported by this LSI.
Rev. 1.0, 02/03, page 417 of 1294
Table 11.9 (1)
External Request Transfer Sources and Destinations in External Request 2Channel Mode
Transfer Direction (Settable Memory Interface) Usable Address DMAC Mode Channels Single Single Single Single O Dual Dual O Dual Dual 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1
Transfer Source 1 2 3 4 5 6 7 8 Synchronous DRAM External device with DACK SRAM-type External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, PCMCIA, MPX SRAM-type, MPX, PCMCIA
Transfer Destination External device with DACK Synchronous DRAM External device with DACK SRAM-type SRAM-type, MPX, PCMCIA O Synchronous DRAM SRAM-type, MPX, PCMCIA O SRAM-type, PCMCIA, MPX
Legend: O: DACK output setting in dual address mode transfer Notes: 1. SRAM-type in the table indicates an SRAM, byte control SRAM, or burst ROM. 2. Memory interfaces in which transfer is possible in single address mode are SRAM, byte control SRAM, burst ROM, and synchronous DRAM. 3. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
* DMABRG Mode Table 11.9 (2) shows the memory interfaces that can be specified for the transfer source and transfer destination in DMA transfer initiated by an external request in DMABRG mode supported by this LSI.
Rev. 1.0, 02/03, page 418 of 1294
Table 11.9 (2)
External Request Transfer Sources and Destinations in DMABRG Mode
Transfer Direction (Settable Memory Interface) Usable Address DMAC Mode Channels Single Single O Dual Dual O Dual Dual All All All All All All
Transfer Source 1 2 3 4 5 6 Synchronous DRAM External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA SRAM-type, PCMCIA, MPX SRAM-type, MPX, PCMCIA
Transfer Destination External device with DACK Synchronous DRAM SRAM-type, MPX, PCMCIA O Synchronous DRAM SRAM-type, MPX, PCMCIA O SRAM-type, PCMCIA, MPX
Legend: O: DACK output setting in dual address mode transfer Notes: 1. SRAM-type in the table indicates an SRAM, byte control SRAM, or burst ROM. 2. Memory interface in which transfer is possible in single address mode is synchronous DRAM. 3. When performing dual address mode transfer, make the DACK output setting for the SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
(4) Bus Mode and Channel Priority Order When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set for channel 0. If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for channel 0. Channel execution alternates in the order: channel 1 channel 0 channel 1 channel 0. An example of round robin mode operation is shown in figure 11.12. Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or round robin mode is set for the priority order, the bus is not released to the CPU until channel 1 transfer ends.
Rev. 1.0, 02/03, page 419 of 1294
CPU
DMAC CH1
DMAC CH1
DMAC CH0
DMAC CH1
DMAC CH0
DMAC CH1
DMAC CH1
CPU
CH0 CPU DMAC channel 1 burst mode
CH1
CH0 DMAC channel 1 burst mode CPU
DMAC channel 0 and channel 1 round robin mode
Priority order: Channel 0: Channel 1:
Round robin mode Cycle steal mode Burst mode (edge-sensing)
Figure 11.12 Bus Handling with Two DMAC Channels Operating 11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing
(1) Number of Bus Cycles The number of bus cycles when the DMAC is the bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus master. See section 10, Bus State Controller (BSC), for details. (2) DREQ Pin Sampling Timing In external request mode, the DMAC samples the DREQ pin at the rising edge of a CKIO clock signal. When detecting a DREQ input, the DMAC generates a bus cycle and performs DMA transfer after four CKIO cycles at the earliest. In the case of DREQ falling edge sampling, the DMAC detects a DREQ input after two CKIO cycles (in the case of low-level sampling, one CKIO cycle). The second and subsequent DREQ sampling operations are performed one cycle after the start of the first DMAC transfer bus cycle (in the case of external request 2-channel mode and single address mode). DRAK is output for one cycle only, once each time DREQ is detected, regardless of the transfer mode or DREQ detection method. In the case of burst mode edge detection, DREQ is sampled in the first cycle only, and so DRAK is output in the first cycle only. (3) Operation * Cycle Steal Mode In cycle steal mode, The DREQ sampling timing differs for dual address mode and single address mode, and for level detection and edge detection of DREQ.
Rev. 1.0, 02/03, page 420 of 1294
For example, in figure 11.13 (external request 2-channel mode, cycle steal mode, dual address mode, level detection), DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. In figure 11.15 (external request 2-channel mode, cycle steal mode, dual address mode, edge detection), DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. The second sampling operation begins from the cycle in which the first DMAC transfer read cycle ends. If DREQ is not detected at this time, sampling is executed in every subsequent cycle. For details of the timing for various types of memory access, see section 10, Bus State Controller (BSC). Figure 11.21 shows external request 2-channel mode, cycle steal mode, single address mode, and level detection. In this case, too, transfer is started, at the earliest, four CKIO cycles after the first DREQ sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer bus cycle. Figure 11.23 shows external request 2-channel mode, cycle steal mode, single address mode, and edge detection. In this case, transfer is started, at the earliest, five CKIO cycles after the first DREQ sampling operation. The second sampling begins one cycle after the first assertion of DRAK. In single address mode, the DACK signal is output every DMAC transfer cycle. * Burst Mode, Dual Address Mode, Level Detection DREQ sampling timing in burst mode using dual address mode and level detection is virtually the same as for cycle steal mode. For example, in figure 11.17, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second sampling operation is performed one cycle after the start of the first DMAC transfer write cycle. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. * Burst Mode, Single Address Mode, Level Detection DREQ sampling timing in burst mode using single address mode and level detection is shown in figure 11.20.
Rev. 1.0, 02/03, page 421 of 1294
In the example shown in figure 11.25, DMAC transfer begins, at the earliest, four CKIO cycles after the first sampling operation, and the second sampling operation begins one cycle after the start of the first DMAC transfer bus cycle. In single address mode, the DACK signal is output every DMAC transfer cycle. In figure 11.29, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second sampling operation begins one cycle after DACK is asserted for the first DMAC transfer. * Burst Mode, Dual Address Mode, Edge Detection In burst mode using dual address mode and edge detection, DREQ sampling is performed in the first cycle only. For example, in the case shown in figure 11.19, DMAC transfer begins, at the earliest, five CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In the case of dual address mode transfer initiated by an external request, the DACK signal can be output in either the read cycle or the write cycle of the DMAC transfer according to the specification of the AM bit in CHCR. * Burst Mode, Single Address Mode, Edge Detection In burst mode using single address mode and edge detection, DREQ sampling is performed only in the first cycle. For example, in the case shown in figure 11.27, DMAC transfer begins, at the earliest, five cycles after the first sampling operation. DMAC transfer then continues until the end of the number of data transfers set in DMATCR. DREQ is not sampled during this time, and therefore DRAK is output in the first cycle only. In single address mode, the DACK signal is output every DMAC transfer cycle. (4) Suspension of DMA Transfer with DREQ Level Detection With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single address mode, the external device for which DMA transfer is being executed can determine at the rising edge of CKIO that DRAK has been asserted, and suspend DMA transfer by negating DREQ. In this case, the next DRAK signal is not output.
Rev. 1.0, 02/03, page 422 of 1294
CKIO Bus locked Source address Destination address Source address Destination address Bus locked
A[25:0]
D[31:0]
Read
Write
Read
Write
DREQ0 (level detection) 1st acceptance 2nd acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC
CPU
DMAC
CPU
DACK0
Figure 11.13 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Level Detection), DACK (Read Cycle) DREQ
Rev. 1.0, 02/03, page 423 of 1294
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Destination address Source address Destination address Bus locked
A[25:0]
Rev. 1.0, 02/03, page 424 of 1294
Read Write Read Write
D[31:0]
DREQ0 (Level detection) 2nd acceptance
1st acceptance
DREQ1
DRAK0
Bus cycle
CPU DMAC
CPU
DMAC
CPU
Figure 11.14 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Bus/DREQ (Level Detection), DACK (Read Cycle) DREQ
DACK0
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Source address Destination address Destination address Bus locked Source address
A[25:0]
D[31:0]
Read
Write
Read
Write
Read
DREQ0 (Edge detection) 2nd acceptance
1st acceptance
3rd acceptance
4th acceptance
DREQ1
DRAK0
Bus cycle
CPU
DMAC
CPU
DMAC
CPU
DMAC
DACK0
Figure 11.15 Dual Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) DREQ
Rev. 1.0, 02/03, page 425 of 1294
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Destination address Source address Destination address Bus locked Source address
A[25:0]
Rev. 1.0, 02/03, page 426 of 1294
Read Write Read Write
D[31:0]
Read
DREQ0 (edge detection) 2nd acceptance
1st acceptance
3rd acceptance
4th acceptance
DREQ1
DRAK0
Bus cycle CPU
DMAC
CPU
DMAC
CPU
DMAC
Figure 11.16 Dual Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) DREQ
DACK0
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Source address Destination address Destination address Bus locked
A[25:0]
D[31:0]
Read Read
Write
Write
DREQ0 (Level detection) 2nd acceptance
1st acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC-1
DMAC-2
CPU
DACK0
Figure 11.17 Dual Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/DREQ (Level Detection), DACK (Read Cycle) DREQ
Rev. 1.0, 02/03, page 427 of 1294
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Source address Destination address Destination address Bus locked
A[25:0]
Rev. 1.0, 02/03, page 428 of 1294
Read Read Write Write
D[31:0]
DREQ0 (Level detection) 2nd acceptance
1st acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC-1
DMAC-2
CPU
Figure 11.18 Dual Address Mode/Burst Modes in DMABRG Mode External Bus External Bus/ DREQ (Level Detection), DACK (Read Cycle)
DACK0
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Destination address Source address Destination address Bus locked
A[25:0]
D[31:0]
Read Write Read
Write
DREQ0 (edge detection) 1st acceptance TE bit: transfer end
DREQ1
DRAK0
Bus cycle CPU
DMAC-1
DMAC-2
CPU
DACK0
Figure 11.19 Dual Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) DREQ
Rev. 1.0, 02/03, page 429 of 1294
: DREQ sampling and determination of channel priority
CKIO Bus locked Source address Source address Destination address Destination address Bus locked
A[25:0]
Rev. 1.0, 02/03, page 430 of 1294
Read Write Read Write
D[31:0]
DREQ0 (Edge detection) 1st acceptance TE bit : Transfer end
DREQ1
DRAK0
Bus cycle CPU
DMAC-1
DMAC-2
CPU
Figure 11.20 Dual Address Mode/Burst Modes in DMABRG Mode External Bus External Bus/DREQ (Edge Detection), DACK (Read Cycle) DREQ
DACK0
: DREQ sampling and determination of channel priority
CKIO
Source address Source address Source address
Source address
A[25:0]
D[31:0]
Read Read Read
Read
DREQ0 (level detection) 1st acceptance 2nd acceptance 3rd acceptance
4th acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC
CPU
DMAC
CPU
DMAC
CPU
DMAC
CPU
DACK0
Figure 11.21 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection)
Rev. 1.0, 02/03, page 431 of 1294
: DREQ sampling and determination of channel priority
CKIO
Source address
Source address
Source address
A[25:0]
Rev. 1.0, 02/03, page 432 of 1294
Read Read Read
D[31:0]
DREQ0 (Level detection) 2nd acceptance
1st acceptance
3rd acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC
CPU
DMAC
CPU
DMAC
CPU
DACK0
Figure 11.22 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection)
: DREQ sampling and determination of channel priority
CKIO
Source address Source address
Source address
A[25:0]
D[31:0]
Read
Read
Read
DREQ0 (Edge detection)
1st acceptance 2nd acceptance
3rd acceptance
DREQ1
DRAK0
Bus cycle
CPU DMAC
CPU
DMAC
CPU
DMAC
CPU
DACK0
Figure 11.23 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Edge Detection)
Rev. 1.0, 02/03, page 433 of 1294
: DREQ sampling and determination of channel priority
CKIO
Source Address Source Address
Source Address
A[25:0]
Rev. 1.0, 02/03, page 434 of 1294
Read Read Read
D[31:0]
DREQ0 (edge detection) 2nd acceptance
1st acceptance
3rd acceptance
DREQ1
DRAK0
Bus Cycle
CPU DMAC
CPU
DMAC
CPU
DMAC
CPU
Figure 11.24 Single Address Mode/Cycle Steal Mode in DMABRG Mode External Bus External Device/ DREQ (Edge Detection)
DACK0
: DREQ sampling and determination of channel priority
CKIO
Source address
Source address
Source address
Source address
A[25:0]
D[31:0]
Read
Read
Read
Read
DREQ0 (level detection) 1st acceptance 2nd acceptance 3rd acceptance
4th acceptance
DREQ1
DRAK0
Bus cycle CPU DMAC-1
DMAC-2
DMAC-3
CPU
DMAC-4
DACK0
Figure 11.25 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Level Detection)
Rev. 1.0, 02/03, page 435 of 1294
: DREQ sampling and determination of channel priority
CKIO
Source address
Source address
Source address
A[25:0]
Rev. 1.0, 02/03, page 436 of 1294
Read Read
D[31:0]
Read
DREQ0 (Level detection) 1st acceptance 2nd acceptance
3rd acceptance
DREQ1
DRAK0
Bus cycle CPU
DMAC-1
DMAC-2
CPU
DMAC-3
Figure 11.26 Single Address Mode/Burst Mode in DMABRG Mode External Bus External Device/ DREQ (Level Detection)
DACK0
: DREQ sampling and determination of channel priority
CKIO
Source address Source address Source address
Source address
A[25:0]
D[31:0]
Read
Read
Read
Read
DREQ0 (Edge detection) 1st acceptance TE bit : Transfer end
DRAK0
Bus cycle
CPU
DMAC-1
DMAC-2
DMAC-3
DMAC-4
CPU
DACK0
Figure 11.27 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Bus External Device/ DREQ (Edge Detection)
Rev. 1.0, 02/03, page 437 of 1294
: DREQ sampling and determination of channel priority
CKIO
Source address Source address Source address
Source address
A[25:0]
Rev. 1.0, 02/03, page 438 of 1294
Read Read Read Read
D[31:0]
DREQ0 (edge detection) 1st acceptance TE bit: transfer end
DRAK0
Bus cycle CPU DMAC-1
DMAC-2
DMAC-3
DMAC-4
CPU
Figure 11.28 Single Address Mode/Burst Mode in DMABRG Mode External Bus External Device/ DREQ (Edge Detection)
DACK0
: DREQ sampling and determination of channel priority
CKIO Destination address Destination address Destination address
A[25:0]
D[31:0]
D1 D2 D7 D8 D1 D2 D7
D8
D1
D2
D7
D8
DREQ0 (level detection) 1st acceptance 2nd acceptance 3rd acceptance
DREQ1
DRAK0 DMAC-1 CPU Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle DMAC-2 DMAC-3 CPU
Bus cycle
DACK0
Figure 11.29 Single Address Mode/Burst Mode in External Request 2-Channel Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: 32 bits, SDRAM: row hit write)
: DREQ sampling and determination of channel priority
Rev. 1.0, 02/03, page 439 of 1294
CKIO
Destination address
Destination address
A[25:0]
Rev. 1.0, 02/03, page 440 of 1294
D1 D2 D5 D6 D7 D8 D1 D2 D7 D8 1st acceptance 2nd acceptance DMAC-1 CPU Asserted 2 cycles before start of bus cycle Asserted 2 cycles before start of bus cycle DMAC-2 : DREQ sampling and determination of channel priority
D[31:0]
DREQ0 (Level detection)
DREQ1
DRAK0
Bus cycle
CPU
Figure 11.30 Single Address Mode/Burst Mode in DMABRG Mode External Device External Bus/ DREQ (Level Detection)/32 Byte Block Transfer (Bus Width: 32 bits, SDRAM: row hit write)
DACK0
11.4.6
Ending DMA Transfer
The conditions for ending DMA transfer are different for ending on individual channels and for ending on all channels simultaneously. Following are the procedures for ending transfer, except for ending transfer when the DMATCR value reaches 0. 1. Cycle steal mode (external request, on-chip peripheral module request, auto-request) When transfer end conditions are met, the DMAC waits until all ongoing DMA transfers requested before transfer end conditions are complete, and then stops the operation. In cycle steal mode, the operation is the same for both edge and level transfer request detection. 2. Burst mode, edge detection (external request, DMABRG request, on-chip peripheral module request, auto-request) It generates the same delay between the time transfer end conditions are met and the time the DMAC stops the operation as in cycle steal mode. In burst mode with edge detection, only the first transfer request activates the DMAC, but the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in Burst Mode, Single Address Mode, Edge Detection and Suspension of DMA Transfer with DREQ Level Detection under Operation in section 11.4.5 (3). Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 3. Burst mode, level detection (external request) It generates the same delay between the time transfer end conditions are met and the time the DMAC stops the operation as in cycle steal mode. As in the case of burst mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request sampling timing shown in Burst Mode, Single Address Mode, Edge Detection and Suspension of DMA Transfer in Case of DREQ Level Detection under Operation in section 11.4.5 (3). Therefore, a transfer request is regarded as having been issued until a stop request is detected, and the corresponding processing is executed before the DMAC stops. 4. Bus timing for transfer suspension The DMAC suspends the operation after processing for one bus cycle unit is complete. In dual address mode transfer, the DMAC executes write cycle processing even if a transfer end condition is satisfied during the read cycle. It suspends the operation after completing the transfers mentioned above in 1, 2, and 3.
Rev. 1.0, 02/03, page 441 of 1294
(1) Conditions for Ending Transfer on Individual Channels Transfer ends on the corresponding channel when either of the following conditions is satisfied: * The DMATCR value reaches 0. * The DE bit in CHCR is cleared to 0. 1. End of transfer when DMATCR = 0 When the DMATCR value reaches 0, the DMAC terminates DMA transfer on the corresponding channel and sets the TE bit in CHCR. If the IE bit is set at this time, an interrupt (DMTE) request is sent to the CPU (an interrupt (DMTE) request can not be sent to the CPU for a DMA transfer end when DMATCR = 0 in a DMABRG request). Transfer ending with DMATCR = 0 does not follow the procedures described in 1, 2, 3, and 4 in section 11.4.6. 2. End of transfer when DE = 0 in CHCR When the DE bit in CHCR is cleared to 0, DMA transfer is suspended on the corresponding channel. (During a DMA transfer in a DMABRG request, do not clear the DE bit to 0 by accessing from the CPU.) The TE bit is not set in this case. Transfer ending in this case follows the procedures described in 1, 2, 3, and 4 in section 11.4.6. (2) Conditions for Ending Transfer Simultaneously on All Channels Transfer ends on all channels simultaneously when either of the following conditions is satisfied: * The AE or NMIF bit in DMAOR is set to 1. * The DME bit in DMAOR is cleared to 0. 1. End of transfer with DMAOR.AE = 1 If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is passed to the CPU. Therefore, when the AE bit is set to 1, SAR, DAR, and DMATCR values indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set to 1 in this case. To resume DMA transfer, first correct the channel settings that caused the address error. Next re-specify DMARSRA/DMARSRB even if there is no change in resource. After that read AE = 1 and then write AE = 0. Acceptance of external requests is suspended while the AE bit is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of on-chip peripheral module requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant onchip peripheral module must be cleared to 0 before the new setting is made. DMABRG must be reset for DMABRG requests. See section 11.6.2, DMABRG Reset for the procedure.
Rev. 1.0, 02/03, page 442 of 1294
2. End of transfer with DMAOR.NMIF = 1 If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is passed to the CPU. Therefore, when NMIF is set to 1, the SAR, DAR, and DMATCR values indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. The TE bit is not set to 1 in this case. To resume DMA transfer after NMI interrupt handling is completed, first re-specify DMARSRA/DMARSRB even when there is no resource change. After that read NMIF = 1 and then write NMIF = 0. Acceptance of external requests is suspended while the NMIF bit is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of on-chip peripheral module requests is also suspended, so when resuming transfer, the DMA transfer request enable bit for the relevant onchip peripheral module must be cleared to 0 before the new setting is made. DMABRG must be reset for DMABRG requests. See section 11.6.2, DMABRG Reset for the procedure. 3. End of transfer with DMAOR.DME = 0 If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in accordance with the procedures in 1, 2, 3, and 4 in section 11.4.6, and the bus is passed to the CPU. The TE bit is not set to 1 in this case. When the DME bit is cleared to 0, the SAR, DAR, and DMATCR values indicate the addresses for the DMA transfer to be performed next and the remaining number of transfers. When resuming transfer, set DME to 1. Operation will then be resumed from the next transfer. (3) Notes on Transfer End When DMA transfer ends, requests may be retained in DMAC. Following are examples of cancellation of requests retained in DMAC. * External requests See (2) External Request Mode, in section 11.4.2, DMA Transfer Requests. * On-chip peripheral module requests Retained requests may be processed if DMA transfer occurs. If DMARCR.REXn = 1 when DMA transfer ends then external requests will be retained in DMAC. Examples of processing are shown below. 1. After DMA transfer ends, set the corresponding resources in DMARSRA or DMARSRB to H'00. (Write H'80.) 2. Read Bit REXn corresponding to the channel in DMARCR. REXn = 0: The DMAC has not accepted (retained) a transfer request. Go to 9. REXn = 1: The DMAC has accepted (retained) a transfer request. Go to 3. 3. Set the channel resources corresponding to DMARSRA, DMARSRB to H'7F. (Write H'FF.) 4. Specify external address space in the corresponding channel SARn (the lower 6 bits are 32-bit boundary), and P4 address H'FE09 0020 in DARn. 5. Specify H'0000 0001 in DMATCRn of the corresponding channel.
Rev. 1.0, 02/03, page 443 of 1294
6. Specify CHCRn.DM [1:0] and SM [1:0] = 00 in the corresponding channel, and CHCRn.RS [3:0] = 0111. 7. Setting CHCRn.TE = 0 for the corresponding channel carries out DMA transfer for requests that were retained in DMAC. 8. Confirm that the corresponding channel DMARCR.REXn = 0.
Note: When DMA transfer ends while DMAOR.AE = 1 or DMAOR.NMIF = 1, requests may be cleared even if DMARCR.REXn = 1. In that case, see "1. End of transfer with DMAOR.AE = 1" and "2. End of transfer with DMAOR.NMIF = 1" in (2) Conditions for Ending Transfer Simultaneously on All Channels of this section.
11.4.7
Interrupt-Request Codes
When the number of transfers specified in DMATCR has been finished and the IE bit in CHCR is set to 1, a transfer-end interrupt request can be sent to the CPU from each channel. Table 11.10 lists the interrupt-request codes that are associated with these DMAC interrupts. Table 11.10 DMAC Interrupt-Request Codes
Interrupt Source DMTE0 DMTE1 DMTE2 DMTE3 DMTE4 DMTE5 DMTE6 DMTE7 DMAE DMABRGI0 DMABRGI1 DMABRGI2 Description CH0 transfer-end interrupt* CH1 transfer-end interrupt CH2 transfer-end interrupt CH3 transfer-end interrupt CH4 transfer-end interrupt CH5 transfer-end interrupt CH6 transfer-end interrupt CH7 transfer-end interrupt Address error interrupt USB address error interrupt All data transfer end interrupt Half data transfer end interrupt INTEVT Code H'640 H'660 H'680 H'6A0 H'780 H'7A0 H'7C0 H'7E0 H'6C0 H'A80 H'AA0 H'AC0 Low Priority High
Note: * A CH0 transfer-end interrupt cannot be generated when the DMABRG in DMABRG mode is used.
Rev. 1.0, 02/03, page 444 of 1294
11.5
11.5.1
Examples of Use
Examples of Transfer between External Memory and an External Device with DACK
(1) External Request 2-Channel Mode Examples of transfer of data in external memory to an external device with DACK using DMAC channel 1 in external request 2-channel mode are considered here. Table 11.11 (1) shows the transfer conditions and the corresponding register settings. Table 11.11 (1) Conditions for Transfer between External Memory and External Device with DACK, and Corresponding Register Settings
Transfer Condition Transfer source: external memory Transfer destination: external device with DACK Number of transfers: 32 Transfer source address: decremented Transfer destination address: (setting invalid) Transfer request source: external pin (DREQ1) edge detection Bus mode: burst Transfer unit: word No interrupt request at end of transfer External request 2-channel mode Channel priority order: 2 > 0 > 1 > 3 > 4 > 5 > 6 > 7 Note: * When DREQ1 is specified as a DMA transfer request source in external request 2-channel mode, only channel 1 accepts the DMA transfer request (DREQ0 is accepted only by channel 0). DMAOR H'0000 0201 Register SAR1 DAR1 DMATCR1 CHCR1 Setting H'0C00 0000 (Accessed by DACK) H'0000 0020 H'0000 22A5*
(2) DMABRG Mode Examples of data transfer from external memory to an external device with DACK using DMAC channel 1 in DMABRG mode are considered here. Table 11.11 (2) shows the transfer conditions and the corresponding register settings.
Rev. 1.0, 02/03, page 445 of 1294
Table 11.11 (2) Conditions for Transfer between External Memory and External Device with DACK, and Corresponding Register Settings
Transfer Condition Transfer source: external memory Transfer destination: external device with DACK Number of transfers: 32 Transfer source address: decremented Transfer destination address: (setting invalid) Transfer request source: external pin (DREQ1) edge detection Bus mode: burst Transfer unit: word Request reception priority: round robin No interrupt request at end of transfer DMABRG mode Channel priority order: 2 > 0 > 1 > 3 > 4 > 5 > 6 > 7 Notes: 1. When DREQ0 to DREQ3 are specified as DMA transfer request sources in DMABRG mode, any channels can accept the requests (a limitation on the use of channels in DMABRG mode is only for a DMABRG request). 2. Always write 1 to the CHSET bit when modifying the CHCRn value in DMABRG mode. 3. Always write 1 to the CHnWEN bit of the corresponding channel when modifying the DMARSRA or DMARSRB value. DMAOR H'0000 C201 DMARCR DMARSRA H'0003 0040 H'0011 0000 3 (H'0091 0000* when writing) Register SAR1 DAR1 DMATCR1 CHCR1 Setting H'0C00 0000 (Accessed by DACK) H'0000 0020 H'0000 22A5* 2 (H'0000 22AD* when writing)
1
Rev. 1.0, 02/03, page 446 of 1294
11.6
DMABRG Operation
The DMABRG has independent FIFOs (32-bit 16-stage) for the LCDC, HAC, SSI, and USB with which it performs DMA transfers between the LCDC, HAC, SSI, and USB and synchronous DRAM. The DMABRG transfers a maximum of 32-byte data in a single DMA transfer. 11.6.1 DMABRG Request
DMA transfer by the DMABRG is performed using DMAC channel 0. The independent FIFOs (32-bit 16-stage) for the LCDC, HAC, SSI, and USB generate DMABRG requests. The LCDC, HAC, SSI, and USB that are connected to the DMABRG can operate at the same time. CHCR0*, SAR0, and DAR0 are automatically set according to the LCDC or DMABRG register settings. CHCR0, SAR0, and DAR0 do not have to be set (rewritten) by the CPU. Note: * If CHCR0.DE = 1 is set by the CPU, an address error may occur (DMAOR.AE = 1) and the DMAC will stop operation. When using DMABRG requests, make sure the CPU does not set CHCR0.DE = 1. 11.6.2 DMABRG Reset
The DMAC of this LSI suspends a DMA transfer when the following conditions are met. (1) NMI interrupt occurred (2) DMA address error occurred When the DMAC suspends a DMA transfer by the above conditions while using the DMABRG (LCDC, HAC, SSI, or USB), reset the DMABRG (CHCR.CHSET = 1), re-specify the DMAC registers*, and then reactivate the DMAC. Setting the BRGRST bit in DMAPCR to 1 resets the DMABRG. The reset is canceled by clearing the BRGRST bit to 0. Resetting the DMABRG forcibly terminates DMA transfer for the HAC, SSI, USB, or LCDC. In this case, a transfer end interrupt is not generated. Resetting the DMABRG initializes the following registers to the state of a power-on reset. * DMABRGCR * DMAACR * DMAUSAR * DMAUDAR * DMAURWSZ * DMAUCR
Rev. 1.0, 02/03, page 447 of 1294
Resetting the DMABRG makes the following register values undefined. * DMAATXSAR(0/1) * DMAARXDAR(0/1) * DMAATXTCR(0/1) * DMAARXTCR(0/1) * DMAATXTCNT(0/1) * DMAARXTCNT(0/1) Do not access the registers of the HAC, SSI, USB, LCDC, and DMAC (except for DMAPCR) while the BRGRST bit is 1. Operation is not guaranteed when these registers are accessed in this state. Always write 0 to the DON bit in LDCNTR in the LCDC before writing 1 to the BRGRST bit in DMAPCR. To cancel the DMABRG reset, write 1 to the DON and DON2 bits in LCCNTR in the LCDC and then write 0 to the BRGRST bit in DMAPCR. Note: * Make sure to write 1 to the CHSET bit in CHCR0 before re-specifying the DMAC registers in the case of DMAC reactivation (DMA transfer will be resumed). 11.6.3 DMA Transfer Operating Mode for HAC and SSI
This LSI has two audio codec interfaces. The HAC and SSI are assigned to the audio codec interfaces. This assignment is selected by the IPSELR11 and IPSELR10 bits in IPSELR of the PFC. For details see section 24.2.35, Peripheral Module Select Register (IPSELR). Figure 11.31 shows a configuration of the DMA for the HAC and SSI. This LSI transfers data by the DMA transfer request from the audio codec via DMAC channel 0. A transfer between synchronous DRAM and the audio codec is performed by using a 32-byte 2-stage FIFO for each interface. Audio data for transfer is stored in the transmit/receive buffer of the synchronous DRAM. The transmit/receive buffer is defined by specifying the start address to DMAARXDAR or DMAATXSAR and the number of transfer bytes to DMAARXTCR or DMAATXTCR. When half of the data is transferred (A0TXH, A0RXH, A1TXH, or A1RXH interrupt is used) or all data is transferred (A0TXE, A0RXE, A1TXE, or A1RXE interrupt is used), an interrupt can be generated. Double buffer control for audio data can be used by switching halved transmit/receive buffers. DMAARXDAR, DMAATXSAR, DMAARXTCR, and DMAATXTCR have the auto-reload function. When the same buffer is repeatedly used in the auto-reload function, it is not necessary to re-specify the registers.
Rev. 1.0, 02/03, page 448 of 1294
This LSI DMAC DMABRG Transmit FIFO (0) Peripheral bus
HAC(0) transmit and receive AC97 codec 0 or 2 I S codec 0
SSI(0) transmit or receive
Receive FIFO (0)
HAC(1) transmit and receive AC97 codec 1 or 2 I S codec 1
Transmit FIFO (1)
Receive FIFO (1) SSI(1) transmit or receive
Transfer request priority control
Specified by IPSELR in PFC
Bus state controller
External bus
External synchronous DRAM
Memory space
Transfer start address
Transmit/receive buffer
Half of the transfer size
2-stage buffer control for audio data is enabled by using two types of interrupts: one is generated when half of data has been transferred and another one is generated when all data has been transferred.
Transfer end address
Figure 11.31 Configuration of DMA for HAC/SSI
Rev. 1.0, 02/03, page 449 of 1294
11.6.4
DMA Audio Receive Operation
To receive audio data in DMA transfer, specify DMABRG mode in bits DMS1 and DMS0 in DMAOR and a transfer request source and request acceptance priority order in DMARSRA and DMARCR. Then, specify the start address of a receive buffer storing receive audio data in DMAARXDAR and the number of transfer bytes in DMAARXTCR. Writing 1 to the RDE bit in DMAACR starts receiving the data. 11.6.5 DMA Audio Transmit Operation
To transmit audio data in DMA transfer, specify DMABRG mode in bits DMS1 and DMS0 in DMAOR and a transfer request source and request acceptance priority order in DMARSRA and DMARCR. Specify the start address of a transmit buffer storing transmit audio data in DMAATXSAR and the number of transfer bytes in DMAATXTCR. Writing 1 to the TDE bit in DMAACR starts transmitting the data.
Rev. 1.0, 02/03, page 450 of 1294
HAC DMA transmit setting
HAC DMA receive setting
Select HAC module by setting PFC.IPSELR
Select HAC module by setting PFC.IPSELR
Reset HAC and set operating mode
Reset HAC and set operating mode
Codec ready?
No
Codec ready?
No
Enable interrupt (if necessary)
Enable interrupt (if necessary)
Enable HAC DMA and transfer started HACACR.*DMA*EN = 1
Enable HAC DMA and transfer started HACACR.*DMA*EN = 1
Set DMAC CH0 resource and priority DMAOR (DMABRG mode) DMARCR (acceptance priority) DMARSRA (resource select)
Set DMAC CH0 resource and priority DMAOR (DMABRG mode) DMARCR (acceptance priority) DMARSRA (resource select)
Set DMA transmit address DMAATXSAR (transmit address) DMAATXTCR (Number of bytes transferred)
Set DMA receive address DMAARXDAR (receive address) DMAARXTCR (Number of bytes transferred)
Activate DMAC DMAACR.TDE = 1
Activate DMAC DMAACR.RDE = 1
Has transfer been completed? DMAACR.TDE = 0? Yes
No
Has transfer been completed? DMAACR.RDE = 0? Yes
No
Continue transfer?
Yes Continue transfer?
Yes
No Change DMA resource (if necessary) Disable interrupt (if necessary)
No Change DMA resource (if necessary) Disable interrupt (if necessary)
Disable HAC DMA and transfer completed HACACR.*DMA*EN = 0 HACACR.ST = 0
Disable HAC DMA and transfer completed HACACR.*DMA*EN = 0 HACACR.ST = 0
Transfer end
Transfer end
Figure 11.32
Example of HAC DMA Transfer Operation Flow
Rev. 1.0, 02/03, page 451 of 1294
SSI DMA transmit setting
SSI DMA receive setting
Select SSI module by setting PFC.IPSELR
Select SSI module by setting PFC.IPSELR
Set SSI operating mode (transmit)
Set SSI operating mode (receive)
Enable interrupt (if necessary)
Enable interrupt (if necessary)
Enable SSI DMA and transfer started SSICR.DMEN = 1 SSICR.EN = 1
Enable SSI DMA and transfer started SSICR.DMEN = 1 SSICR.EN = 1
Set DMAC CH0 resource and priority DMAOR (DMABRG mode) DMARCR (acceptance priority) DMARSRA (resource select)
Set DMAC CH0 resource and priority DMAOR (DMABRG mode) DMARCR (acceptance priority) DMARSRA (resource select)
Set DMA transmit address DMAATXSAR (transmit address) DMAATXTCR (Number of bytes transferred)
Set DMA receive address DMAARXDAR (receive address) DMAARXTCR (Number of bytes transferred)
Activate DMAC DMAACR.TDE = 1
Activate DMAC DMAACR.RDE = 1
Has transfer been completed? DMAACR.TDE = 0? Yes
No
Has transfer been completed? DMAACR.RDE = 0? Yes
No
Continue transfer?
Yes
Continue transfer?
Yes
No Change DMA resource (if necessary) Disable interrupt (if necessary)
No Change DMA resource (if necessary) Disable interrupt (if necessary)
Disable SSI DMA and transfer completed SSICR.DMEN = 0 SSICR.EN = 0
Disable SSI DMA and transfer completed SSICR.DMEN = 0 SSICR.EN = 0
Transfer end
Transfer end
Figure 11.33 Example of SSI DMA Transfer Operation Flow
Rev. 1.0, 02/03, page 452 of 1294
11.6.6
Auto Reload Function
The DMAC stops a DMA transfer for the HAC or SSI when the transfer of data bytes specified by DMAATXTCR or DMAARXTCR is complete. When the transfer is complete, the settings specified before the transfer are read out from DMAARXDAR or DMAATXSAR. When restarting a transfer with the same start address and the same transfer bytes, write 1 to the DMA activation bit (RDE or TDE bit) in DMAACR to reactivate the DMAC. It is not necessary to respecify the DMAARXDAR or DMAATXSAR value. When the auto reload setting bit (RAR or TAR bit) in DMAACR is 1, the DMAC is automatically reactivated and performs transfers between the transmit/receive buffer and audio codec repeatedly. To terminate a DMA transfer with the auto reload enabled, write 1 to the DMA forced termination bit (RDS or TDS bit) in DMAACR. 11.6.7 Forced Termination of DMA Audio Transfer
To forcibly terminate a DMA transfer while the transfer of data bytes specified by DMAATXTCR or DMAARXTCR is incomplete, write 1 to the DMA termination bit (RDS or TDS bit) in DMAACR. In a forced termination, a transfer end interrupt is also generated. In a forced termination, the number of transfer bytes remaining on termination is indicated in DMAATXTCNT or DMAARXTCNT. The DMA audio transfer counter loads the DMAATXTCR or DMAARXTCR value on activation of the DMAC (when the RDE or TDE bit in DMAACR is set to 1) and is decremented every time a DMA transfer is performed. When resuming the DMA transfer after a forced termination, check the DMA transfer counter value for transfer progress, respecify the start address and number of transfer bytes, and then reactivate the DMAC. Since DMA audio data is transferred using FIFO, all received data may not be stored in the receive buffer at forced termination. When the DMA forced termination bit (RDS bit) in DMAACR is read as 0, the data is completely stored. Re-specifying the registers with the RDS or TDS bit set to 1 does not activate the DMA. Clear the DMA enable bit of the SSI or HAC to 0 before forcibly terminating a transfer. Figure 11.34 shows the forced termination procedure for the DMA audio transfer.
Rev. 1.0, 02/03, page 453 of 1294
Forced termination and resume procedure
1. To forcibly terminate DMA transfer in HAC or SSI before the specified bytes are transferred, disable DMA in HAC or SSI that are being used. When HAC is in use: When SSI is in use: HACACR.*DMA*_EN = 0 SSICR.EN = 0
Disable interrupt for corresponding transfer (if necessary)
[1] Stop HAC or SSI DMA transfer
With transfer terminate interrupt enabled, it is generated when the terminated DMA stops completely. When the DMA stop causes overrun or underrun in HAC or SSI, the related interrupt should be generated. To avoid interrupt generation, disable the related interrupts beforehand.
[2] Set termination bit in DMAACR DMAACR.TDS = 1 (transmitting) DMAACR.RDS = 1 (receiving)
TDS == 0? (transmitting) RDS == 0? (receiving) Yes
No
2. Setting the forced termination bit in DMAACR stops DMA in HAC or SSI. However, it is only after the completion of the bus cycle being performed that DMA stops completely. Activating DMA before it completely stops will not take effect. To know whether DMA has completely stopped, read the forced termination bit in DMAACR. When the read value is 1, DMA has not stopped. Make sure that the forced termination bit in DMAACR is 0 before activating DMA again. In the receive operation, all received data may not be stored in synchronous DRAM at the DMA forced termination since received data is temporarily stored in FIFO first. Therefore, the forced termination bit in DMAACR will be cleared to 0 when all received data is completely stored in synchronous DRAM.
Is transfer resuming? No
Yes
Read DMAARXTCNT when receiving or DMAATXTCNT when trasmitting to calculate number of transfers remained
Transfer end Set transfer address and number of bytes DMAARXDAR/DMAARXTCR (receiving) DMAATXSAR/DMAATXTCR (transmitting)
Reactivating the related DMA DMAACR.RDE = 1 (receiving) DMAACR.TDE = 1 (transmitting)
Set HAC or SSI DMA again -When HAC is in use: HACACR.*DMA*_EN = 1 -When SSI is in use: SSICR.DMEN = 1
Enable interrupt for corresponding transfer (if necessary)
Transfer resume
Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer
Rev. 1.0, 02/03, page 454 of 1294
HAC/SSI DMA transfer setting (interrupt used) Select HAC/SSI module by setting PFC.IPSELR Reset HAC/SSI and set operating mode
Codec ready? (Only for HAC)
No
Enable DMA interrupts DMABRGCR[31:24] (DMAC side interrupt enable) INTPRI08[23:20] (interrupt level setting) INTMSKCLR00[14:12] (INTC side interrupt enable) Enable HAC/SSI DMA and transfer started HACACR.*DMA*_EN = 1 (HAC) HACACR.AT = 1 (HAC) SSICR.DMEN = 1 (SSI) SSICR.EN = 1 (SSI) Set DMAC CH0 resource and priority DMAOR (DMABRG mode) DMARCR (acceptance priority) DMARSRA (resource select)
Set DMA transfer address DMAARXDAR (receive address: receiving) DMAARXTCR (Number of bytes transferred: receiving) DMAATXSAR (transmit address: transmitting) DMAATXTCR (Number of bytes transferred: transmitting) Activate DMAC DMAACR.RDE = 1 (receiving) DMAACR.TDE = 1 (transmitting)
DMAC interrupt occurred? Yes Check and clear interrupt event DMABRGCR[23:16]
No
Continue transfer? No Change DMA resource Disable interrupts
Yes
Disable HAC/SSI DMA and transfer completed HACACR.*DMA*EN = 0 (HAC) HACACR.AT = 0 (HAC) SSICR.DMEN = 0 (SSI) SSICR.EN = 0 (SSI)
Transfer end
Figure 11.35 HAC/SSI DMA Transfer Operation Flow Using an Interrupt
Rev. 1.0, 02/03, page 455 of 1294
11.6.8
Double Buffer Control for Audio Data
There are two types of transfer end interrupts. * A0TXH, A0RXH, A1TXH, or A1RXH (half data transfer end interrupt) An interrupt is generated when a half of the transfer size specified by DMAARXTCR or 12 DMAATXTCR is completed.* * * A0TXE, A0RXE, A1TXE, or A1RXE (all data transfer end interrupt) An interrupt is generated when the whole transfer size specified by DMAARXTCR or DMAATXTCR is completed. Using half data transfer end and all data transfer end interrupts makes transfers for consecutive audio data efficient since half of the transmit/receive buffer can be accessed by the CPU during a 3 transfer of the other half.* In addition, by enabling the auto reload function (TAR/RAR bit in DMAACR), it is not necessary to re-specify the registers for the second transfer or later. Notes: *1. When the transfer size specified in DMAARXTCR or DMAATXTCR is 4 bytes, a half data transfer end interrupt is not generated. *2. When the transfer size specified in DMAARXTCR or DMAATXTCR is 8n + 4 bytes (n is an integer = 1 or greater) (transfer count is an odd number), a half data transfer end interrupt is generated when n + 1 transfers are completed. *3. The DMABRG for the HAC or SSI has FIFOs that stores a maximum of 64-byte data that is pre-fetched on transmit. If a half of the transfer size of audio data is less than 64 bytes, the remaining data in the transmit/receive buffer may already be stored in the FIFO when a half data transfer end interrupt is generated. When using the double buffer control by a half data transfer end interrupt, configure the transmit/receive buffer in synchronous DRAM having the size of 128 bytes or more. 11.6.9 HAC/SSI Endian Conversion Function
Data is transferred between the HAC or SSI and a transmit/receive buffer in 32-bit (longword) units. When data less than 32 bits is transferred, the byte order of audio data in the transmit/receive buffer in synchronous DRAM may differ from the DMA transfer order, depending on the MD5 pin level which specifies the endian type. (1) 8-Bit Data Transfer for SSI When SSI handles the transfer of 8-bit (byte) audio data, data transfer starts from the leastsignificant byte as shown in figure 11.36: first the left channel data is input to or output from bits 7 to 0, secondly the right channel data is input to or output from bits 15 to 8, and then the next left channel data is input to or output from bits 23 to 16. Selecting big endian mode (MD5 = 0) requires the conversion for alignment such that the least-significant byte is stored in the
Rev. 1.0, 02/03, page 456 of 1294
highest address in the transmit/receive buffer in synchronous DRAM (DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 01).
Slot data Transfer data External bus Address on memory side TAM[1:0]/RAM[1:0] = 01 TAM[1:0]/RAM[1:0] = 00 31-24 R1 23-16 L1 15-8 R0 7-0 L0 Slot data Transfer data External bus Address on memory side TAM[1:0]/RAM[1:0] = 01 TAM[1:0]/RAM[1:0] = 00 31-24 R1 23-16 L1 15-8 R0 7-0 L0
31-24 +0 L0
23-16 +1 R0
15-8 +2 L1
7-0 +3 R1
31-24 +3 R1
23-16 +2 L1
15-8 +1 R0
7-0 +0 L0
Big endian (conversion needed)
Little endian (conversion not needed)
Figure 11.36 8-Bit Data Transfer for SSI (2) 16-Bit Data Transfer for HAC/SSI When HAC or SSI handles the transfer of 16-bit (word) audio data, data transfer starts from the least-significant word as shown in figure 11.37: first the left channel data is input to or output from bits 15 to 0 and then the right channel data is input to or output from bits 31 to 16. Selecting big endian mode (MD5 = 0) requires the conversion for alignment such that the least-significant word is stored in the highest address in a transmit/receive buffer in synchronous DRAM (DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 10).
Slot data Transfer data External bus Address on memory side TAM[1:0]/RAM[1:0] = 01 TAM[1:0]/RAM[1:0] = 00 31-24 R 31-24 +0 L 23-16 15-8 +2 R 23-16 15-8 L 7-0 7-0 Slot data Transfer data External bus Address on memory side TTAM[1:0]/RAM[1:0] = 01 TAM[1:0]/RAM[1:0] = 00 31-24 R 31-24 +2 R 23-16 15-8 +0 L 23-16 15-8 L 7-0 7-0
Big endian (conversion needed)
Little endian (conversion not needed)
Figure 11.37 16-Bit Data Transfer for HAC/SSI 11.6.10 Switching Data for Left and Right Channels When HAC handles the transfer of 16-bit (word) audio data, it performs the alignment such that the left channel data is the most-significant word and the right channel data is the least-significant word. When SSI handles the transfer of 16-bit audio data, however, it performs the alignment such that the left channel data is the least-significant word and the right channel data is the most-significant word. Therefore, the difference must be taken into consideration when performing transfers between HAC and SSI. For DMA transfer of audio data, specify DMAACR.TAM[1:0]/DMAACR.RAM[1:0] = 10 for one channel to adjust the alignment.
Rev. 1.0, 02/03, page 457 of 1294
11.6.11 LCDC DMA Transfer Figure 11.38 shows a DMA transfer flow for the LCDC.
Transfer start [1] Set DMAOR, DMATCR0, and DMARSRA so that DMABRG can be used. [2] Set LCDC registers. For details of LCDC register settings, see section 30, LCDC Controller (LCDC). [3] DMA transfer is started by a DMA transfer request output from the LCDC. Data in synchronous DRAM is stored in FIFO of DMABRG. [4] The data stored in FIFO is transmitted to the LCDC. [5] DMA transfer is repeated until the DMA transfer request from the LCDC is stopped.
Set DMAC registers
[1]
Set LCDC registers
[2]
DMA transfer
Data stored in FIFO
[3]
Data transferred to LCDC
[4]
Has transfer completed? Yes Transfer end
No
[5]
Figure 11.38 Example of LCDC Data Transfer Flow 11.6.12 USB DMA Transfer The USB contains a 8-kbyte shared memory. It is possible to perform a DMA transfer between the USB internal shared memory and synchronous DRAM by using the DMABRG. Figure 11.39 shows a DMA transfer flow between the shared memory and synchronous DRAM. On this transfer, specifying the transfer size and number of transfers is not needed. The DMABRG converts the number of transfer bytes specified by the SZ bits in DMAURWSZ into the appropriate transfer data size and the number of transfers to perform a DMA transfer. When the number of bytes actually transferred reaches the number of transfer bytes specified by the SZ bits in DMAURWSZ, the UTF bit in DMABRGCR is set to 1 and the DMA transfer is successfully completed. When the transfer is continued beyond the shared memory area (H'FE34 1000 to H'FE34 2FFF), a USB address error is generated. When a USB address error is detected, the UAF bit in DMABRGCR is set to 1 and operation ends abnormally.
Rev. 1.0, 02/03, page 458 of 1294
Start
Set DMAOR, DMARCR, and DMARSRA
DMABRGCR.UTE = 1 DMABRGCR.UAE = 1
Set DMAUSAR to transfer source address
Set DMAUDAR to transfer destination address
Set DMAURWSZ to transfer direction and transfer data size
Specify DMAUCR.CVRT as data alignment method
Start transfer DMAUCR.START = 1
DMABRGCR.UTF = 1? or DMABRGCR.UAF = 1? Transfer end successfully UTF = 1
Yes
No
Address error UAF = 1 Review transfer settings DMAUSAR, DMAUSAR, DMAURWSZ
Clear flag DMABRGCR.UTF = 0
Clear flag DMABRGCR.UAF = 0
Data not retransferred?
Yes
No
No more transfer data?
Yes
No
Transfer end
Figure 11.39 DMA Transfer Flow Shared Memory Synchronous DRAM
Rev. 1.0, 02/03, page 459 of 1294
11.6.13 USB Endian Conversion Function The DMABRG supports the endian conversion function for data transfers between the peripheral bus and USB bridge bus, and the external bus and USB bridge bus shown in figure 11.40. The data alignment method of the USB is specified by the CVRT bits in DMAUCR. The data alignment method between the peripheral bus and USB bridge bus differs from that between the external bus and USB bridge bus. Table 11.12 shows the data alignment method between the peripheral bus and USB bridge bus and table 11.13 shows that between the external bus and USB bridge bus.
USB bridge bus 32 bits 32 bits
Peripheral bus
USB 32 bits
DMABRG 32 bits
32 bits External bus
Bus state controller
Synchronous DRAM
Figure 11.40 Bus Arrangement for Data Alignment
Rev. 1.0, 02/03, page 460 of 1294
Table 11.12 Data Alignment between Peripheral Bus and USB Bridge Bus
Transfer Mode Byte boundary mode Access Size Byte Address 4n + 0 31 B0 4n + 1 31 B1 4n + 2 31 B2 4n + 3 31 B3 Word 4n + 0 31 B0 4n + 2 31 B2 Longword 4n + 0 31 B0 Word/longword boundary mode Byte 4n + 0 31 B0 4n + 1 31 B1 4n + 2 31 B2 4n + 3 31 B3 Word 4n + 0 31 B0 4n + 2 31 B2 Longword 4n + 0 31 B0 B1 B2 B3 B3 0 B1 0 31 B2 31 B0 B1 B2 B3 B3 0 0 0 31 B3 31 B0 B1 0 0 0 31 B2 0 0 31 B1 0 B1 B2 B3 0 B3 0 B1 0 31 B3 31 B3 31 B0 0 B2 B1 B0 0 B2 0 0 0 31 B3 31 B1 B0 0 0 0 31 B2 0 0 31 B1 0 Peripheral Bus 0 31 B0 0 USB Bridge Bus 0
Rev. 1.0, 02/03, page 461 of 1294
Table 11.13 Data Alignment between External Bus and USB Bridge Bus
Transfer Mode Byte boundary mode Access Size Byte Address 4n + 0 31 B0 4n + 1 31 B1 4n + 2 31 B2 4n + 3 31 B3 Longword 4n + 0 31 B0 Word/longword boundary mode Byte 4n + 0 31 B0 4n + 1 31 B1 4n + 2 31 B2 4n + 3 31 B3 Longword 4n + 0 31 B0 B1 B2 B3 0 31 B2 B3 B0 B1 0 0 31 B2 31 B3 0 0 0 31 B1 0 B1 B2 B3 0 0 0 31 B3 31 B3 31 B0 0 B2 B1 B0 0 0 0 31 B2 0 0 31 B1 0 Peripheral Bus 0 31 B0 0 USB Bridge Bus 0
11.6.14 DMABRG Interrupts The DMABRG issues three interrupts: a USB address error interrupt, an all data transfer end interrupt, and a half data transfer end interrupt. The DMABRG generates a USB address error interrupt request for a DMA transfer request from the USB, an all data transfer end interrupt request for a DMA transfer request from the HAC, SSI, or USB, and a half data transfer end interrupt request for a transfer request from the HAC or SSI. A DMABRG interrupt request is not generated for a DMA transfer request from the LCDC. When a reset is cancelled, the interrupt priority is in the following order: a USB address error interrupt, an all data transfer end interrupt, and a half data transfer end interrupt.
Rev. 1.0, 02/03, page 462 of 1294
(1) USB Address Error Interrupt Request (DMABRGI0) When a USB address error occurs with the UAE bit in DMABRGCR set to 1, the DMABRG sets the UAF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. (2) All Data Transfer End Interrupt Request (DMABRGI1) * When all data transfer is completed on the receive side for channel 1 of the HAC or SSI with the A1RXEE bit in DMABRGCR set to 1, the DMABRG sets the A1RXEF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. * When all data transfer is completed on the transmit side for channel 1 of the HAC or SSI with the A1TXEE bit in DMABRGCR set to 1, the DMABRG sets the A1TXEF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. * When all data transfer is completed on the receive side for channel 0 of the HAC or SSI with the A0RXEE bit in DMABRGCR set to 1, the A0RXEF bit in DMABRGCR is set to 1 and an interrupt request is output to the INTC. * When all data transfer is completed on the transmit side for channel 0 of the HAC or SSI with the A0TXEE bit in DMABRGCR set to 1, the DMABRG sets the A0TXEF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. * When USB data transfer is completed with the UTE bit in DMABRGCR set to 1, the DMABRG sets the UTF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. (3) Half Data Transfer End Interrupt Request (DMABRGI2) * When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive side for channel 1 of the HAC or SSI with the A1RXHE bit in DMABRGCR set to 1, the DMABRG sets the A1RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. * When data transfer of half of the bytes specified in DMAARXTCR is completed on the transmit side for channel 1 of the HAC or SSI with the A1TXHE bit in DMABRGCR set to 1, the A1TXHF bit in DMABRGCR is set to 1 and an interrupt request is output to the INTC. * When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive side for channel 0 of the HAC or SSI with the A0RXHE bit in DMABRGCR set to 1, the DMABRG sets the A0RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. * When data transfer of half of the bytes specified in DMAARXTCR is completed on the transmit side for channel 0 of the HAC or SSI with the A0TXHE bit in DMABRGCR set to 1, the DMABRG sets the A0TXHF bit in DMABRGCR to 1 and outputs an interrupt request to the INTC. The DMABRG outputs three types of interrupt requests to the INTC: an all data transfer end interrupt, a half data transfer end interrupt and an address error interrupt. To know which interrupt the DMABRG has issued, read interrupt flag bits in DMABRGCR. An interrupt flag bit that is set to 1 indicates the corresponding interrupt has been output.
Rev. 1.0, 02/03, page 463 of 1294
11.7
Usage Notes
1. When modifying SAR, DAR, DMATCR, and CHCR, first clear the DE bit for the relevant channel. 2. Inputting an NMI interrupt with the DMAC not operating sets the NMIF bit in DMAOR. * When DMA transfer is not correctly performed, take the following actions: Read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR, and DMATCR on this LSI. If the NMIF bit was set before the transfer, the DMATCR indicates the transfer count that has been specified. If the NMIF bit was set during the transfer, when the DE bit is 1 and the TE bit is 0 in CHCR, the DMATCR indicates the number of transfers remaining. Also, the next addresses to be accessed can be found by reading SAR and DAR. If the AE bit has been set, an address error has occurred. Check the settings in CHCR, SAR, and DAR. 3. Check that DMA transfer is not in progress before making a transition to module standby state, standby mode, or deep sleep mode. Either check CHCR.TE = 1, or set DMAOR.DME = 0 to terminate DMA transfer. Setting DMAOR.DME = 0 stops the transfer on the completion of the DMA bus cycle currently being performed. Note, therefore, that transfer may not end immediately, depending on the transfer data size. DMA operation is not guaranteed if module standby state, standby mode, or deep sleep mode is entered without confirming that DMA transfer has ended. 4. Do not specify a DMAC, cache, BSC, or UBC control register as the DMAC transfer source or destination. 5. When activating the DMAC, make the SAR, DAR, and DMATCR settings for the relevant channel before setting the DE bit to 1 in CHCR, or make the register settings with the DE bit in CHCR cleared to 0, then set the DE bit to 1. It does not matter whether setting of the DME bit in DMAOR to 1 is carried out first or last. To operate the relevant channel, the DME and DE bits must both be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings are not made (with the exception of the unused register in single address mode). 6. After the DMATCR count reaches 0 and DMA transfer ends successfully, always write 0 to DMATCR even when executing the maximum number of transfers on the same channel. 7. When using falling edge detection for external requests, hold the external request pin high to make DMAC settings. 8. When using the DMAC in single address mode, specify an external address as the address. Specifying an on-chip peripheral module address causes an address error and stops transfers on all channels.
Rev. 1.0, 02/03, page 464 of 1294
Section 12 Clock Pulse Generator (CPG)
This LSI incorporates a clock pulse generator (CPG) that generates a CPU clock (Ick), peripheral clock (Pck), bus clock (Bck), and module clock (Fck). The CPG generates the clocks supplied inside the processor and performs power-down mode control.
12.1
Features
The CPG has the following features. * Six clock modes Any of six clock operating modes can be selected, with different division ratio combinations of the CPU clock, bus clock, and peripheral clock after a power-on reset. * Five clocks The CPG can generate individually the CPU clock (Ick) used by the CPU, FPU, caches, and TLB, the peripheral clock (Pck) used by the peripheral modules, the bus clock (Bck) used by the external bus interface, the module clock (Fck), and the DCK clock (DCK). * Frequency change function The PLL circuits and a frequency divider in the CPG enable the CPU clock, bus clock, peripheral clock, module clock, and DCK clock frequencies to be changed independently. Frequency changes are performed by software in accordance with the settings in FRQCR, MCKCR, and DCKDR. * PLL on/off control Power consumption can be reduced by stopping the PLL circuits during low-frequency operation. * Power-down mode control It is possible to stop the clock in sleep mode, deep sleep mode, hardware standby mode, and software standby mode, and to stop specific modules with the module standby function.
Rev. 1.0, 02/03, page 465 of 1294
Figure 12.1 shows a block diagram of the CPG.
Oscillation circuits Frequency divider 1 x1 x1/2 x1/3 x1/4 x1/6 x1/8
XTAL EXTAL MD8
Crystal oscillator
PLL circuit 1 x6 x12
CPU clock (Ick) cycle Icyc
x1 x1/2 x1/4 x1/8
Frequency divider 3
Peripheral clock (Pck) cycle Pcyc Module clock (Fck) Bus clock (Bck) cycle Bcyc
PLL circuit 2 CKIO x1 PLL circuit 3 DCK x1 x1 x1/2 x1/3
Frequency divider 2
CPG control unit MD2 MD1 MD0 Clock frequency control circuit FRQCR DCKDR MCKCR Bus interface Standby control circuit STBCR STBCR2
Peripheral bus
Legend: FRQCR DCKDR MCKCR STBCR STBCR2
: Frequency control register : Clock division register : Module clock control register : Standby control register : Standby control register 2
Figure 12.1 Block Diagram of CPG Each of the CPG blocks functions as described below. (1) PLL Circuit 1 PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL pin or crystal oscillator by 6 or 12. Starting and stopping of this circuit is controlled by the setting of the frequency control register. (2) PLL Circuit 2 PLL circuit 2 coordinates the phases of the bus clock and the clock signal output from the
Rev. 1.0, 02/03, page 466 of 1294
CKIO pin. Starting and stopping of this circuit is controlled by the setting of the frequency control register. (3) PLL Circuit 3 PLL circuit 3 coordinates the phases of the bus clock and the clock signal output from the DCK pin. Starting and stopping of this circuit is controlled by the setting of the clock division register. (4) Crystal Oscillator Oscillation circuits for when a crystal resonator is connected to the XTAL and EXTAL pins. Usage of the crystal oscillator is enabled by the MD8 pin setting. (5) Frequency Divider 1 Frequency divider 1 generates the CPU clock (Ick), bus clock (Bck), and peripheral clock (Pck). The division ratio is set in the frequency control register. (6) Frequency Divider 2 Frequency divider 2 generates the clock output from the DCK pin. The division ratio is set in the clock division register. (7) Frequency Divider 3 Frequency divider 3 generates the module clock (Fck). The division ratio is set in the module clock control register. (8) Clock Frequency Control Circuit The clock frequency control circuit controls the clock frequency by means of the MD pins, frequency control register, clock division register, and module clock control register. (9) Standby Control Circuit The standby control circuit controls the state of the on-chip oscillation circuits and other modules when the clock is switched or in sleep and standby modes. (10) Frequency Control Register (FRQCR) FRQCR contains control bits for the clock output from the CKIO pin, on/off of PLL circuits 1 and 2, and frequency division ratios of the CPU clock, bus clock, and peripheral clock. (11) Clock Division Register (DCKDR) DCKDR contains control bits for the clock output from the DCK pin, on/off of PLL circuit 3, division ratio of the DCK output clock, and enable/disable of the DCK output clock. (12) Module Clock Control Register (MCKCR) MCKCR contains control bits for the division ratio of the module clock.
Rev. 1.0, 02/03, page 467 of 1294
(13) Standby Control Register (STBCR) STBCR contains power-saving mode control bits. For further information on STBCR, see section 14, Power-Down Modes. (14) Standby Control Register 2 (STBCR2) STBCR2 contains power-saving mode control bits. For further information on STBCR2, see section 14, Power-Down Modes.
12.2
Input/Output Pins
Table 12.1 shows the CPG pin configuration and function. Table 12.1 Pin Configuration and Function of an Oscillation Circuit
Pin Name Mode control pins Abbreviation MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL MD8 Output Input Input Connects crystal resonator. Connects crystal resonator, or used as external clock input pin. Selects use/non-use of crystal resonator. When MD8 = 0, external clock is input from the EXTAL pin. When MD8 = 1, crystal resonator is connected directly to the EXTAL and XTAL pins. Used as external clock output pins. Level can also be fixed. 0 when CKIO output clock is unstable*. I/O Input Function These bits set clock operating mode.
Clock output pins
CKIO DCK
Output Output Output
CKIO enable pin
CKE
Note: * Set to 1 by a power-on reset.
Rev. 1.0, 02/03, page 468 of 1294
12.3
Clock Operating Modes
Table 12.2 shows the relationship between the combinations of mode control pin (MD2 to MD0) settings and clock operating modes. Table 12.3 shows the FRQCR settings and internal clock frequencies. Table 12.2 Clock Operating Modes
Pin Combination MD2 0 0 0 0 1 1 1 MD1 0 0 1 1 0 0 1 MD0 0 1 0 1 0 1 0 PLL1 On (x12) On (x12) On (x6) On (x12) On (x6) On (x12) Off (x6) PLL2 On On On On On On Off CPU Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral Clock 3 3/2 1 2 3/2 3 1/2 FRQCR Initial Value H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808
Clock Operating Mode 0 1 2 3 4 5 6
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode. 2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input frequency (fEX) and CKIO clock output (fOP) in section 33.3.1, Clock and Control Signal Timing.
Rev. 1.0, 02/03, page 469 of 1294
Table 12.3 FRQCR Settings and CPU Clock Frequencies
FRQCR (Lower 9 Bits) H'000 H'002 H'004 H'008 H'00A H'00C H'011 H'013 H'01A H'01C H'023 H'02C H'048 H'04A H'04C H'05A H'05C H'063 H'06C H'091 H'093 H'0A3 H'0DA H'0DC H'0EC H'123 H'16C 1/6 1/8 1/8 1/6 1/8 1/6 1/8 1/4 1/6 1/4 1/3 1/6 1/8 1/3 1/4 1/2 1/6 1/8 1/2 1/4 1/3 1/2 Frequency Division Ratio CPU Clock 1 Bus Clock 1 Peripheral Clock 1/2 1/4 1/8 1/2 1/4 1/8 1/3 1/6 1/4 1/8 1/6 1/8 1/2 1/4 1/8 1/4 1/8 1/6 1/8 1/3 1/6 1/6 1/4 1/8
Note: Do not set the lower nine bits of FRQCR to values other than those shown in this table.
Rev. 1.0, 02/03, page 470 of 1294
12.4
Register Descriptions
The CPG has the following registers. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 12.4 Register Configuration (1)
Register Name Frequency control register Clock division register Module clock control register Abbrev. FRQCR DCKDR MCKCR R/W R/W R/W R/W P4 Address H'FFC0 0000 H'FE0A 0020 H'FE0A 0024 Area 7 Address Size H'1FC0 0000 H'1E0A 0020 H'1E0A 0024 16 32 32 Sync Clock Pck Pck Pck
Table 12.4 Register Configuration (2)
Power-on Reset Manual Reset by RESET Pin/WDT/ by by RESET WDT/ Multiple Pin H-UDI Exception
*1
Retained Retained
Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained * Retained Retained Retained
Register Name Frequency control register Clock division register Module clock control register
Abbrev. FRQCR DCKDR MCKCR
H'0000 0001 H'0000 0000
Retained Retained
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. *1. The initial values of bits 11 to 9 are 1, and those of bits 8 to 0 are undefined.
Rev. 1.0, 02/03, page 471 of 1294
12.4.1
Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register that specifies use/non-use of clock output from the CKIO pin, on/off control of PLL circuits 1 and 2, and the frequency division ratios of the CPU clock, bus clock, and peripheral clock. FRQCR can only be accessed in words. FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is determined by the clock operating mode.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 CKO EN 1 R/W 10 PLL1 EN 1 R/W 9 8 PLL2 IFC2 EN 1 R/W R/W 7 IFC1 R/W 6 5 4 3 2 1 0
IFC0 BFC2 BFC1 BFC0 PFC2 PFC1 PFC0 R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Clock Output Enable Specifies whether a clock is output from the CKIO pin or the CKIO pin is placed in the highimpedance state. When the CKIO pin goes to the high-impedance state, operation continues at the operating frequency before this state was entered. When the CKIO pin becomes highimpedance, it is pulled up. Note that the CKIO pin is not pulled up in hardware standby mode. 0: CKIO pin goes to high-impedance state 1: Clock is output from CKIO pin
15 to 12 --
11
CKOEN
1
R/W
10
PLL1EN
1
R/W
PLL Circuit 1 Enable Specifies whether PLL circuit 1 is on or off. 0: PLL circuit 1 is not used 1: PLL circuit 1 is used
9
PLL2EN
1
R/W
PLL Circuit 2 Enable Specifies whether PLL circuit 2 is on or off. 0: PLL circuit 2 is not used 1: PLL circuit 2 is used
Rev. 1.0, 02/03, page 472 of 1294
Bit 8 7 6
Bit Name IFC2 IFC1 IFC0
Initial Value -- -- --
R/W R/W R/W R/W
Description CPU Clock Frequency Division Ratio Setting These bits specify the CPU clock frequency division ratio with respect to the input clock or PLL circuit 1 output frequency. 000: x 1 001: x 1/2 010: x 1/3 011: x 1/4 100: x 1/6 101: x 1/8 Other than above: Setting prohibited
5 4 3
BFC2 BFC1 BFC0
-- -- --
R/W R/W R/W
Bus Clock Frequency Division Ratio Setting These bits specify the bus clock frequency division ratio with respect to the input clock or PLL circuit 1 output frequency. 000: x 1 001: x 1/2 010: x 1/3 011: x 1/4 100: x 1/6 101: x 1/8 Other than above: Setting prohibited
2 1 0
PFC2 PFC1 PFC0
-- -- --
R/W R/W R/W
Peripheral Clock Frequency Division Ratio Setting These bits specify the peripheral clock frequency division ratio with respect to the input clock or PLL circuit 1 output frequency. 000: x 1/2 001: x 1/3 010: x 1/4 011: x 1/6 100: x 1/8 Other than above: Setting prohibited
Rev. 1.0, 02/03, page 473 of 1294
12.4.2
Clock Division Register (DCKDR)
DCKDR is a 32-bit readable/writable register that specifies use/non-use of clock output from the DCK pin and the DCK clock frequency division ratio. By setting the DIV1 and DIV0 bits, the CKIO clock is divided by 1, 2, or 3 and supplied to the DCK pin. This division ratio setting also allows the DCK clock to be extended to become one to three CKIO cycles even while BS2 is being asserted. For details on adjustment of the CS negate time, see the description of WCR4.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 DCK EN 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 PLL3 EN 0 R/W 18 0 R 2 DCK OUT 0 R/W 17 0 R 1 DIV1 0 R/W 16 0 R 0 DIV0 1 R/W
Bit 31 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Indicates whether the DCK output clock is stable (usable). 0: Unstable (unusable) 1: Stable (usable)
7
DCKEN
0
R
6 to 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. PLL Circuit 3 Enable Specifies whether PLL circuit 3 is on or off. Writing 1 to this bit turns the on-chip PLL circuit 3 on. 0: PLL circuit 3 is not used. In this case, the DCK output is fixed at 1. 1: PLL circuit 3 is used.
3
PLL3EN
0
R/W
2
DCKOUT
0
R/W
DCK Output Control Controls the DCK pin state. Writing 1 to this bit sets the DCK pin at the output state. 0: DCK pin goes to high-impedance state 1: Clock is output from DCK pin
Rev. 1.0, 02/03, page 474 of 1294
Bit 1 0
Bit Name DIV1 DIV0
Initial Value 0 1
R/W R/W R/W
Description Frequency Division Ratio Setting These bits specify the DCK clock frequency division ratio with respect to the CKIO clock. 00: Setting prohibited 01: CKIO x 1/1 10: CKIO x 1/2 11: CKIO x 1/3
12.4.3
Module Clock Control Register (MCKCR)
MCKCR is a 32-bit readable/writable register that specifies the frequency division ratio of the module clock (Fck).
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 FLM CK3 0 R/W 18 0 R 2 FLM CK2 0 R/W 17 0 R 1 FLM CK1 0 R/W 16 0 R 0 FLM CK0 0 R/W
Bit 31 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Module Clock Frequency Division Ratio Setting These bits specify the Fck clock frequency division ratio with respect to the peripheral clock. 0000: Peripheral clock x 1/1 0001: Setting prohibited 0010: Setting prohibited 0011: Setting prohibited Other than above: Setting prohibited
3 2 1 0
FLMCK3 FLMCK2 FLMCK1 FLMCK0
0 0 0 0
R/W R/W R/W R/W
Rev. 1.0, 02/03, page 475 of 1294
12.5
Frequency Changing Method
There are two methods of changing the clock frequency: by switching off and on PLL circuit 1, and by changing the frequency division ratio of each clock. In both cases, control is performed by software by means of FRQCR, MCKCR, and DCKDR. These methods are described below. 12.5.1 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is Off)
When PLL circuit 1 is turned on, the oscillation stabilization time for PLL circuit 1 is required. The oscillation stabilization time is counted by the on-chip WDT. 1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT. The following settings are necessary: TME bit in WTCSR = 0: WDT stopped CKS2 to CKS0 bits in WTCSR: WDT count clock frequency division ratio WTCNT: Initial counter value 2. Set the PLL1EN bit to 1. 3. This LSI operation stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI resumes operation. The WDT stops after overflowing. 12.5.2 Switching between PLL Circuit 1 On/Off (When PLL Circuit 2 is On)
When PLL circuit 2 is on, the oscillation stabilization time for PLL circuit 1 and PLL circuit 2 is required. 1. Make WDT settings as in step 1 in section 12.5.1. 2. Set the PLL1EN bit to 1. 3. This LSI operation stops temporarily, PLL circuit 1 starts oscillation, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, PLL circuit 2 starts oscillation. The WDT resumes its upcount from the value set in step 1 above. Even during this time, the internal clock is stopped and an unstable clock is output to the CKIO pin. 5. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI resumes operation. The WDT stops after overflowing.
Rev. 1.0, 02/03, page 476 of 1294
12.5.3
Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is On)
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, the oscillation stabilization time for PLL circuit 2 is required. 1. Make WDT settings as in step 1 in section 12.5.1. 2. Set the BFC2 to BFC0 bits to the desired value. 3. This LSI stops temporarily, and the WDT starts counting up. The internal clock stops and an unstable clock is output to the CKIO pin. 4. After the WDT count overflows, a clock begins to be supplied within the chip, and this LSI resumes operation. The WDT stops after overflowing. 12.5.4 Changing Bus Clock Frequency Division Ratio (When PLL Circuit 2 is Off)
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, WDT counting is not performed. 1. Set the BFC2 to BFC0 bits to the desired value. 2. The specified clock is switched to immediately. 12.5.5 Changing Frequency Division Ratio of CPU Clock or Peripheral Clock
When the frequency division ratio of the CPU clock or peripheral clock is changed, WDT counting is not performed. 1. Set the IFC2 to IFC0 or PFC2 to PFC0 bits to the desired value. 2. The specified clock is switched to immediately. 12.5.6 Switching between PLL Circuit 3 On/Off
When PLL circuit 3 is turned on, the oscillation stabilization time for PLL circuit 3 is required. The oscillation stabilization time is counted by an on-chip fixed timer. After counting has finished (oscillation stabilized), the DCKEN bit in DCKDR is set to 1. At this timing the DCK oscillation stabilization end can be notified to external devices by using the GPIO to output the value in the DCKEN bit. Before turning on/off PLL circuit 1 or 2, changing the bus clock frequency division ratio, or entering standby mode, make sure to stop PLL circuit 3 (clear the DCKEN bit to 0). After changing these settings, start PLL circuit 3.
Rev. 1.0, 02/03, page 477 of 1294
*
Turning On PLL Circuit 3
1. Set the PLL3EN bit in DCKDR to 1. 2. The on-chip fixed timer starts counting up. At this time, an unstable clock is output to the DCK pin. The DCKEN bit is cleared to 0 to indicate that the DCK cannot be used. 3. After the on-chip fixed timer finishes counting, the DCKEN bit is set to 1 to indicate that DCK oscillation has become stable. For the time until the on-chip fixed timer finishes counting (oscillation stabilization time), refer to section 33, Electrical Characteristics. * Turning Off PLL Circuit 3
1. Clear the PLL3EN bit in DCKDR to 0. 12.5.7 Changing DCK Output Clock Division Ratio
Before changing the DCK clock frequency division ratio, be sure to stop oscillation of PLL circuit 3. 1. Clear the PLL3EN bit in DCKDR to 0. Then set the clock frequency division ratio with the DIV0 and DIV1 bits in DCKDR. 2. Set the PLL3EN bit to 1. 3. The on-chip fixed timer starts counting up. At this time, an unstable clock is output to the DCK pin. The DCKEN bit is cleared to 0 to indicate that the DCK cannot be used. 4. After the on-chip fixed timer finishes counting, the DCKEN bit is set to 1 to indicate that DCK oscillation has become stable. 12.5.8 Controlling DCK Output Clock
The DCK pin can be switched between clock output and the high-impedance state by means of the DCKOUT bit in DCKDR. When the DCK pin goes to the high-impedance state, it is pulled up. Make the DCKOUT bit setting after stopping PLL circuit 3. 1. Clear the PLL3EN bit in DCKDR to 0. Then set the DCK pin state with the DCKOUT bit.
Rev. 1.0, 02/03, page 478 of 1294
12.5.9
Controlling CKIO Output Clock
The CKIO pin can be switched between clock output and the high-impedance state by means of the CKOEN bit in FRQCR. When the CKIO pin goes to the high-impedance state, it is pulled up.
12.6
Usage Notes
(1) Using a crystal resonator Place the crystal resonator and capacitors CL1 and CL2 close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no other signal lines cross the signal lines for these pins.
CL1
CL2
Avoid crossing signal lines
R
Recommended values CL1 = CL2 = 0-33 pF R=0
EXTAL
XTAL
This LSI Note: The values for CL1, CL2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer.
Figure 12.2 Points for Attention when Using Crystal Resonator (2) Inputting external clock from EXTAL pin Make no connection to the XTAL pin. (3) Using a PLL oscillation circuit Separate VDD-CPG and VSS-CPG from the other VDD and VSS lines at the board power supply source, and insert resistors RCB and RB and bypass capacitors CPB and CB, close to the pins.
Rev. 1.0, 02/03, page 479 of 1294
VDD-PLL1 CPB1 VSS-PLL1
RCB1 Recommended values: RCB1 = RCB2 = RCB3 = RB = 10 CPB1 = CPB2 = CPB3 = 10 F (Tantalum capacitor) RCB2 CPB2 CB = 0.1 F (Tantalum capacitor)
VDD-PLL2
VSS-PLL2 This LSI VDD-PLL3 CPB3 VSS-PLL3 RCB3 1.5 V
VDD-CPG CB VSS-CPG
RB 3.3 V
Figure 12.3 Points for Attention when Using PLL Oscillation Circuit
Rev. 1.0, 02/03, page 480 of 1294
Section 13 Watchdog Timer (WDT)
The WDT is a single-channel timer used to count the clock stabilization time when exiting standby mode or a temporary standby state in which the clock frequency is changed. It can be used as a normal watchdog timer or an interval timer.
13.1
Features
The WDT has the following features. * Can be used to secure clock stabilization time Used when exiting standby mode or a temporary standby state in which the clock frequency is changed. * Can be switched between watchdog timer mode and interval timer mode * Internal reset generation in watchdog timer mode An internal reset is executed on counter overflow. * Interrupt generation in interval timer mode An interval timer interrupt is generated on counter overflow. * Selection of eight counter input clocks Any of eight clocks can be selected, scaled from the x1 clock of frequency divider 1 shown in figure 12.1 in Section 12, Clock Pulse Generator (CPG). * Power-on reset or manual reset can be selected. Figure 13.1 shows a block diagram of the WDT.
WDT Standby clearing Internal reset request Interrupt request Standby control Reset control Clock selection Interrupt control WTCSR Overflow WTCNT Frequency divider Clock selector Clock Standby mode Frequency divider 1 x1 clock
Bus interface
Legend: WTCSR : Watchdog timer control/status register WTCNT : Watchdog timer counter
Figure 13.1 Block Diagram of WDT
Rev. 1.0, 02/03, page 481 of 1294
13.2
Register Descriptions
The WDT has the following registers. These registers control clock selection and timer mode switching. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 13.1 Register Configuration (1)
Register Name Watchdog timer counter Watchdog timer control/status register Abbrev. WTCNT WTCSR R/W R/W R/W P4 Address H'FFC0 0008 H'FFC0 000C Area 7 Address H'1FC0 0008 H'1FC0 000C Size 8/16*1 8/16*
1
Sync Clock Pck Pck
Table 13.1 Register Configuration (2)
Manual Reset by RESET Pin/WDT/ by RESET by WDT/ Multiple Exception Pin H-UDI Power-on Reset H'00 H'00 Retained Retained Retained Retained Standby Sleep by by Sleep Software/ Each Instruction/ by Deep Sleep Hardware Module Retained Retained * Retained Retained
Register Name Watchdog timer counter Watchdog timer control/status register
Abbrev. WTCNT WTCSR
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. *1. Read: Byte access Write: Word access
Rev. 1.0, 02/03, page 482 of 1294
13.2.1
Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable counter that counts up on the selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an interrupt is generated in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the RESET pin. To write to WTCNT, use a word-size access with the upper byte set to H'5A. To read from WTCNT, use a byte-size access.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
13.2.2
Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register containing bits for selecting the clock used for counting and timer mode, and overflow flags. To write to WTCSR, use a word-size access with the upper byte set to H'A5. To read from WTCSR, use a byte-size access.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
TME WT/IT RSTS WOVF IOVF CKS2 CKS1 CKS0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7
Bit Name TME
Initial Value 0
R/W Description R/W Timer Enable Specifies starting and stopping of timer operation. Clear this bit to 0 when using the WDT in standby mode or to change a clock frequency. 0: Up-count stopped, WTCNT value retained 1: Up-count started
6
WT/IT
0
R/W Timer Mode Select Specifies whether the WDT is used as a watchdog timer or interval timer. Up counting may not be performed correctly if this bit is modified while the WDT is running. 0: Interval timer mode 1: Watchdog timer mode
Rev. 1.0, 02/03, page 483 of 1294
Bit 5
Bit Name RSTS
Initial Value 0
R/W Description R/W Reset Select Specifies the kind of reset to be performed when WTCNT overflows in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset
4
WOVF
0
R/W Watchdog Timer Overflow Flag Indicates that WTCNT has overflowed in watchdog timer mode. This flag is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W Interval Timer Overflow Flag Indicates that WTCNT has overflowed in interval timer mode. This flag is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W Clock Select 2 to 0 R/W These bits select the clock used for the WTCNT R/W count from eight clocks obtained by dividing the input clock of Frequency divider 1x1 clock. When PLL1 is switched on or off, the clock after the switching is used. The overflow cycles shown below are for use of a 33-MHz input clock and PLL circuit 1 on (x6). Clock Division Ratio 000: 001: 010: 011: 100: 101: 110: 111: 1/32 1/64 1/128 1/256 1/512 1/1024 1/2048 1/4096 Overflow Cycle 41 s 82 s 164 s 328 s 656 s 1.31 ms 2.62 ms 5.25 ms
Up counting may not be performed correctly if bits CKS2 to CKS0 are modified while the WDT is running. Always stop the WDT before modifying these bits.
Rev. 1.0, 02/03, page 484 of 1294
13.2.3
Notes on Register Access
WTCNT and WTCSR differ from other registers in being more difficult to write to. The procedure for writing to these registers is given below. (1) Writing to WTCNT and WTCSR These registers must be written to with a word transfer instruction. They cannot be written to with a byte or longword transfer instruction. As shown in figure 13.2, when writing to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the lower byte containing the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write 15 Address: H'FFC0 0008 (H'1FC0 0008) H'5A 8 7 Write data 0
WTCSR write 15 Address: H'FFC0 000C (H'1FC0 000C) H'A5 8 7 Write data 0
Figure 13.2 Writing to WTCNT and WTCSR
Rev. 1.0, 02/03, page 485 of 1294
13.3
13.3.1
Operation
Standby Clearing Procedure
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The procedure is shown below. (As the WDT does not operate when standby mode is cleared with a reset, the RESET pin should be held low until the clock stabilizes.) 1. Be sure to clear the TME bit in WTCSR to 0 before making a transition to software standby mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2 to CKS0 in WTCSR, and set the initial value in WTCNT. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. Make a transition to software standby mode, and stop the clock, by executing a SLEEP instruction. 3. The WDT starts counting on detection of an NMI signal transition edge or an interrupt. 4. When the WDT count overflows, the CPG starts clock supply and the processor resumes operation. The WOVF flag in WTCSR is not set at this time. 5. The counter stops at a value of H'00 to H'01. The value at which the counter stops depends on the clock ratio. 13.3.2 Frequency Changing Procedure
The WDT is used when changing the clock frequency by means of the PLL. It is not used when the frequency is changed simply by switching between frequency dividers. 1. Be sure to clear the TME bit in WTCSR to 0 before making a frequency change. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count overflows. 2. Select the count clock to be used with bits CKS2 to CKS0 in WTCSR, and set the initial value in WTCNT. Make these settings so that the time until the count overflows is at least as long as the clock oscillation stabilization time. 3. When FRQCR is modified, the clock stops. The WDT starts counting. For details of FRQCR, see section 12.4.1, Frequency Control Register (FRQCR). 4. When the WDT count overflows, the CPG resumes clock supply and the processor resumes operation. The WOVF flag in WTCSR is not set at this time. 5. The counter stops at a value of H'00 to H'01. The value at which the counter stops depends on the clock ratio. 6. When re-setting WTCNT immediately after modifying FRQCR, first read the counter and confirm that its value is as described in step 5 above.
Rev. 1.0, 02/03, page 486 of 1294
13.3.3
Using Watchdog Timer Mode
1. Set the WT/IT bit in WTCSR to 1, select the type of reset with the RSTS bit, and the count clock with bits CKS2 to CKS0, and set the initial value in WTCNT. 2. When the TME bit in WTCSR is set to 1, the count starts in watchdog timer mode. 3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does not overflow. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, and generates a reset of the type specified by the RSTS bit. The counter then continues counting. 13.3.4 Using Interval Timer Mode
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each time the counter overflows. This enables interrupts to be generated at fixed intervals. 1. Clear the WT/IT bit in WTCSR to 0, select the count clock with bits CKS2 to CKS0, and set the initial value in WTCNT. 2. When the TME bit in WTCSR is set to 1, the count starts in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1, and sends an interval timer interrupt request to INTC. The counter continues counting.
Rev. 1.0, 02/03, page 487 of 1294
Rev. 1.0, 02/03, page 488 of 1294
Section 14 Power-Down Modes
In power-down modes, some of the on-chip peripheral modules and the CPU functions are halted, enabling power consumption to be reduced. The following power-down modes and functions are provided. * Sleep mode * Deep sleep mode * Software standby mode * Hardware standby mode * Module standby function Table 14.1 shows the conditions for entering these modes from the program execution state, the status of the CPU and peripheral modules in each mode, and the method of exiting each mode.
Rev. 1.0, 02/03, page 489 of 1294
Table 14.1 Status in Power-Down Modes
PowerDown Mode Sleep mode Status Entering Conditions CPG CPU On-Chip Memory Peripheral Modules Operating Pins External Memory Exiting Method * Interrupt * Reset
Operating SLEEP instruction executed while STBY bit is 0 in STBCR Operating SLEEP instruction executed while STBY bit is 0 in STBCR, and DSLP bit is 1 in STBCR2
Halted Retained (registers retained)
Retained Refreshing
Deep sleep mode
Halted Retained (registers retained)
Operating (DMA halted)
* Interrupt Retained Selfrefreshing * Reset
Software SLEEP Halted standby instruction mode executed while STBY bit is 1 in STBCR Hardware Setting CA pin Halted standby to low level mode Module standby function * Setting MSTP Operating bit to 1 in STBCR * Setting CSTP bit to 1 in CLKSTP00
Halted Retained (registers retained)
Halted
* Interrupt Retained Selfrefreshing * Reset
Halted
Undefined Halted
Highimpedance state
Undefined * Power-on reset
Operating Retained
Specified modules halted
Retained Refreshing
* Clearing MSTP and CSTP bits to 0 * Reset
Rev. 1.0, 02/03, page 490 of 1294
14.1
Input/Output Pins
Table 14.2 shows the pins used for power-down mode control. Table 14.2 Pin Configuration
Pin Name Processing status 1 Processing status 0 Abbreviation STATUS1 STATUS0 I/O Output Function Indicate the processor's operating status.
STATUS1 High High Low Low STATUS0 High Low High Low Operating Status Reset Sleep mode Standby mode Normal operation
Hardware standby request
CA
Input
A transition to hardware standby mode is made by inputting a low-level to the pin.
14.2
Register Descriptions
The following registers are used for power-down mode control. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 14.3 Register Configuration (1)
Register Name Standby control register Standby control register 2 Clock stop register 00 Clock stop clear register 00 Abbrev. STBCR STBCR2 CLKSTP00 R/W R/W R/W R/W P4 Address H'FFC0 0004 H'FFC0 0010 H'FE0A 0000 H'FE0A 0010 Area 7 Address H'1FC0 0004 H'1FC0 0010 H'1E0A 0000 H'1E0A 0010 Size 8 8 32 32 Sync Clock Pck Pck Pck Pck
CLKSTPCLR00 W
Rev. 1.0, 02/03, page 491 of 1294
Table 14.3 Register Configuration (2)
Manual Reset by RESET Pin/WDT/ Multiple Exception Retained Retained Retained Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained * Retained Retained Retained Retained
Register Name Standby control register Standby control register 2 Clock stop register 00 Clock stop clear register 00
Abbrev. STBCR STBCR2 CLKSTP00
Power-on Reset by RESET Pin/ WDT/H-UDI H'00 H'00 H'0000 0000
CLKSTPCLR00
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
14.2.1
Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the power-down mode status.
Bit: Initial value: R/W: 7
STBY
6 0 R
5 0 R
4
MSTP4
3 0 R
2
MSTP2
1 0 R
0 0 R
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name STBY
Initial Value 0
R/W R/W
Description Standby Specifies a transition to software standby mode. 0: Transition to sleep mode on execution of SLEEP instruction 1: Transition to software standby mode on execution of SLEEP instruction
6, 5
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 492 of 1294
Bit 4
Bit Name MSTP4
Initial Value 0
R/W R/W
Description Module Stop 4 Specifies stopping of the clock supply to the DMAC among the peripheral modules. When DMA transfer is used, stop the transfer before setting this bit to 1. When DMA transfer is performed after clearing this bit to 0, DMAC settings must be made again. 0: DMAC operates 1: DMAC clock supply is stopped
3
0
R
Reserved This bit is always read as 0. The write value should always be 0. Module Stop 2 Specifies stopping of the clock supply to the TMU among the peripheral modules. 0: TMU operates 1: TMU clock supply is stopped
2
MSTP2
0
R/W
1, 0
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
14.2.2
Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that specifies the sleep mode and deep sleep mode transition conditions.
Bit: Initial value: R/W: 7 6 5 0 R 4 0 R 3 0 R 2 0 R 1 0
DSLP STHZ
MSTP6 MSTP5
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name DSLP
Initial value 0
R/W R/W
Description Deep Sleep Specifies a transition to deep sleep mode 0: Transition to sleep mode or standby mode on execution of SLEEP instruction, according to setting of the STBY bit in STBCR 1: Transition to deep sleep mode on execution of SLEEP instruction when the STBY bit in STBCR is 0.
Rev. 1.0, 02/03, page 493 of 1294
Bit 6
Bit Name STHZ
Initial value 0
R/W R/W
Description STATUS Pin High-Impedance Control Selects whether the STATUS0 and STATUS1 pins are set to high-impedance in hardware standby mode. 0: Sets STATUS0 and STATUS1 pins to highimpedance in hardware standby mode 1: Drives STATUS0 pin low and STATUS1 pin high in hardware standby mode
5 to 2
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Module Stop 6 Specifies that the clock supply to the store queue (SQ) in the cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ, and the SQ functions are therefore unavailable. 0: SQ operating 1: Specifies stopping of the clock supply to the SQ among the peripheral module.
1
MSTP6
0
R/W
0
MSTP5
0
R/W
Module Stop 5 Specifies stopping of the clock supply to the UBC among the peripheral module. 0: UBC operating 1: UBC clock supply is stopped
Rev. 1.0, 02/03, page 494 of 1294
14.2.3
Clock Stop Register 00 (CLKSTP00)
CLKSTP00 is a 32-bit readable/writable register that controls the operating clock for peripheral modules. The clock supply is stopped by writing 1 to the corresponding bit in CLKSTP00. The clock supply is restarted by writing 1 to the corresponding bit in CLKSTPCLR00. Writing 0 to CLKSTP00 will not change the bit value. Table 14.4 shows which module each bit is assigned to.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 0 R/W 2 0 R/W 17 16
CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP 31 30 29 28 27 26 25 24 23 22 Initial value: 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 15 14 13 12 11 10 9 8 7 6 0 R/W
CSTP CSTP 20 19 0 0 0 R/W R/W R/W 5 0 R/W 4 0 R/W 3 0 R/W
CSTP CSTP 17 16 0 0 R/W R/W 1 0 R/W 0 CSTP 0 0 R/W
CSTP CSTP CSTP CSTP CSTP CSTP CSTP CSTP 15 14 13 12 11 10 9 8 Initial value: 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 14.4 Bit Assignment of CLKSTP00 and CLKSTPCLR00
Bit No. 31 30 29 28 27 26 25 24 Bit Bit Name Module No. Bit Name Module CSTP31 CSTP30 CSTP29 CSTP28 CSTP27 CSTP26 CSTP25 CSTP24 SSI(1) SSI(0) 23 22 CSTP23 CSTP22 CSTP20 CSTP19 CSTP17 CSTP16 MFI HSPI LCDC USB CMT HAC(1) Bit No. 15 14 13 12 11 10 9 8 Bit Name Module CSTP15 CSTP14 CSTP13 CSTP12 CSTP11 CSTP10 CSTP9 CSTP8 HAC(0) ADC Bit No. Bit Name Module 7 6 CSTP0 INTC
SCIF(2) 21 SCIF(1) 20 SCIF(0) 19 I C(1) I2C(0) SIM
2
HCAN2(1) 5 HCAN2(0) 4 DMABRG GPIO MMCIF DMAC 3 2 1 0
18 17 16
Rev. 1.0, 02/03, page 495 of 1294
14.2.4
Clock Stop Clear Register 00 (CLKSTPCLR00)
CLKSTPCLR00 is a 32-bit write-only register that is used to clear corresponding bits in CLKSTP00. Write 1 to the corresponding bits in CLKSTPCLR00 to restart supplying the clock. Table 14.4 shows which module each bit is assigned to.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 W 15
0 W 14
0 W 13
0 W 12
0 W 11
0 W 10
0 W 9
0 W 8
0 W 7
0 W 6
0 W 5
0 W 4
0 W 3
0 W 2
0 W 1
0 W 0
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
14.3
14.3.1
Operation
Sleep Mode
(1) Transition to Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches from the program execution state to sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The peripheral modules continue to operate, and the clock continues to be output from the CKIO pin. In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. (2) Exit from Sleep Mode Sleep mode is exited by means of an interrupt (NMI, IRL, IRQ, GPIO, or peripheral module) or a reset. In sleep mode, interrupts are accepted even if the BL bit in SR is 1. If necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. (a) Exit by interrupt When an NMI, IRL, IRQ, GPIO, or peripheral module interrupt is generated, sleep mode is exited and the interrupt exception handling is executed. The code corresponding to the interrupt source is set in INTEVT. (b) Exit by reset Sleep mode is exited by means of a power-on or manual reset.
Rev. 1.0, 02/03, page 496 of 1294
14.3.2
Deep Sleep Mode
(1) Transition to Deep Sleep Mode If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode. After execution of the SLEEP instruction, the CPU halts but its register contents are retained. Except for the DMAC, peripheral modules continue to operate. The clock continues to be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory that requires refreshing, select self-refreshing mode prior to making the transition to deep sleep mode. Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a transition to deep sleep mode while DMA transfers are in progress, the results of those transfers cannot be guaranteed. In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the STATUS0 pin. (2) Exit from Deep Sleep Mode As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, IRQ, GPIO, or peripheral module) or a reset. 14.3.3 Software Standby Mode
(1) Transition to Software Standby Mode If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches from the program execution state to software standby mode. In software standby mode, the clock and peripheral modules halt as well as the CPU. Clock output from the CKIO pin is also stopped. The CPU and cache register contents are retained. Some peripheral module registers are initialized. The procedure for a transition to software standby mode is shown below. (a) Clear the TME bit in WTCSR of the WDT to 0, and stop the WDT. Set the initial value for up counting in WTCNT of the WDT, and set the clock to be used for up counting in bits CKS2 to CKS0 in WTCSR. (b) Set the STBY bit in STBCR to 1, then execute a SLEEP instruction. (c) When software standby mode is entered and the LSI's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. (2) Exit from Software Standby Mode Software standby mode is exited by means of an interrupt (NMI, IRL, IRQ*, or GPIO) or a reset via the RESET and MRESET pins.
Rev. 1.0, 02/03, page 497 of 1294
Note: * Software standby mode can be cleared by an IRQ4 or IRQ5 interrupt, but not by an IRQ6 or IRQ7 interrupt. (a) Exit by interrupt A hot start can be performed by means of the on-chip WDT. When an NMI, IRL, IRQ, or GPIO interrupt is detected, the WDT starts counting. After the count overflows, clocks are supplied to the entire LSI, software standby mode is exited, and the STATUS1 and STATUS0 pins both go low. Interrupt exception handling is then executed, and the code corresponding to the interrupt source is set in INTEVT. In standby mode, interrupts are accepted even if the BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack before executing the SLEEP instruction. The phase of the CKIO pin clock output may be unstable immediately after an interrupt is detected, until software standby mode is exited. (b) Exit by reset Software standby mode is exited by means of a reset (power-on or manual) via the RESET pin. The RESET pin should be held low until clock oscillation stabilizes. The internal clock continues to be output at the CKIO pin. (3) Clock Pause Function In software standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL pin. This function is used as follows. (a) Enter software standby mode following the transition procedure described above. (b) When software standby mode is entered and the LSI's internal clock stops, a low-level signal is output at the STATUS1 pin, and a high-level signal at the STATUS0 pin. (c) The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the STATUS0 pin high. (d) When the frequency is changed, input an NMI interrupt after the change. When the clock is stopped, input an NMI interrupt after applying the clock. (e) After the time set in the WDT, clock supply begins inside the LSI, the STATUS1 and STATUS0 pins both go low, and operation is resumed from interrupt exception handling. 14.3.4 Module Standby Function
(1) Transition to Module Standby Function Setting 1 to the MSTP6 to MSTP4 and MSTP2 bits in STBCR and STBCR2, and the CSTP31 to CSTP0 bits in CLKSTP00 enables the clock supply to the corresponding peripheral modules to be halted. Use of this function allows power consumption in sleep mode to be further reduced. In the module standby state, the peripheral module external pins retain their states prior to halting of the modules, and most registers retain their states prior to halting of the modules.
Rev. 1.0, 02/03, page 498 of 1294
(2) Exit from Module Standby Function In the case of STBCR and STBCR2, the module standby function is exited by writing 0 to the MSTP6 to MSTP4 and MSTP2 bits. In the case of CLKSTP00, the module standby function is exited by writing 1 to the corresponding bit in CLKSTPCLR00. The module standby function is also exited by means of a power-on reset via the RESET pin or a power-on reset caused by watchdog timer overflow. 14.3.5 Hardware Standby Mode
(1) Transition to Hardware Standby Mode Setting the CA pin level low effects a transition to hardware standby mode. Note that the CA pin must be continuously held low while in hardware standby mode. In this mode, all modules stop, as in software standby mode selected using the SLEEP instruction. Hardware standby mode differs from software standby mode in the following points: (a) Interrupts and manual resets are not available. (b) All output pins other than the STATUS pins are in the high-impedance state and the pull-up resistance is off. Operation when a low-level is input to the CA pin in software standby mode depends on the CPG status, as follows: (a) In software standby mode The clock remains stopped and a transition is made to the hardware standby state. (b) When WDT is operating at the time software standby mode is exited by interrupt After software standby mode is momentarily exited and the CPU restarts operation, a transition is made to hardware standby mode. (2) Exit from Hardware Standby Mode Hardware standby mode is exited by means of a power-on reset via the RESET pin. 14.3.6 STATUS Pin Change Timing
The timing of STATUS1 and STATUS0 pin changes is shown below.
Rev. 1.0, 02/03, page 499 of 1294
(1) In Reset (a) Power-on reset
CKIO PLL stabilization time
RESET
STATUS
Normal*1
Reset*2
Normal*1
0-30 Bcyc*3 0-5 Bcyc*3 Notes: 1. Normal 2. Reset 3. Bcyc : LL (STATUS1 is low and STATUS0 is low) : HH (STATUS1 is high and STATUS0 is high) : Bus clock cycle
Figure 14.1 STATUS Output in Power-On Reset (b) Manual reset
CKIO
RESET (High)
MRESET*1
STATUS
Normal *2
Reset *3
Normal *2
0-30 Bcyc *4 0 Bcyc *1,*4 Notes: 1. In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting until the end of the currently executing bus cycle 2. Normal :LL (STATUS1 is low and STATUS0 is low) 3. Reset :HH (STATUS1 is high and STATUS0 is high) 4. Bcyc : Bus clock cycle
Figure 14.2 STATUS Output in Manual Reset
Rev. 1.0, 02/03, page 500 of 1294
(2) In Exit from Software Standby Mode (a) Software standby Interrupt
Oscillation stops Interrupt request WDT overflow
CKIO WDT count Normal *
1
STATUS
Standby *
2
Normal *
1
Notes:
1. Normal 2. Standby
: LL (STATUS1 is low and STATUS0 is low) : LH (STATUS1 is low and STATUS0 is high)
Figure 14.3 STATUS Output in Sequence of Software Standby Interrupt (b) Software standby Power-on reset
Oscillation stops Reset
CKIO
RESET*1 Undefined STATUS Normal*2 Standby*3 Reset*4 Normal*2
0-10 Bcyc*5
0-30 Bcyc*5
Notes: 1. When standby mode is exited by means of a power-on reset, a WDT count is not performed. Hold RESET low for the PLL oscillation stabilization time. 2. Normal : LL (STATUS1 is low and STATUS0 is low) 3. Standby : LH (STATUS1 is low and STATUS0 is high) 4. Reset : HH (STATUS1 is high and STATUS0 is high) 5. Bcyc : Bus clock cycle
Figure 14.4 STATUS Output in Sequence of Software Standby Power-On Reset
Rev. 1.0, 02/03, page 501 of 1294
(c) Software standby Manual reset
Oscillation stops Reset
CKIO
RESET (High) MRESET*1
STATUS
Normal*2
Standby*3
Undefined
Reset*4
Normal*2
0-30 Bcyc*5
0-20 Bcyc*5
Notes: 1. When standby mode is exited by means of a manual reset, a WDT count is not performed. Hold MRESET low for the PLL oscillation stabilization time. 2. Normal : LL (STATUS1 is low and STATUS0 is low) 3. Standby : LH (STATUS1 is low and STATUS0 is high) 4. Reset : HH (STATUS1 is high and STATUS0 is high) : Bus clock cycle 5. Bcyc
Figure 14.5 STATUS Output in Sequence of Software Standby Manual Reset (3) In Exit from Sleep Mode (a) Sleep Interrupt
Interrupt request
CKIO
STATUS
Normal*1
Sleep*2
Normal*1
Notes:
1. Normal : LL (STATUS1 is low and STATUS0 is low) 2. Sleep : HL (STATUS1 is high and STATUS0 is low)
Figure 14.6 STATUS Output in Sequence of Sleep Interrupt
Rev. 1.0, 02/03, page 502 of 1294
(b) Sleep Power-on reset
Reset
CKIO
RESET*1 Undefined STATUS Normal*2 Sleep*3 Reset*4 Normal*2
0-10 Bcyc*5
0-30 Bcyc*5
Notes: 1. When sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time. 2. Normal : LL (STATUS1 is low and STATUS0 is low) 3. Sleep : HL (STATUS1 is high and STATUS0 is low) 4. Reset : HH (STATUS1 is high and STATUS0 is high) : Bus clock cycle 5. Bcyc
Figure 14.7 STATUS Output in Sequence of Sleep Power-On Reset (c) Sleep Manual reset
Reset
CKIO
RESET (High)
MRESET*1
STATUS
Normal*2
Sleep*3
Reset*4
Normal*2
0-30 Bcyc*5 Notes: 1. 2. 3. 4. 5. Hold MRESET low until STATUS = reset. Normal : LL (STATUS1 is low and STATUS0 is low) Sleep : HL (STATUS1 is high and STATUS0 is low) Reset : HH (STATUS1 is high and STATUS0 is high) Bcyc : Bus clock cycle
0-30 Bcyc*5
Figure 14.8 STATUS Output in Sequence of Sleep Manual Reset
Rev. 1.0, 02/03, page 503 of 1294
(4) In Exit from Deep Sleep Mode (a) Deep sleep Interrupt
Interrupt request
CKIO
STATUS
Normal*1
Sleep*2
Normal*1
Notes:
1. Normal : LL (STATUS1 is low and STATUS0 is low) 2. Sleep : HL (STATUS1 is high and STATUS0 is low)
Figure 14.9 STATUS Output in Sequence of Deep Sleep Interrupt (b) Deep sleep Power-on reset
Reset
CKIO
RESET*1 Undefined STATUS Normal*2 Sleep*3 Reset*4 Normal*2
0-10 Bcyc*5
0-30 Bcyc*5
Notes: 1. When deep sleep mode is exited by means of a power-on reset, hold RESET low for the oscillation stabilization time. 2. Normal : LL (STATUS1 is low and STATUS0 is low) 3. Sleep : HL (STATUS1 is high and STATUS0 is low) 4. Reset : HH (STATUS1 is high and STATUS0 is high) 5. Bcyc : Bus clock cycle
Figure 14.10 STATUS Output in Sequence of Deep Sleep Power-On Reset
Rev. 1.0, 02/03, page 504 of 1294
(c) Deep sleep Manual reset
Reset
CKIO
RESET (High)
MRESET*1
STATUS
Normal*2
Sleep*3
Reset*4
Normal*2
0-30 Bcyc*5 Notes: 1. 2. 3. 4. 5. Hold MRESET low until STATUS = reset. Normal : LL (STATUS1 is low and STATUS0 is low) Sleep : HL (STATUS1 is high and STATUS0 is low) Reset : HH (STATUS1 is high and STATUS0 is high) : Bus clock cycle Bcyc
0-30 Bcyc*5
Figure 14.11 STATUS Output in Sequence of Deep Sleep Manual Reset
Rev. 1.0, 02/03, page 505 of 1294
14.3.7
Hardware Standby Mode Timing
Figure 14.12 shows the timing of the signals of the respective pins in hardware standby mode. The CA pin level must be kept low while in hardware standby mode. After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
RESET
STATUS
Normal*1,*2
Standby*3
Undefined
Reset*4
0-10 Bcyc*5 Waiting for end of bus cycle Notes: 1. 2. 3. 4. 5.
0-10 Bcyc*5
Same in sleep and reset. Normal : LL (STATUS1 is low and STATUS0 is low) Standby : LH (STATUS1 is low and STATUS0 is high) Reset : HH (STATUS1 is high and STATUS0 is high) Bcyc : Bus clock cycle
Figure 14.12 Hardware Standby Mode Timing (When CA = Low in Normal Operation)
Rev. 1.0, 02/03, page 506 of 1294
Interrupt request
WDT overflow
CKIO
CA
RESET
(High)
STATUS
Standby*1
Normal*2
Standby*1
0-10 Bcyc*3 WDT count Notes: 1. Standby 2. Normal 3. Bcyc : LH (STATUS1 is low and STATUS0 is high) : LL (STATUS1 is low and STATUS0 is low) : Bus clock cycle
Figure 14.13 Hardware Standby Mode Timing (When CA = Low in WDT Operation)
VDDQ*
VDD
VDDmin
CA
RESET min.0 s min.0 s max.50 s Note: * VDDQ, VDD-CPG
Figure 14.14 Timing when Power is Off
Rev. 1.0, 02/03, page 507 of 1294
Rev. 1.0, 02/03, page 508 of 1294
Section 15 Timer Unit (TMU)
This LSI includes an on-chip 32-bit timer unit (TMU) which has three channels (channels 0 to 2).
15.1
Features
The TMU has the following features. * Auto-reload type 32-bit down-counter provided for each channel * Input capture function provided in channel 2 * Selection of rising edge or falling edge as external clock input edge when external clock is selected or input capture function is used for each channel * 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit down-counter provided for each channel * Selection of six counter input clocks for each channel External clock (TCLK), five peripheral clocks (Pck/4, Pck/16, Pck/64, Pck/256, and Pck/1024) (Pck is the peripheral clock) * Two interrupt sources One underflow source (each channel) and one input capture source (channel 2) * DMAC data transfer request capability In channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is generated.
Rev. 1.0, 02/03, page 509 of 1294
Figure 15.1 shows a block diagram of the TMU.
RESET, STBY,etc. TUNE0, TUNE1 Pck/4, Pck/16, Pck/64*
TUNI2 ICPI2
TCLK
TMU operation controller
Prescaler To each To channels channel 0 to 2
TCLK controller
TSTR Channels 0 and 1 Interrupt controller Channel 2 Counter Interrupt controller
Counter
TCR
TCOR
TCNT
TCR2
TCOR2
TCNT2
TCPR2
Bus interface
Peripheral bus Note: * Internal signals with 1/4, 1/16, or 1/64 of the Pck frequency and supplied to the on-chip peripheral modules. Legend: TSTR : Timer start register TCOR : Timer constant register TCNT : Timer counter : Timer control register TCR TCPR2 : Input capture register 2 (only in channel 2)
Figure 15.1 Block Diagram of TMU
15.2
Input/Output Pins
Table 15.1 shows the TMU pin configuration. Table 15.1 Pin Configuration
Pin Name Clock input Abbreviation TCLK I/O Input Function External clock input pin/input capture control input pin
Rev. 1.0, 02/03, page 510 of 1294
15.3
Register Descriptions
The TMU has the following registers. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 15.2 Register Configuration (1)
Ch. Register Name Abbrev. R/W TSTR R/W P4 Address H'FFD8 0004 H'FFD8 0008 H'FFD8 000C H'FFD8 0010 H'FFD8 0014 H'FFD8 0018 H'FFD8 001C H'FFD8 0020 H'FFD8 0024 H'FFD8 0028 H'FFD8 002C Area 7 Address Size H'1FD8 0004 H'1FD8 0008 H'1FD8 000C H'1FD8 0010 H'1FD8 0014 H'1FD8 0018 H'1FD8 001C H'1FD8 0020 H'1FD8 0024 H'1FD8 0028 H'1FD8 002C 8 32 32 16 32 32 16 32 32 16 32 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Common Timer start register
0
Timer constant register 0 Timer counter 0 Timer control register 0
TCOR0 R/W TCNT0 TCR0 R/W R/W
1
Timer constant register 1 Timer counter 1 Timer control register 1
TCOR1 R/W TCNT1 TCR1 R/W R/W
2
Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2
TCOR2 R/W TCNT2 TCR2 TCPR2 R/W R/W R
Rev. 1.0, 02/03, page 511 of 1294
Table 15.2 Register Configuration (2)
Manual Reset by RESET Pin/WDT/ Multiple Exception Standby Sleep by Sleep by Software/ Instruction Each /Deep by Sleep Hardware Module
Ch.
Register Name
Power-on Reset by RESET Pin/ Abbrev. WDT/H-UDI
Common Timer start register
TSTR
H'00
H'00
Retained
*
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
0
Timer constant register 0 Timer counter 0 Timer control register 0
TCOR0 H'FFFF FFFF H'FFFF FFFF Retained TCNT0 TCR0 H'FFFF FFFF H'FFFF FFFF Retained H'0000 H'0000 Retained
1
Timer constant register 1 Timer counter 1 Timer control register 1
TCOR1 H'FFFF FFFF H'FFFF FFFF Retained TCNT1 TCR1 H'FFFF FFFF H'FFFF FFFF Retained H'0000 H'0000 Retained
2
Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2
TCOR2 H'FFFF FFFF H'FFFF FFFF Retained TCNT2 TCR2 TCPR2 H'FFFF FFFF H'FFFF FFFF Retained H'0000 Retained H'0000 Retained Retained Retained
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
15.3.1
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that specifies whether TCNT in each channel is operated or stopped.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 1 0
STR2 STR1 STR0 0 R/W 0 R/W 0 R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Counter Start 2 Specifies whether TCNT2 is operated or stopped. 0: TCNT2 count operation is stopped 1: TCNT2 performs count operation
2
STR2
0
R/W
Rev. 1.0, 02/03, page 512 of 1294
Bit 1
Bit Name STR1
Initial Value 0
R/W R/W
Description Counter Start 1 Specifies whether TCNT1 is operated or stopped. 0: TCNT1 count operation is stopped 1: TCNT1 performs count operation
0
STR0
0
R/W
Counter Start 0 Specifies whether TCNT0 is operated or stopped. 0: TCNT0 count operation is stopped 1: TCNT0 performs count operation
15.3.2
Timer Constant Register (TCORn) (n = 0 to 2)
The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT, which continues counting down from the set value.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
1 R/W 11
1 R/W 10
1 R/W 9
1 R/W 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
15.3.3
Timer Counter (TCNTn) (n = 0 to 2)
The TCNT registers are 32-bit readable/writable registers. Each TCNT counts down on the input clock selected by the TPSC2 to TPSC0 bits in TCR. When a TCNT counter underflows while counting down, the UNF flag is set in TCR of the corresponding channel. At the same time, the TCOR value is set in TCNT, and the count-down operation continues from the set value.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1 R/W 15
1 R/W 14
1 R/W 13
1 R/W 12
1 R/W 11
1 R/W 10
1 R/W 9
1 R/W 8
1 R/W 7
1 R/W 6
1 R/W 5
1 R/W 4
1 R/W 3
1 R/W 2
1 R/W 1
1 R/W 0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Rev. 1.0, 02/03, page 513 of 1294
15.3.4
Timer Control Registers (TCRn) (n = 0 to 2)
The TCR registers are 16-bit readable/writable registers. Each TCR selects the count clock, specifies the edge when an external clock is selected, and controls interrupt generation when the flag indicating TCNT underflow is set to 1. TCR2 is also used for input capture control and control of interrupt generation in the event of input capture. * TCR0 and TCR1
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8
UNF
7 0 R
6 0 R
5
UNIE
4
3
2
1
0
CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
* TCR2
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9
ICPF
8
UNF
7
6
5
UNIE
4
3
2
1
0
ICPE1 ICPE0
CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0. Input Capture Interrupt Flag Status flag, provided in channel 2 only, which indicates the occurrence of input capture. 0: Input capture has not occurred [Clearing condition] When 0 is written to ICPF 1: Input capture has occurred [Setting condition] 2 When input capture occurs*
15 to 10 --
9
ICPF*
1
0
R/W
8
UNF
0
R/W
Underflow Flag Status flag that indicates the occurrence of TCNT underflow. 0: TCNT has not underflowed [Clearing condition] When 0 is written to UNF 1: TCNT has underflowed [Setting condition] When TCNT underflows*
2
Rev. 1.0, 02/03, page 514 of 1294
Bit 7 6
Bit Name ICPE1* 1 ICPE0*
1
Initial Value R/W 0 0 R/W R/W
Description Input Capture Control These bits, provided in channel 2 only, specify whether the input capture function is used, and control enabling or disabling of interrupt generation when the function is used. When the input capture function is used, a data transfer request is sent to the DMAC in the event of input capture. The CKEG bits specify whether the rising edge or falling edge of the TCLK pin is used to set the TCNT2 value in TCPR2. The TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. When the ICPF bit is 1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer request is generated regardless of the value of the ICPF bit. However, a new DMAC transfer request is not generated until processing of the previous request is finished. 00: Input capture function is not used. 01: Setting prohibited 10: Input capture function is used, but interrupt due to input capture (TICPI2) is not enabled. Data transfer request is sent to the DMAC in the event of input capture. 11: Input capture function is used, and interrupt due to input capture (TICPI2) is enabled. Data transfer request is sent to the DMAC in the event of input capture.
5
UNIE
0
R/W
Underflow Interrupt Control Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1, indicating TCNT underflow. 0: Interrupt due to underflow (TUNI) is disabled 1: Interrupt due to underflow (TUNI) is enabled
4 3
CKEG1 CKEG0
0 0
R/W R/W
Clock Edge 1 and 0 These bits select the external clock input edge when an external clock is selected or the input capture function is used. 00: Count/input capture register set on rising edge 01: Count/input capture register set on falling edge 1X: Count/input capture register set on both rising and falling edges
Rev. 1.0, 02/03, page 515 of 1294
Bit 2 1 0
Bit Name TPSC2 TPSC1 TPSC0
Initial Value R/W 0 0 0 R/W R/W R/W
Description Timer Prescaler 2 to 0 These bits select the TCNT count clock. 000: Counts on Pck/4 001: Counts on Pck/16 010: Counts on Pck/64 011: Counts on Pck/256 100: Counts on Pck/1024 101: Setting prohibited 110: Setting prohibited 111: Counts on external clock (TCLK)
Notes: X: Don't care *1. Reserved bit in channel 0 or 1 (initial value is 0, and can only be read). *2. Writing 1 does not change the value; the previous value is retained.
15.3.5
Input Capture Register 2 (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in channel 2. The input capture function is controlled by means of the ICPE and CKEG bits in TCR2. When input capture occurs, the TCNT2 value is copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 15
R 14
R 13
R 12
R 11
R 10
R 9
R 8
R 7
R 6
R 5
R 4
R 3
R 2
R 1
R 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 1.0, 02/03, page 516 of 1294
15.4
Operation
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). Each TCNT performs count-down operation. The channels have an auto-reload function that allows cyclic count operations, and can also perform external event counting. Channel 2 also has an input capture function. 15.4.1 Counter Operation
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied from TCOR into TCNT, and the count-down continues (auto-reload function). (1) Example of Count Operation Setting Procedure Figure 15.2 shows an example of the count operation setting procedure.
Select operation
Select count clock
(1)
Underflow interrupt generation setting
(1) Select the count clock with the TPSC2 to TPSC0 bits in TCR. When the external clock (TCLK) is selected, specify the external clock edge with the When input capture CKEG1 and CKEG0 bits in TCR. function is used (2) Specify whether an interrupt is to be generated Input capture interrupt (3) on TCNT underflow with the UNIE bit in TCR. generation setting (3) When the input capture function is used, set the ICPE bits in TCR, including specification of whether the interrupt function is to be used. (4) Set a value in TCOR. Timer constant (4) (5) Set the initial value inTCNT. register setting (6) Set the STR bit to 1 in TSTR to start the count. (2) Set initial timer counter value (5)
Start count
(6)
Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt enabled state is set without clearing the flag, another interrupt will be generated.
Figure 15.2 Example of Count Operation Setting Procedure
Rev. 1.0, 02/03, page 517 of 1294
(2) Auto-Reload Count Operation Figure 15.3 shows the TCNT auto-reload operation.
TCNT value TCOR
TCOR value set in TCNT on underflow
H'0000 0000 STR0-STR2
Time
UNF
Figure 15.3 TCNT Auto-Reload Operation (3) TCNT Count Timing * Operating on internal clock Any of five count clocks (Pck/4, Pck/16, Pck/64, Pck/256, or Pck/1024) scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR. Figure 15.4 shows the timing in this case.
Pck Internal clock
TCNT
N+1
N
N-1
Figure 15.4 Count Timing when Operating on Internal Clock
Rev. 1.0, 02/03, page 518 of 1294
* Operating on external clock The external clock pin (TCLK) input can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR. The detected edge (rising, falling, or both edges) can be selected with the CKEG1 and CKEG0 bits in TCR. Figure 15.5 shows the timing for both-edge detection.
Pck External clock input pin TCNT N+1 N N-1
Figure 15.5 Count Timing when Operating on External Clock 15.4.2 Input Capture Function
Channel 2 has an input capture function. The procedure for using the input capture function is as follows: 1. Use bits TPSC2 to TPSC0 in TCR to set an internal clock as the timer operating clock. 2. Use bits ICPE1 and ICPE0 in TCR to specify whether to use the input capture function and when using this function whether to generate interrupts. 3. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK pin is to be used to set the TCNT value in TCPR2. When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0. A new DMAC transfer request is not generated until processing of the previous request is finished. Figure 15.6 shows the operation timing when the input capture function is used (with TCLK rising edge detection).
Rev. 1.0, 02/03, page 519 of 1294
TCNT value TCOR
TCOR value set in TCNT on underflow
H'0000 0000 TCLK
Time
TCPR2
TCNT value set
TICPI2
Figure 15.6 Operation Timing when Using Input Capture Function
15.5
Interrupts
There are four TMU interrupt sources: underflow interrupts and the input capture interrupt when the input capture function is used. Underflow interrupts are generated on each of the channels, and input capture interrupts on channel 2 only. An underflow interrupt request is generated (for each channel) when both the UNF bit and the interrupt enable bit (UNIE) for that channel are set to 1. When the input capture function is used and an input capture request is generated, an interrupt is requested if the ICPF bit in TCR2 is 1 and the input capture control bits (ICPE1 and ICPE0) in TCR2 are both set to 11. The TMU interrupt sources are summarized in table 15.3. Table 15.3 TMU Interrupt Sources
Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Low Priority High
Rev. 1.0, 02/03, page 520 of 1294
15.6
15.6.1
Usage Notes
Register Writes
When writing to a TMU register, timer count operation must be stopped by clearing the start bit (STR2 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and the UNF and ICPF bits in TCR can be cleared while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in progress, make sure not to change the values of bits other than those being cleared. 15.6.2 Reading from TCNT
Reading from TCNT is performed synchronously with the timer count operation. Note that when the timer count operation is performed simultaneously with reading from a register, the synchronous processing causes the TCNT value before the count-down operation to be read as the TCNT value. 15.6.3 External Clock Frequency
Ensure that the external clock (TCLK) frequency for each channel does not exceed Pck/4.
Rev. 1.0, 02/03, page 521 of 1294
Rev. 1.0, 02/03, page 522 of 1294
Section 16 Timer/Counter (CMT)
The unit has 2 major modes of operation. It can be configured as a four-channel timer/counter unit that contains a 32 bit free running timer as a common time-stamp for four 32-bit capture/compare registers. Alternatively it can be configured as four 16-bit timer/counters with count enables. In this mode there are four independent 16-bit incrementing/decrementing blocks. Each channel can then be set up to output a signal when the compare time is reached or to store the timer value when an input edge is received. This latter case also supports up/down counting on some channels.
16.1
Features
* 32-bit free-running timer * Four channels of output compare or input capture * 4-channel 16-bit timer/counter * Interrupt on capture, compare, and overflow * Programmable pin/edge polarity * Programmable timer clock * Independent clocks for 16-bit timers * Rotary switches supported Figure 16.1 shows a block diagram of the CMT.
IRQ
CPU
CMT_CTR0
Peripheral bus
CMT_CTR1 Timer/ Counter CMT_CTR2
CMT_CTR3
Figure 16.1 Block Diagram of CMT
Rev. 1.0, 02/03, page 523 of 1294
16.2
Input/Output Pins
Table 16.1 shows the CMT pin configuration. Table 16.1 Pin Configuration
Pin Name CMT_CTR0 to CMT_CTR3 Number of Pins 4 I/O Input/Output Function Multi-function timer/counter input/output
16.3
Register Descriptions
The CMT has the following registers. For details on the addresses of these registers and the state of registers in each operating mode, see section 33, List of Registers. Table 16.2 Register Configuration (1)
Ch. Register Name Abbrev. CMTCFG CMTFRT CMTCTL CMTIRQS R/W R/W R R/W R/W P4 Address H'FE1C 0000 H'FE1C 0004 H'FE1C 0008 H'FE1C 000C H'FE1C 0010 H'FE1C 0020 H'FE1C 0030 H'FE1C 0014 H'FE1C 0024 H'FE1C 0034 H'FE1C 0018 H'FE1C 0028 H'FE1C 0038 H'FE1C 001C H'FE1C 002C H'FE1C 003C Area 7 Address Size H'1E1C 0000 H'1E1C 0004 H'1E1C 0008 H'1E1C 000C H'1E1C 0010 H'1E1C 0020 H'1E1C 0030 H'1E1C 0014 H'1E1C 0024 H'1E1C 0034 H'1E1C 0018 H'1E1C 0028 H'1E1C 0038 H'1E1C 001C H'1E1C 002C H'1E1C 003C 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Common Configuration register
Free-running timer Control register IRQ status register 0 Channel 0 time register
CMTCH0T R/W
Channel 0 stop time register CMTCH0ST R/W Channel 0 timer/counter 1 Channel 1 time register CMTCH0C R/W CMTCH1T R/W
Channel 1 stop time register CMTCH1ST R/W Channel 1 timer/counter 2 Channel 2 time register CMTCH1C R/W CMTCH2T R/W
Channel 2 stop time register CMTCH2ST R/W Channel 2 timer/counter 3 Channel 3 time register CMTCH2C R/W CMTCH3T R/W
Channel 3 stop time register CMTCH3ST R/W Channel 3 timer/counter CMTCH3C R/W
Rev. 1.0, 02/03, page 524 of 1294
Table 16.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI Standby Manual Reset by by RESET Sleep Software/E Pin/WDT/ by Sleep ach Multiple Instruction/ by Deep Sleep Hardware Module Exception Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Ch.
Register Name
Abbrev. CMTCFG CMTFRT CMTCTL
Common Configuration register Free-running timer Control register IRQ status register 0 Channel 0 time register Channel 0 stop time register Channel 0 timer/counter 1 Channel 1 time register Channel 1 stop time register Channel 1 timer/counter 2 Channel 2 time register Channel 2 stop time register Channel 2 timer/counter 3 Channel 3 time register Channel 3 stop time register Channel 3 timer/counter
H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
CMTIRQS H'0000 0000 H'0000 0000 CMTCH0T H'0000 0000 H'0000 0000 CMTCH0ST H'0000 0000 H'0000 0000 CMTCH0C H'0000 0000 H'0000 0000 CMTCH1T H'0000 0000 H'0000 0000 CMTCH1ST H'0000 0000 H'0000 0000 CMTCH1C H'0000 0000 H'0000 0000 CMTCH2T H'0000 0000 H'0000 0000 CMTCH2ST H'0000 0000 H'0000 0000 CMTCH2C H'0000 0000 H'0000 0000 CMTCH3T H'0000 0000 H'0000 0000 CMTCH3ST H'0000 0000 H'0000 0000 CMTCH3C H'0000 0000 H'0000 0000
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
Rev. 1.0, 02/03, page 525 of 1294
16.3.1
Configuration Register (CMTCFG)
CMTCFG is a 32-bit readable/writable register. The possible operations for a pin are timer compare, timer input capture, up or down count, and capture input, where one pin is used for capture while the second is used to enable the count.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 ED3 0 R/W 0 R/W 30 R 14 29 R 13 ED2 0 R/W 0 R/W 28 R 12 27 R 11 ED1 0 R/W 0 R/W 26 R 10 25 R 9 ED0 0 R/W 0 R/W 24 R 8 23 R 7 0 R 22 R 6 21 R 5 20 R 4 19 R 3 T23 0 R/W 0 R/W 0 R/W 18 R 2 17 16
ROT2 ROT0 0 R/W 1 T01 0 R/W 0 R/W 0 R/W 0
FRCM FRTM 0 R/W 0 R/W
Bit
Bit Name
Initial Value --
R/W R
Description Reserved These bits can only be read from. The write value should always be 0. Channel 2, 3 Rotation Enable Only set to 1 when operating in updown-counter mode (T01=11, T23=011), otherwise this bit is disabled (ROT2=0). When this bit is set to 1, this indicates that pins of channels 2 and 3 are operating in rotary mode. This is an encoding of CMT_CTR2 pin and CMT_CTR3 pin to generate up and down signals to the counter. Counter 3 needs to be disabled by clearing to 0 the TE3 bit in CMTCTL. Channel 0,1 Rotation Enable Only set to 1 when operating in updown-counter mode (T01=11, T23=011), otherwise this bit is disabled (ROT0=0). When this bit is set to 1, this indicates that pins of channels 0 and 1 are operating in rotary mode. This is an encoding of CMT_CTR0 pin and CMT_CTR1 pin to generate up and down signals to the counter. Counter 1 needs to be disabled by clearing to 0 the TE1 bit in CMTCTL.
31 to 18 --
17
ROT2
0
R/W
16
ROT0
0
R/W
Rev. 1.0, 02/03, page 526 of 1294
Bit 15, 14
Bit Name ED3
Initial Value All 0
R/W R/W
Description Channel 3 Pin Active Control [Input capture mode] 00: Edge detection of CMT_CTR3 pin disabled 01: Edge detection on rising edge of CMT_CTR3 pin input 10: Edge detection on falling edge of CMT_CTR3 pin input 11: Edge detection on either edge of CMT_CTR3 pin input [Output compare mode] 1 00: Reserved* 01: 1 is output to CMT_CTR3 pin during active period 10: 0 is output to CMT_CTR3 pin during active period 11: Reserved Channel 2 Pin Active Control [Input capture mode] 00: Edge detection of CMT_CTR2 pin disabled 01: Edge detection on rising edge of CMT_CTR2 pin input 10: Edge detection on falling edge of CMT_CTR2 pin input 11: Edge detection on either edge of CMT_CTR2 pin input [Output compare mode] 1 00: Reserved* 01: 1 is output to CMT_CTR2 pin during active period 10: 0 is output to CMT_CTR2 pin during active period 11: Reserved
13, 12
ED2
All 0
R/W
11, 10
ED1
All 0
R/W
Channel 1 Pin Active Control [Input capture mode] 00: Edge detection of CMT_CTR1 pin disabled 01: Edge detection on rising edge of CMT_CTR1 pin input 10: Edge detection on falling edge of CMT_CTR1 pin input 11: Edge detection on either edge of CMT_CTR1 pin input [Output compare mode] 1 00: Reserved* 01: 1 is output to CMT_CTR1 pin during active period 10: 0 is output to CMT_CTR1 pin during active period 11: Reserved
Rev. 1.0, 02/03, page 527 of 1294
Bit 9, 8
Bit Name ED0
Initial Value All 0
R/W R/W
Description Channel 0 Pin Active Control [Input capture mode] 00: Edge detection of CMT_CTR0 pin disabled 01: Edge detection on rising edge of CMT_CTR0 pin input 10: Edge detection on falling edge of CMT_CTR0 pin input 11: Edge detection on either edge of CMT_CTR0 pin input [Output compare mode] 1 00: Reserved* 01: 1 is output to CMT_CTR0 pin during active period 10: 0 is output to CMT_CTR0 pin during active period 11: Reserved
7
--
0
R
Reserved This bit can only be read from. The write value should always be 0. Free-Running Control Mode In 16-bit timer/counter mode, when bits T23 are set to 100, this bit determines whether the up-counter uses a free-running counter or input capture on channel 3. 0: External clock (up-counter with input capture) 1: Internal clock (free-running up-counter)
6
FRCM
0
R/W
5
FRTM
0
R/W
Free-Running Timer Mode Determines whether the timer works as a common 32-bit free-running timer or four independent 16-bit timers/counters. When this bit is set to 1, settings of bits 4 to 0 in this register become disabled. 0: 16-bit timer/counter mode 1: 32-bit free-running timer (FRT) mode
Notes: *1 When these channels be used, be sure to set up values other than Reserved.
Rev. 1.0, 02/03, page 528 of 1294
Bit 4 to 2
Bit Name T23
Initial Value All 0
R/W R/W
Description Timer 2, 3 Configuration These bits are only used in 16-bit timer/counter mode. These bits control the use of CMT_CTR2 and CMT_CTR3 pins. CMT_CTR2 pin is mapped to timer 2/counter 2 and CMT_CTR3 pin is mapped to timer 3/counter 3. Configuration modes for channels 2 and 3: 000: Timers 2 and 3 001: Up-counter 2 and timer 3 010: Up-counters 2 and 3 011: Updown-counter 2 100: Up-counter with input capture 101: Reserved 110: Reserved 111: Reserved Note: Up-counter 2 is a sub-set of updown-counter 2.
1, 0
T01
All 0
R/W
Timer 0,1 Configuration These bits are only used in 16-bit timer/counter mode. These bits control the use of CMT_CTR0 and CMT_CTR1 pins. CMT_CTR0 pin is mapped to timer 0/counter 0 and CMT_CTR1 pin is mapped to timer 1/counter 1. Configuration modes for channels 0 and 1: 00: Timers 0 and 1 01: Up-counter 0 and timer 1 10: Up-counters 0 and 1 11: Updown-counter 0 Note: Up-counter 0 is a sub-set of updown-counter 0.
Rev. 1.0, 02/03, page 529 of 1294
16.3.2
Bit: Initial value: R/W: Bit: Initial value: R/W:
Free-Running Timer (CMTFRT)
31 30 29 28 27 26 25 24 FRT 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 FRT 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 23 22 21 20 19 18 17 16
Bit 31 to 0
Bit Name FRT
Initial Value All 0
R/W R
Description Free-Running Timer These bits indicate the current value of the free-running timer (FRT).
16.3.3
Control Register (CMTCTL)
CMTCTL is a 32-bit readable/writable register that controls interrupts, makes settings for the clocks, and selects the operating mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 TE3 0 R/W 15 CC3 0 R/W 0 R/W 30 TE2 0 R/W 14 29 TE1 0 R/W 13 CC2 0 R/W 0 R/W 28 TE0 0 R/W 12 27 IOE3 0 R/W 11 CC1 0 R/W 0 R/W 26 IOE2 0 R/W 10 25 IOE1 0 R/W 9 CC0 0 R/W 0 R/W 24 23 22 ICE2 0 R/W 6 SI2 0 R/W 21 ICE1 0 R/W 5 SI1 0 R/W 20 ICE0 0 R/W 4 SI0 0 R/W 19 IEE3 0 R/W 3 OP3 0 R/W 18 IEE2 0 R/W 2 OP2 0 R/W 17 IEE1 0 R/W 1 OP1 0 R/W 16 IEE0 0 R/W 0 OP0 0 R/W
IOE0 ICE3 0 R/W 8 0 R/W 7 SI3 0 R/W
Bit 31 30 29 28
Bit Name TE3 TE2 TE1 TE0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Timer Enable Enables the counting of each of the 16-bit counters. If these bits are inactive when operating in timer mode or in counter mode, the counters are reset to 0. In updown-counter mode, a counter for each pair (counter 1 or counter 3) needs to be disabled (TE1=0, TE3=0). 0: Counting disabled; counter will be reset to H'000 1: Counter is incremented
Rev. 1.0, 02/03, page 530 of 1294
Bit 27 26 25 24 23 22 21 20 19 18 17 16
Bit Name IOE3 IOE2 IOE1 IOE0 ICE3 ICE2 ICE1 ICE0 IEE3 IEE2 IEE1 IEE0
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Channel 3 to 0 Interrupt Overflow Enable These bits enable an interrupt to be generated when the relevant IOn bit is set in the IRQ status register. 0: Interrupt generation disabled 1: Interrupt generation enabled Channel 3 to 0 Interrupt Compare Enable These bits enable an interrupt to be generated when the relevant ICn bit is set in the IRQ status register. 0: Interrupt generation disabled 1: Interrupt generation enabled Channel 3 to 0 Interrupt Edge Enable These bits enable an interrupt to be generated when the relevant IEn bit is set in the IRQ status register. 0: Interrupt generation disabled 1: Interrupt generation enabled When a channel is in outup compare mode, the corresponding IEEn has to be set to 0.
15, 14
CC3
All 0
R/W
Timer Clock Control Channel 3 These bits specify the clock input for the 16-bit 1 timer/counter in channel 3.* 00: Clock for timer 3 is 1/32 of source clock 01: Clock for timer 3 is 1/128 of source clock 10: Clock for timer 3 is 1/512 of source clock 11: Clock for timer 3 is 1/1024 of source clock Set the same value as the CC0 bit when using 16bit input capture mode.
13, 12
CC2
All 0
R/W
Timer Clock Control Channel 2 These bits specify the clock input for the 16-bit 1 timer/counter in channel 2.* 00: Clock for timer 2 is 1/32 of source clock 01: Clock for timer 2 is 1/128 of source clock 10: Clock for timer 2 is 1/512 of source clock 11: Clock for timer 2 is 1/1024 of source clock Set the same value as the CC0 bit when using 16bit input capture mode.
Rev. 1.0, 02/03, page 531 of 1294
Bit 11, 10
Bit Name CC1
Initial Value All 0
R/W R/W
Description Timer Clock Control Channel 1 These bits specify the clock input for the 16-bit 1 timer/counter in channel 1.* 00: Clock for timer 1 is 1/32 of source clock 01: Clock for timer 1 is 1/128 of source clock 10: Clock for timer 1 is 1/512 of source clock 11: Clock for timer 1 is 1/1024 of source clock Set the same value as the CC0 bit when using 16bit input capture mode.
9, 8
CC0
All 0
R/W
Free-Running Timer Clock Control This clock is used for the 32-bit free-running timer (FRT) and also for the 16-bit timer/counter in 1 channel 0.* 00: Clock for FRT and timer 0 is 1/32 of source clock 01: Clock for FRT and timer 0 is 1/128 of source clock 10: Clock for FRT and timer 0 is 1/512 of source clock 11: Clock for FRT and timer 0 is 1/1024 of source clock
7 6 5 4
SI3 SI2 SI1 SI0
0 0 0 0
R/W R/W R/W R/W
Channel 3 to 0 Stop Ignore For the channel n, these bits determine whether in output compare mode with 32-bit free-running timer mode, the output remains active for half the maximum time or until the stop value is reached. 0: Output remains active until the channel n stop time value is reached 1: Output remains active for half the total time of the FRT
3 2 1 0
OP3 OP2 OP1 OP0
0 0 0 0
R/W R/W R/W R/W
Channel 3 to 0 Operation For the channel n, if in timer mode, these bits determine whether the timer is used in output compare or input capture mode. 0: Input capture mode 1: Output compare mode When a channel is in output compare mode, the corresponding IEEn bits has to be set to 0.
Note: n = 3 to 0 *1 The source clock is the peripheral clock (Pck). The clock which divided from the source clock is the timer/counter resolution of the channel.
Rev. 1.0, 02/03, page 532 of 1294
16.3.4
IRQ Status Register (CMTIRQS)
CMTIRQS, once set, can only be cleared by a write. Writing 0 to these bits clears the interrupt status bits. These conditions only create an interrupt if the relevant interrupt enable bit is set.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 IO3 0 R/W 26 0 R 10 IO2 0 R/W 25 0 R 9 IO1 0 R/W 24 0 R 8 IO0 0 R/W 23 0 R 7 IC3 0 R/W 22 0 R 6 IC2 0 R/W 21 0 R 5 IC1 0 R/W 20 0 R 4 IC0 0 R/W 19 0 R 3 IE3 0 R/W 18 0 R 2 IE2 0 R/W 17 0 R 1 IE1 0 R/W 16 0 R 0 IE0 0 R/W
Bit
Bit Name
Initial Value --
R/W R
Description Reserved These bits can only be read from. The write value should always be 0. Channel 3 to 0 Interrupt Overflow A bit for each channel indicates if the up-counters or updown-counters have wrapped i.e. overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF. 0: The count has not overflowed or underflowed 1: The count has overflowed or underflowed
31 to 12 --
11 10 9 8
IO3 IO2 IO1 IO0
0 0 0 0
R/W R/W R/W R/W
7 6 5 4
IC3 IC2 IC1 IC0
0 0 0 0
R/W R/W R/W R/W
Channel 3 to 0 Interrupt Compare A bit for each channel indicates whether in timer mode, the free-running timer has become equal to the channel times. 0: Timer has not become equal to the channel time value 1: Timer has become equal to the channel time value Channel 3 to 0 Interrupt Edge A bit for each channel indicates whether an edge that wil cause an action (active edge) has been defected. 0: Channel 3 to 0 has not received an active edge 1: Channel 3 to 0 has received an active edge
3 2 1 0
IE3 IE2 IE1 IE0
0 0 0 0
R/W R/W R/W R/W
Rev. 1.0, 02/03, page 533 of 1294
16.3.5
Channels 0 to 3 Time Registers (CMTCH0T to CMTCH3T)
In output compare mode, these registers specify the value to be compared with the free-running timer. In input capture mode, this register stores the free-running timer values or the 16-bit timer values on the active edge of the input. Every time an edge is detected, these registers are updated and the new captured value will be saved.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Channel n time 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Channel n time 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
16.3.6
Channels 0 to 3 Stop Time Registers (CMTCH0ST to CMTCH3ST)
In output compare mode, these registers specify the value to be compared with the free-running timer. When this value is reached, the timer output is reset to the inactive state.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Channel n stop time 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Channel n stop time 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
16.3.7
Bit: Initial value: R/W: Bit: Initial value: R/W:
Channels 0 to 3 Counters (CMTCH0C to CMTCH3C)
31 R 15 30 R 14 29 R 13 28 R 12 27 R 11 26 R 10 25 R 9 24 R 8 23 R 7 22 R 6 21 R 5 20 R 4 19 R 3 18 R 2 17 R 1 16 R 0
Channel n counter 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Rev. 1.0, 02/03, page 534 of 1294
Bit
Bit Name
Initial Value --
R/W R
Description Reserved These bits can only be read from. The write value should always be 0. Channel n Counter A register for each channel indicates the current value of the counters. This register can be written to for setting the counter values. Reading from these registers does not affect the count value.
31 to 16 --
15 to 0
Channel n counter
All 0
R/W
Note: n = 3 to 0
16.4
Operation
The timer consists of two sections of which the first is a 32-bit free-running timer for which the clock can be set to operate between approximately 1 MHz and 30 kHz. The second section consists of four 16-bit counters with the ability to count up and the ability to count down. This counting is controlled through edge detection on the input pins. The timer and counters can be used as counters which count based on inputs or can operate as timers with input capture/output compare. They differ from the 32-bit timer of the FRT in that they are reset to H'0000 when a capture or compare occurs on that channel. The timer/counter consists of four channels, each of which can be configured as a timer or a counter. In timer mode, each of the four channels has two operating modes: input capture mode and output compare mode. 16.4.1 Edge Detection
The timers and counters are based on edge detection on the input pins. An active edge can be programmed to be a rising edge, falling edge, or both edges. In addition, the edge detection logic can operate in rotary switch mode where the combination of two inputs indicates whether the switch has been turned right or left. This switch indicates increment or decrement of the updowncounter. Edge detection operating on two inputs functions as a pair. The outputs can either work independently for the timers or the up-counters or can work as pairs to indicate up and down to the updown-counters. In order for an edge to be detected, the pulse must last for at least two cycles of the clock divided from the source clock for that channel, as shown in figure 16.2.
Rev. 1.0, 02/03, page 535 of 1294
Pck
The clock divided from Pck input signal edge detection
Figure 16.2 Edge Detection The timing diagram in figure 16.2 shows an edge detection (rising edge). The input pin must be asserted for at least two clock resolution cycles. 16.4.2 32-Bit Timer: Input Capture
When operating in input capture mode, the channel will detect an edge on the input signal. The selection of rising or falling edge is programmable. When this edge is detected, the current value of the free-running timer (FRT) is captured into the channel time register for that channel. In addition, the interrupt edge bit for that channel will be set. In this case, if the interrupt enable bit for that channel is set, an interrupt will be generated.
Common between channels
Clock generation
32-bit free-running timer CMT_CTR Peripheral bus Multiplexer Edge detection
Channel time register
Edge control
IRQ
Figure 16.3 32-Bit Timer Mode: Input Capture
Rev. 1.0, 02/03, page 536 of 1294
16.4.3
32-Bit Timer: Output Compare
When operating in output compare mode, the channel time register is compared with the FRT. When the free-running timer becomes equal to the channel time register, the output will be set to the active state as defined in the pin active control bit. The output will remain in this state until the time reaches half of the maximum channel time, as shown in figure 16.4, or it reaches the channel stop time value specified by the corresponding stop ignore bit in the control register (CMTCTL). At the point where the channel time register is equal to the FRT, the interrupt compare bit will be set, and an interrupt generated if the interrupt enable bit is set.
FRT Active
Count
Note: The output is active until the free-running timer becomes half of the count value.
Figure 16.4 Output Pin Assertion Period
Common between channels
Clock generation
IRQ 32-bit free-running timer CMT_CTR FRT = Count Multiplexer Peripheral bus
Channel time register Preload
Figure 16.5 32-Bit Timer Mode: Output Compare
Rev. 1.0, 02/03, page 537 of 1294
16.4.4
16-Bit Timer: Input Capture
When operating in input capture mode, the 16-bit counters will be free-running using the clocks defined by the timer clock control bits. When an active edge defined by the pin active control bit is received, the channel time will be set to the value of that channel's 16-bit counter and the interrupt edge bit will be set. The counter will then be reset to H'0000 and will begin counting again. The counters will retain their values or can be cleared to H'0000 by disabling the timer enable bits. Channel 0 is always enabled for this mode. The other three channels will be enabled if they use the same clock source as channel 0.
Common between channels
Clock generation
16-bit counter CMT_CTR Peripheral bus
Edge detection
Channel time register
Edge control
IRQ
Figure 16.6 16-Bit Timer Mode: Input Capture
Rev. 1.0, 02/03, page 538 of 1294
16.4.5
16-Bit Timer: Output Compare
When operating in output compare mode, the 16-bit counters will be free-running using the clocks defined by the timer clock control bits. Bits 15 to 0 in the channel time register are compared with the 16-bit counter for that channel. When the values become equal, the output will be inverted from its current state (i.e. toggled), and the interrupt compare bit will be set. The counter will then be reset to H'0000 and will begin counting again. Each time a match on the counter occurs, the output will be toggled. The counters will retain their values or can be cleared to H'0000 by disabling the timer enable bits.
Common between channels
Clock generation
IRQ 16-bit counter CMT_CTR
FRT = Count
Peripheral bus
Channel time register
Preload
Figure 16.7 16-Bit Timer Mode: Output Compare
Rev. 1.0, 02/03, page 539 of 1294
16.4.6
Counter: Up-/Updown-Counter
Each of the pins can be connected to each of the four up-counters. These counters count up when an active edge is detected on the input pins. The counters can be written to by software to be preloaded and the current value can be read. Two up-counters can also be configured to count both up and down. In this case since two pins are required, the second up-counter within the pair is not available. The pins are then referred to as up (pins 0 and 2) and down (pins 1 and 3). An active edge on these pins will cause the counter either to count up or down, or if both edges are active then the count will remain unchanged. In either up-counter or updown-counter mode, the counter will generate an interrupt if an edge is detected or if the count overflows or underflows.
IRQ CMT_CTR Up Updown-counter CMT_CTR Down Pin B Edge detection IRQ Preload
Read
Pin A
Edge detection
Figure 16.8 Updown-Counter Mode
IRQ CMT_CTR Edge detection Up-counter Read
Figure 16.9 Up-Counter Mode
Rev. 1.0, 02/03, page 540 of 1294
16.4.7
Counter: Up-Counter with Capture
In this mode, the 16-bit counter of channel 2 will operate either as a free-running up-counter or as an up-counter with input capture, depending on the setting of the FRCM bit. If the FRCM bit is cleared to 0, the counter counts up when an active edge is detected on the input pin of channel 3. If the FRCM bit is set to 1, the counter is a free-running counter. The counter will retain its value or can be cleared to H'0000 by disabling the timer enable bit.
IRQ CMT_CTR Read
Pin A
Edge detection
Channel time register
CMT_CTR
Pin B
Edge detection MPX Internal clock FRCM Preload Up-counter
Figure 16.10 Up-Counter with Capture Mode 16.4.8 Interrupts
The Status Register will have the interrupt status bits set for timer operation on either input capture or output compare regardless of the state of the interrupt enable bits. The counters will set an interrupt status bit if the count changes or the counter underflows or overflows. If the interrupt enable bit for a type of interrupt and the interrupt status bit of the same type for the same channel is set then an interrupt is generated.
Rev. 1.0, 02/03, page 541 of 1294
16.4.9
Rotary Mode
Each of the two updown-counters can operate in rotary mode. This treats the two input signals as encoded, as shown in figure 16.11. A rotary switch generates the following waveforms depending on the direction. The direction is determined by the value of A when a falling edge is detected on the B input; if A is 1, the direction is left (down is 1) and if A is 0, the direction is right (up is 1). A is pin 0 and pin 2. B is pin 1 and pin 3. The interrupt edge bit in channels 3 to 0 will be set whenever a change in the counter value occurs. If a counter overflow or underflow occurs, the interrupt overflow bit in channels 3 to 0 will be set as well.
A (data) B (edge)
Right rotation
Left rotation
Figure 16.11 Rotary Mode 16.4.10 Timer Frequency The frequency of the free running timer and the 16-bit timers can be altered under software control to be 1 of 4 frequencies. Each 16-bit timer can have an independent clock. 16.4.11 Standby Mode CMT allows clock gating to reduce power consumption. The module standby mode can be executed by controlling bit 17 in the Clock Stop Register 00 (CLKSTP00). To wake up the module, bit 17 in the Clock Stop Clear Register 00 (CLKSTPCLR00) must be enabled. After enabling this bit all access to CMT can be possible. To power down the module, the following procedure is required. 1. 2. 3. All channels needs to be in input capture mode (CMTCTL.OP3 - OP0=0000). The active edge for each channel needs to be disabled (CMTCFG.ED3 - ED0=00). Disable bit 17 in the Clock Stop Register 00 (CLKSTP00).
Rev. 1.0, 02/03, page 542 of 1294
Section 17 Serial Communication Interface with FIFO (SCIF)
This LSI is equipped with a 3-channel serial communication interface with built-in FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform both asynchronous and synchronous serial communications. 128-stage FIFO buffers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. Channels 1 and 2 have modem control functions (SCIF1_RTS, SCIF2_RTS, SCIF1_CTS, and SCIF2_CTS).
17.1
Features
The SCIF has the following features. * Asynchronous serial communication mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). There is a choice of 8 serial data transfer formats. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even/odd/none Receive error detection: Parity, framing, and overrun errors Break detection: A break is detected when a framing error lasts for more than 1 frame length at Space 0 (low level). When a framing error occurs, a break can also be detected by reading the SCIF_RXD pin level directly from the serial port register (SCSPTR). * Synchronous serial communication mode Serial data communication is synchronized with a clock. Serial data communication can be carried out with other LSIs that have a synchronous communication function. There is a single serial data communication format. Data length: 8 bits Receive error detection: Overrun errors
Rev. 1.0, 02/03, page 543 of 1294
* Full-duplex communication capability The transmitter and receiver are independent units, enabling transmission and reception to be performed simultaneously. The transmitter and receiver both have a 128-stage FIFO buffer structure, enabling continuous serial data transmission and reception. * On-chip baud rate generator allows any bit rate to be selected. * Choice of serial clock source: internal clock from baud rate generator or external clock from SCIF_CLK pin * Four interrupt sources There are four interrupt sources--transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error--that can issue requests independently. * The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. * When not in use, the SCIF can be stopped by halting its clock supply to reduce power consumption. * In asynchronous mode, modem control functions (SCIF_RTS and SCIF_CTS) are provided.(only in channels 1 and 2) * The amount of data in the transmit/receive FIFO registers, and the number of receive errors in the receive data in the receive FIFO register, can be ascertained. * In asynchronous mode, a timeout error (DR) can be detected during reception. Figure 17.1 shows a block diagram of the SCIF. Figures 17.2 to 17.6 show block diagrams of the I/O ports in SCIF. There are three channels in this LSI. In figures 17.1 to 17.6, the channels are omitted and explained. Note that the SCIF_CTS and SCIF_RTS pins are available only in channels 1 and 2 and not in channel 0.
Rev. 1.0, 02/03, page 544 of 1294
SCFRDRn (128-stage)
SCFTDRn (128-stage)
SCIFn_RXD
SCRSRn
SCTSRn
SCSMRn SCLSRn SCTFDRn SCRFDRn SCFCRn SCFSRn SCSCRn SCSPTRn SCRERn Transmission/ reception control
SCBRRn
Bus interface
Module data bus
Peripheral bus
Pck Baud rate generator Pck/4 Pck/16 Pck/64 Clock
SCIFn_TXD Parity generation Parity check SCIFn_CLK SCIFn_CTS SCIFn_RTS
External clock TXIn RXIn ERIn BRIn SCIF
Note: n = 0 to 2 Channel 0 does not have SCIF0_CTS and SCIF0_RTS. Legend: SCRSRn SCBRRn :Bit rate register :Receive shift register SCFRDRn :Receive FIFO data register SCSPTRn :Serial port register SCTSRn SCFCRn :FIFO control register :Transmit shift register SCFTDRn :Transmit FIFO data register SCTFDRn :Transmit FIFO data count register SCSMRn :Serial mode register SCRFDRn :Receive FIFO data count register SCSCRn SCLSRn :Line status register :Serial control register SCFSRn SCRERn :Serial error register :Serial status register
Figure 17.1 Block Diagram of SCIF Figures 17.2 to 17.6 show block diagrams of the I/O ports in SCIF.
Rev. 1.0, 02/03, page 545 of 1294
Reset
R D7 Q D RTSIO C
Peripheral bus
SPTRW SCIF_RTS Reset
R D6 Q D RTSDT C
SPTRW
Modem control enable signal* SCIF_RTS signal
SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF_RTS pin function is designated as modem control by the MCE bit in SCFCR.
Figure 17.2 SCIF_RTS Pin (Only in Channels 1 and 2)
Reset
R Q D CTSIO C
D5 Peripheral bus
SPTRW SCIF_CTS Reset
R Q D CTSDT C
D4
SPTRW SCIF_CTS signal Modem control enable signal*
SPTRR
SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF_CTS pin function is designated as modem control by the MCE bit in SCFCR.
Figure 17.3 SCIF_CTS Pin (Only in Channels 1 and 2) CIF_CTS
Rev. 1.0, 02/03, page 546 of 1294
Reset R Q D SCKIO C SPTRW Reset SCIF_CLK R Q D SCKDT C SPTRW Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* D2 D3 Peripheral bus
SPTRR SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF_CLK pin function is designated as internal clock output or external clock input by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Figure 17.4 SCIF_CLK Pin
Reset R Q D SPB2IO C SPTRW SCIF_TXD Reset R Q D SPB2DT C SPTRW D0 D1 Peripheral bus
Transmit enable signal
Serial transmit data SPTRW: Write to SCSPTR
Figure 17.5 SCIF_TXD Pin
Rev. 1.0, 02/03, page 547 of 1294
SCIF_RXD
Serial receive data
Peripheral bus SPTRR SPTRR: Read from SCSPTR
Figure 17.6 SCIF_RXD Pin
17.2
Input/Output Pins
Table 17.1 shows the SCIF pin configuration. Since the pin functions are the same in each channel, the channel number is omitted in the description below. The modem control pins are available only in channels 1 and 2, and not in channel 0. Table 17.1 Pin Configuration
Pin Name Serial clock pin Receive data pin Transmit data pin Modem control pin Modem control pin Abbreviation SCIF0_CLK to SCIF2_CLK SCIF0_RXD to SCIF2_RXD SCIF0_TXD to SCIF2_TXD SCIF1_CTS, SCIF2_CTS SCIF1_RTS, SCIF2_RTS I/O Input/Output Input/Output Input/Output Input/Output Input/Output Function Clock input/output Receive data input Transmit data output Transmission enabled Transmission request
Note: These pins are made to function as serial pins by performing SCIF operation settings with the C/A bit in SCSMR, the TE, RE, CKE1, and CKE0 bits in SCSCR, and the MCE bit in SCFCR. Break state transmission and detection can be set in SCSPTR of the SCIF.
Rev. 1.0, 02/03, page 548 of 1294
17.3
Register Descriptions
The SCIF has the following registers. Since the register functions are the same in each channel, the channel number is omitted in the description below. For details on the addresses of these registers and the state of registers in each operating mode, see section 32, List of Registers. Table 17.2 Register Configuration (1)
Ch. Register Name 0 Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit FIFO data register 0 Serial status register 0 Receive FIFO data register 0 FIFO control register 0 Transmit FIFO data count register 0 Receive FIFO data count register 0 Serial port register 0 Line status register 0 Serial error register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit FIFO data register 1 Serial status register 1 Receive FIFO data register 1 FIFO control register 1 Transmit FIFO data count register 1 Receive FIFO data count register 1 Serial port register 1 Line status register 1 Abbrev. SCSMR0 SCBRR0 SCSCR0 R/W R/W R/W R/W P4 Address H'FE60 0000 H'FE60 0004 H'FE60 0008 H'FE60 000C
1
Area 7 Address Size H'1E60 0000 H'1E60 0004 H'1E60 0008 H'1E60 000C H'1E60 0010 H'1E60 0014 H'1E60 0018 H'1E60 001C H'1E60 0020 H'1E60 0024 H'1E60 0028 H'1E60 002C H'1E61 0000 H'1E61 0004 H'1E61 0008 H'1E61 000C H'1E61 0010 H'1E61 0014 H'1E61 0018 H'1E61 001C H'1E61 0020 H'1E61 0024 H'1E61 0028 16 8 16 8 16 8 16 16 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
SCFTDR0 W SCFSR0 R/W*
H'FE60 0010 H'FE60 0014 H'FE60 0018 H'FE60 001C H'FE60 0020 H'FE60 0024
SCFRDR0 R SCFCR0 R/W
SCTFDR0 R/W SCRFDR0 R/W SCSPTR0 R/W SCLSR0 SCRER0 SCSMR1 SCBRR1 SCSCR1 R/W* R R/W R/W R/W
4
H'FE60 0028 H'FE60 002C H'FE61 0000 H'FE61 0004 H'FE61 0008 H'FE61 000C
SCFTDR1 W SCFSR1 R/W*
1
H'FE61 0010 H'FE61 0014 H'FE61 0018 H'FE61 001C H'FE61 0020 H'FE61 0024
SCFRDR1 R SCFCR1 R/W
SCTFDR1 R/W SCRFDR1 R/W SCSPTR1 R/W SCLSR1 R/W*
4
H'FE61 0028
Rev. 1.0, 02/03, page 549 of 1294
Ch. Register Name 1 2 Serial error register 1 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit FIFO data register 2 Serial status register 2 Receive FIFO data register 2 FIFO control register 2 Transmit FIFO data count register 2 Receive FIFO data count register 2 Serial port register 2 Line status register 2 Serial error register 2
Abbrev. SCRER1 SCSMR2 SCBRR2 SCSCR2
R/W R R/W R/W R/W
P4 Address H'FE61 002C H'FE62 0000 H'FE62 0004 H'FE62 0008 H'FE62 000C
1
Area 7 Address Size H'1E61 002C H'1E62 0000 H'1E62 0004 H'1E62 0008 H'1E62 000C H'1E62 0010 H'1E62 0014 H'1E62 0018 H'1E62 001C H'1E62 0020 H'1E62 0024 H'1E62 0028 H'1E62 002C 16 16 8 16 8 16 8 16 16 16 16 16 16
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
SCFTDR2 W SCFSR2 R/W*
H'FE62 0010 H'FE62 0014 H'FE62 0018 H'FE62 001C H'FE62 0020 H'FE62 0024
SCFRDR2 R SCFCR2 R/W
SCTFDR2 R/W SCRFDR2 R/W SCSPTR2 R/W SCLSR2 SCRER2 R/W* R
4
H'FE62 0028 H'FE62 002C
Table 17.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'0000 H'FF H'0000 Standby Manual Reset by RESET by Sleep Software/ by Sleep Pin/WDT/ Each Instruction/ by Multiple Exception Deep Sleep Hardware Module H'0000 H'FF H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Ch. Register Name 0 Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit FIFO data register 0 Serial status register 0 Receive FIFO data register 0 FIFO control register 0 Transmit FIFO data count register 0 Receive FIFO data count register 0 Serial port register 0 Line status register 0
Abbrev. SCSMR0 SCBRR0 SCSCR0
SCFTDR0 Undefined Undefined SCFSR0 H'0060 H'0060
SCFRDR0 Undefined Undefined SCFCR0 H'0000 H'0000 H'0000 H'0000 H'0000*2 H'0000
SCTFDR0 H'0000 SCRFDR0 H'0000 SCSPTR0 H'0000*2 SCLSR0 H'0000
Rev. 1.0, 02/03, page 550 of 1294
Ch. Register Name 0 1 Serial error register 0 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit FIFO data register 1 Serial status register 1 Receive FIFO data register 1 FIFO control register 1 Transmit FIFO data count register 1 Receive FIFO data count register 1 Serial port register 1 Line status register 1 Serial error register 1 2 Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit FIFO data register 2 Serial status register 2 Receive FIFO data register 2 FIFO control register 2 Transmit FIFO data count register 2 Receive FIFO data count register 2 Serial port register 2 Line status register 2 Serial error register 2
Abbrev. SCRER0 SCSMR1 SCBRR1 SCSCR1
Power-on Reset by RESET Pin/WDT/ H-UDI H'0000 H'0000 H'FF H'0000
Standby Manual Reset by by RESET Sleep Software/ by Sleep Pin/WDT/ Each Multiple Instruction/ by Deep Sleep Hardware Module Exception H'0000 H'0000 H'FF H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
SCFTDR1 Undefined Undefined SCFSR1 H'0060 H'0060
SCFRDR1 Undefined Undefined SCFCR1 H'0000 H'0000 H'0000 H'0000
SCTFDR1 H'0000 SCRFDR1 H'0000
SCSPTR1 H'0000*3 H'0000*3 SCLSR1 SCRER1 SCSMR2 SCBRR2 SCSCR2 H'0000 H'0000 H'0000 H'FF H'0000 H'0000 H'0000 H'0000 H'FF H'0000
SCFTDR2 Undefined Undefined SCFSR2 H'0060 H'0060
SCFRDR2 Undefined Undefined SCFCR2 H'0000 H'0000 H'0000 H'0000
SCTFDR2 H'0000 SCRFDR2 H'0000
SCSPTR2 H'0000*3 H'0000*3 SCLSR2 SCRER2 H'0000 H'0000 H'0000 H'0000
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. *1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0. *2. Bits 2 and 0 are undefined. *3. Bits 6, 4, 2,and 0 are undefined. *4. To clear the flag, 0 can only be written to bit 0. Rev. 1.0, 02/03, page 551 of 1294
17.3.1
Receive Shift Register (SCRSR)
SCRSR is the register used to receive serial data. The SCIF sets serial data input from the SCIF_RXD pin in SCRSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to SCFRDR, automatically. SCRSR cannot be directly read from and written to by the CPU.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-
-
-
-
-
-
-
-
17.3.2
Receive FIFO Data Register (SCFRDR)
SCFRDR is an 8-bit FIFO register of 128 stages that stores received serial data. When the SCIF has received one byte of serial data, it transfers the received data from SCRSR to SCFRDR where it is stored, and completes the receive operation. SCRSR is then enabled for reception, and consecutive receive operations can be performed until SCFRDR is full (128 data bytes). SCFRDR is a read-only register, and cannot be written to by the CPU. If a read is performed when there is no receive data in SCFRDR, an undefined value will be returned. When SCFRDR is full of receive data, subsequent serial data is lost.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
R
R
R
R
R
R
R
R
Rev. 1.0, 02/03, page 552 of 1294
17.3.3
Transmit Shift Register (SCTSR)
SCTSR is the register used to transmit serial data. To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR to SCTSR, then sends the data to the SCIF_TXD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from SCFTDR to SCTSR, and transmission started, automatically. SCTSR cannot be directly read from and written to by the CPU.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
-
-
-
-
-
-
-
-
17.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is an 8-bit FIFO register of 128 stages that stores data for serial transmission. If SCTSR is empty when transmit data has been written to SCFTDR, the SCIF transfers the transmit data written in SCFTDR to SCTSR and starts serial transmission. SCFTDR is a write-only register, and cannot be read by the CPU. The next data cannot be written when SCFTDR is filled with 128 bytes of transmit data. Data written in this case is ignored.
Bit: 7 6 5 4 3 2 1 0
Initial value: R/W:
W
W
W
W
W
W
W
W
Rev. 1.0, 02/03, page 553 of 1294
17.3.5
Serial Mode Register (SCSMR)
SCSMR is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate generator clock source. SCSMR can always be read from and written to by the CPU.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 0 R 1 0
CKS1 CKS0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Communication Mode Selects asynchronous mode or synchronous mode as the SCIF operating mode. 0: Asynchronous mode 1: Synchronous mode
7
C/A
0
R/W
6
CHR
0
R/W
Character Length Selects 7 or 8 bits as the asynchronous mode data length. In synchronous mode, the data length is fixed at 8 bits regardless of the CHR bit setting. When 7-bit data is selected, the MSB (bit 7) of SCFTDR is not transmitted. 0: 8-bit data 1: 7-bit data
Rev. 1.0, 02/03, page 554 of 1294
Bit 5
Bit Name PE
Initial Value 0
R/W R/W
Description Parity Enable In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking is performed in reception. In synchronous mode, parity bit addition and checking is disabled regardless of the PE bit setting. 0: Parity bit addition and checking disabled 1: Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.
4
O/E
0
R/W
Parity Mode Selects either even or odd parity for use in parity addition and checking. In asynchronous mode, the O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking. In synchronous mode or when parity addition and checking is disabled in asynchronous mode, the O/E bit setting is invalid. 0: Even parity 1: Odd parity When even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd.
Rev. 1.0, 02/03, page 555 of 1294
Bit 3
Bit Name STOP
Initial Value 0
R/W R/W
Description Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit setting is valid only in asynchronous mode. Since the stop bit is not added in synchronous mode, the STOP bit setting is invalid. 0: 1 stop bit* 2 1: 2 stop bits* In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Note: *1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. *2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent.
1
2
--
0
R
Reserved This bit is always read as 0. The write value should always be 0. Clock Select 1 and 0 These bits select the clock source for the on-chip baud rate generator. The clock source can be selected from Pck, Pck/4, Pck/16, and Pck/64, according to the setting of bits CKS1 and CKS0. For details of the relationship between clock sources, bit rate register settings, and baud rate, see section17.3.8, Bit Rate Register (SCBRR). 00: Pck clock 01: Pck/4 clock 10: Pck/16 clock 11: Pck/64 clock
1 0
CKS1 CKS0
0 0
R/W R/W
Note : Pck = Peripheral Clock
Rev. 1.0, 02/03, page 556 of 1294
17.3.6
Serial Control Register (SCSCR)
SCSCR is a register used to enable/disable transmission/reception by SCIF, serial clock output, interrupt requests, and to select transmission/reception clock source for the SCIF. SCSCR can always be read from and written to by the CPU.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 REIE 0 R/W 2 0 R 1 0
CKE1 CKE0 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Transmit Interrupt Enable Enables or disables transmit-FIFO-data-empty interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR falls to or below the transmit trigger set number, and the TDFE flag in SCFSR is set to 1. TXI interrupt requests can be cleared using the following methods: Either by reading 1 from the TDFE flag, writing transmit data exceeding the transmit trigger set number to SCFTDR and then clearing the TDFE flag to 0, or by clearing the TIE bit to 0. 0: Transmit-FIFO-data-empty interrupt (TXI) request disabled 1: Transmit-FIFO-data-empty interrupt (TXI) request enabled
7
TIE
0
R/W
Rev. 1.0, 02/03, page 557 of 1294
Bit 6
Bit Name RIE
Initial Value 0
R/W R/W
Description Receive Interrupt Enable Enables or disables generation of a receive-datafull interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt (ERI) request when the ER flag in SCFSR is set to 1, and a break interrupt (BRI) request when the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1. 0: Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request disabled 1: Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI) request, and break interrupt (BRI) request enabled Note: An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0.
5
TE
0
R/W
Transmit Enable Enables or disables the start of serial transmission by the SCIF. Serial transmission is started when transmit data is written to SCFTDR while the TE bit is set to 1. 0: Transmission disabled 1: Transmission enabled* Note: SCSMR and SCFCR settings must be made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set to 1.
Rev. 1.0, 02/03, page 558 of 1294
Bit 4
Bit Name RE
Initial Value 0
R/W R/W
Description Receive Enable Enables or disables the start of serial reception by the SCIF. Serial reception is started when a start bit is detected in this state in asynchronous mode or a synchronization clock is input while the RE bit is set to 1. It should be noted that clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER flags, which retain their states. Serial reception begins once the start bit is detected in these states. 0: Reception disabled 1: Reception enabled* Note*: SCSMR and SCFCR settings must be made, the reception format decided, and the receive FIFO reset, before the RE bit is set to 1.
3
REIE
0
R/W
Receive Error Interrupt Enable Enables or disables generation of receive-error interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the RIE bit is 0. Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is to be notified of ERI and BRI interrupt requests. 0: Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled 1: Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
2
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 559 of 1294
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_CLK pin. The CKE1 and CKE0 bits are used together to specify whether the SCIF_CLK pin functions as a serial clock output pin or a serial clock input pin. Note however that the CKE0 bit setting is valid only when an internal clock is selected as the SCIF clock source (CKE1 = 0). When an external clock is selected (CKE1 = 1), the CKE0 bit setting is invalid. The CKE1 and CKE0 bits must be set before determining the SCIF's operating mode with SCSMR. * Asynchronous mode 00: Internal clock/SCIF_CLK pin functions as port 01: Internal clock/SCIF_CLK pin functions as 1 clock output* 1X: External clock/SCIF_CLK pin functions as 2 clock input* * Synchronous mode 0X: Internal clock/SCIF_CLK pin functions as synchronization clock output 1X: External clock/SCIF_CLK pin functions as synchronization clock input
Notes: X: Don't care *1. Outputs a clock with a frequency 16 times the bit rate. *2. Inputs a clock with a frequency 16 times the bit rate.
17.3.7
Serial Status Register (SCFSR)
SCFSR is a 16-bit register that consists of status flags that indicate the operating status of the SCIF. SCFSR can be read from or written to by the CPU at all times. However, 1 cannot be written to flags ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 ER 6 5 4 3 FER 0 R 2 PER 0 R 1 RDF 0 DR
TEND TDFE BRK
0 1 1 0 R/W*1 R/W*1 R/W*1 R/W*1
0 0 R/W*1 R/W*1
Rev. 1.0, 02/03, page 560 of 1294
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
7
ER
0
R/W*
Receive Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR, and reception continues. The FER and PER bits in SCFSR can be used to determine whether there is a receive error in the readout data from SCFRDR. 0: No framing error or parity error occurred during reception [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ER after reading ER = 1
1: A framing error or parity error occurred during reception [Setting conditions] * When the SCIF checks whether the stop bit at the end of the receive data is 1 when 2 reception ends, and the stop bit is 0*
* When, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SCSMR
Rev. 1.0, 02/03, page 561 of 1294
Bit 6
Bit Name TEND
Initial Value 1
R/W R/W*
1
Description Transmit End Indicates that transmission has been ended without valid data in SCFTDR on transmission of the last bit of the transmit character. 0: Transmission is in progress [Clearing conditions] * When transmit data is written to SCFTDR, and 0 is written to TEND after reading TEND =1 When data is written to SCFTDR by the DMAC
*
1: Transmission has been ended [Setting conditions] * * * Power-on reset or manual reset When the TE bit in SCSCR is 0 When there is no transmit data in SCFTDR on transmission of the last bit of a 1-byte serial transmit character
Rev. 1.0, 02/03, page 562 of 1294
Bit 5
Bit Name TDFE
Initial Value 1
R/W R/W*
1
Description Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data number set by bits TTRG1 and TTRG0 in SCFCR, and new transmit data can be written to SCFTDR. 0: A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR [Clearing conditions] * When transmit data exceeding the transmit trigger set number is written to SCFTDR after reading TDFE = 1, and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC
*
1: The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number [Setting conditions] * * Power-on reset or manual reset When the number of SCFTDR transmit data bytes falls to or below the transmit trigger set 3 number as the result of a transmit operation*
Notes: *1. Only 0 can be written, to clear the flag. *2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. *3. As SCFTDR is a 128-byte FIFO register, the maximum number of bytes that can be written when TDFE = 1 is 128 - (transmit trigger set number). Data written in excess of this will be ignored. The upper bits of SCFDR indicate the number of data bytes transmitted to SCFTDR.
Rev. 1.0, 02/03, page 563 of 1294
Bit 4
Bit Name BRK
Initial Value 0
R/W R/W*
1
Description Break Detect Indicates that a receive data break signal has been detected. 0: A break signal has not been received [Clearing conditions] * * Power-on reset or manual reset When 0 is written to BRK after reading BRK =1
2
1: A break signal has been received* [Setting condition] *
When data with a framing error is received, followed by the space "0" level (low level ) for at least one frame length
3
FER
0
R
Framing Error In asynchronous mode, indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR. 0: There is no framing error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no framing error in the data that is to be read next from SCFRDR
1: There is a framing error that is to be read from SCFRDR [Setting condition] * When there is a framing error in the data that is to be read next from SCFRDR
Rev. 1.0, 02/03, page 564 of 1294
Bit 2
Bit Name PER
Initial Value 0
R/W R
Description Parity Error In asynchronous mode, indicates whether or not a parity error has been found in the data that is to be read next from SCFRDR. 0: There is no parity error that is to be read from SCFRDR [Clearing conditions] * * Power-on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR
1: There is a parity error in the receive data that is to be read from SCFRDR [Setting condition] * 1 RDF 0 R/W*
1
When there is a parity error in the data that is to be read next from SCFRDR
Receive FIFO Data Full Indicates that the received data has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. 0: The number of receive data bytes in SCFRDR is less than the receive trigger set number [Clearing conditions] * * Power-on reset or manual reset When SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF = 1, and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number
*
1: The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number [Setting condition] * When SCFRDR contains at least the receive 3 trigger set number of receive data bytes*
Rev. 1.0, 02/03, page 565 of 1294
Bit 0
Bit Name DR
Initial Value 0
R/W R/W*
1
Description Receive Data Ready In asynchronous mode, indicates that there are fewer than the receive trigger set number of data bytes in SCFRDR, and no further data has arrived for at least 15 etu after the stop bit of the last data received. This is not set when using synchronous mode. 0: Reception is in progress or has ended normally and there is no receive data left in SCFRDR [Clearing conditions] * * Power-on reset or manual reset When all the receive data in SCFRDR has been read after reading DR = 1, and 0 is written to DR When all the receive data in SCFRDR has been read by the DMAC
*
1: No further receive data has arrived [Setting condition] * When SCFRDR contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data 4 received*
etu: Elementary time unit (time for transfer of 1 bit) Notes: *1. Only 0 can be written, to clear the flag. *2. When a break is detected, the receive data (H'00) following detection is not transferred to SCFRDR. When the break ends and the receive signal returns to mark "1", receive data transfer is resumed. *3. SCFRDR is a 128-byte FIFO register. When RDF = 1, at least the receive trigger set number of data bytes can be read. If all the data in SCFRDR is read and another read is performed, the data value will be undefined. The number of receive data bytes in SCFRDR is indicated by SCRFDR. *4. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
Rev. 1.0, 02/03, page 566 of 1294
17.3.8
Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that set the serial transmission/reception bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR. SCBRR can always be read from and written to by the CPU. The SCBRR setting is found from the following equation. Asynchronous mode:
N= Pck 64 x 22n-1 x B x 106 - 1
Synchronous mode:
N= Pck x 106 - 1 8 x 22n-1 x B
Where B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 N 255) Pck: Peripheral module operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See table 17.3 for the relation between n and the clock.) Table 17.3 SCSMR Settings
SCSMR Setting n 0 1 2 3 Clock Pck Pck/4 Pck/16 Pck/64 CKS1 0 0 1 1 CKS0 0 1 0 1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) = Pck x 106 -1 (N + 1) x B x 64 x 22n-1 x 100
Rev. 1.0, 02/03, page 567 of 1294
17.3.9
FIFO Control Register (SCFCR)
SCFCR performs data count resetting and trigger data number setting for transmit and receive FIFO registers, and also contains a loopback test enable bit. SCFCR can always be read from and written to by the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10
RST 1 RG2*
9
RST 1 RG1*
8
7
6
5
4
3
2
1
0
RST 1 1 RTRG1 RTRG0 TTRG1 TTRG0 MCE* TFRST RFRST LOOP RG0*
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. SCIF_RTS Output Active Trigger The SCIF_RTS signal becomes high when the number of receive data stored in SCFRDR exceeds the trigger number shown below. 000:127 001:1 010:16 011:32 100:64 101:96 110:108 111:120
15 to 11 --
10 9 8
RSTRG2*1 RSTRG1*1 RSTRG0*1
0 0 0
R/W R/W R/W
7 6
RTRG1 RTRG0
0 0
R/W R/W
Receive FIFO Data Number Trigger These bits are used to set the number of receive data bytes that sets the RDF flag in SCFSR. The RDF flag is set when the number of receive data bytes in SCFRDR is equal to or greater than the trigger set number shown below. 00:1 01:16 10:64 11:96
Rev. 1.0, 02/03, page 568 of 1294
Bit 5 4
Bit Name TTRG1 TTRG0
Initial Value 0 0
R/W R/W R/W
Description Transmit FIFO Data Number Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when the number of transmit data bytes in SCFTDR is equal to or less than the trigger set number shown below. 00:64 (64)*2 01:32 (96) 10:4 (124) 11:0 (128)
3
MCE*1
0
R/W
Modem Control Enable Enables the SCIF_CTS and SCIF_RTS modem control signals. Always set the MCE bit to 0 in synchronous mode. 0: Modem signals disabled*3 1: Modem signals enabled
2
TFRST
0
R/W
Transmit FIFO Data Register Reset Invalidates the transmit data in the transmit FIFO data register and resets it to the empty state. 0: Reset operation disabled*4 1: Reset operation enabled
1
RFRST
0
R/W
Receive FIFO Data Register Reset Invalidates the receive data in the receive FIFO data register and resets it to the empty state. 0: Reset operation disabled*4 1: Reset operation enabled
0
LOOP
0
R/W
Loopback Test Internally connects the transmit output pin (SCIF_TXD) and receive input pin (SCIF_RXD), and the SCIF_RTS pin and SCIF_CTS pin, enabling loopback testing. 0: Loopback test disabled 1: Loopback test enabled
Rev. 1.0, 02/03, page 569 of 1294
Notes: *1. Reserved bit in channel 0. *2. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set. *3. SCIF_CTS is fixed at active-0 regardless of the input value, and SCIF_RTS output is also fixed at 0. *4. A reset operation is performed in the event of a power-on reset or manual reset.
17.3.10 Transmit FIFO Data Count Register (SCTFDR) SCTFDR is a 16-bit register that indicates the number of transmit data bytes stored in SCFTDR. SCTFDR can always be read from the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 T7 0 R 6 T6 0 R 5 T5 0 R 4 T4 0 R 3 T3 0 R 2 T2 0 R 1 T1 0 R 0 T0 0 R
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. These bits show the number of untransmitted data bytes in SCFTDR. A value of H'0000 indicates that there is no transmit data, and a value of H'0080 indicates that SCFTDR is full of transmit data.
7 to 0
T7 to T0
All 0
R
17.3.11 Receive FIFO Data Count Register (SCRFDR) SCRFDR is a 16-bit register that indicates the number of receive data bytes stored in SCFRDR. SCRFDR can always be read from the CPU.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 R7 0 R 6 R6 0 R 5 R5 0 R 4 R4 0 R 3 R3 0 R 2 R2 0 R 1 R1 0 R 0 R0 0 R
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 570 of 1294
Bit 7 to 0
Bit Name R7 to R0
Initial Value All 0
R/W R
Description These bits show the number of receive data bytes in SCFRDR. A value of H'0000 indicates that there is no receive data, and a value of H'0080 indicates that SCFRDR is full of receive data.
17.3.12 Serial Port Register (SCSPTR) SCSPTR is a 16-bit readable/writable register that controls input/output and data for the port pins multiplexed with the serial communication interface (SCIF) pins at all times. Input data can be read from the SCIF_RXD pin, output data written to the SCIF_TXD pin, and breaks in serial transmission/reception controlled, by means of bits 1 and 0. All SCSPTR bits except bits 6, 4, 2, and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is undefined. SCSPTR is not initialized in standby mode or in the module standby state. Note that when reading data via a serial port pin in the SCIF, the peripheral clock value from 2 cycles before is read.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 RT SIO* 0 R/W 6 5 4 3 RT CT CT SCK SDT* SIO* SDT* IO 0 0 R/W R/W R/W R/W 2 1 0 SCK SPB2 SPB2 DT IO DT 0 R/W R/W R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Serial Port SCIF_RTS Port Input/Output Specifies the serial port SCIF_RTS pin input/output condition. When actually setting the SCIF_RTS pin as a port output pin to output the value set by the RTSDT bit, the MCE bit in SCFCR should be cleared to 0. 0: RTSDT bit value is not output to SCIF_RTS pin 1: RTSDT bit value is output to SCIF_RTS pin
7
RTSIO*
0
R/W
Rev. 1.0, 02/03, page 571 of 1294
Bit 6
Bit Name RTSDT*
Initial Value --
R/W R/W
Description Serial Port SCIF_RTS Port Data Specifies the serial port SCIF_RTS pin input/output data. Input or output is specified by the RTSIO bit. In output mode, the RTSDT bit value is output to the SCIF_RTS pin. The SCIF_RTS pin value is read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
5
CTSIO*
0
R/W
Serial Port SCIF_CTS Port Input/Output Specifies the serial port SCIF_CTS pin input/output condition. When actually setting the SCIF_CTS pin as a port output pin to output the value set by the CTSDT bit, the MCE bit in SCFCR should be cleared to 0. 0: CTSDT bit value is not output to SCIF_CTS pin 1: CTSDT bit value is output to SCIF_CTS pin
4
CTSDT*
--
R/W
Serial Port SCIF_CTS Port Data Specifies the serial port SCIF_CTS pin input/output data. Input or output is specified by the CTSIO bit. In output mode, the CTSDT bit value is output to the SCIF_CTS pin. The SCIF_CTS pin value is read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
Rev. 1.0, 02/03, page 572 of 1294
Bit 3
Bit Name SCKIO
Initial Value 0
R/W R/W
Description Serial Port Clock Port Input/Output Specifies the serial port SCIF_CLK pin input/output condition. When actually setting the SCIF_CLK pin as a port output pin to output the value set by the SCKDT bit, the CKE1 and CKE0 bits in SCSCR should be cleared to 0. 0: SCKDT bit value is not output to SCIF_CLK pin 1: SCKDT bit value is output to SCIF_CLK pin
2
SCKDT
--
R/W
Serial Port Clock Port Data Specifies the serial port SCIF_CLK pin input/output data. Input or output is specified by the SCKIO bit. In output mode, the SCKDT bit value is output to the SCIF_CLK pin. The SCIF_CLK pin value is read from the SCKDT bit regardless of the value of the SCKIO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
1
SPB2IO
0
R/W
Serial Port Break Input/Output Specifies the serial port SCIF_TXD pin output condition. When actually setting the SCIF_TXD pin as a port output pin to output the value set by the SPB2DT bit, the TE bit in SCSCR should be cleared to 0. 0: SPB2DT bit value is not output to the SCIF_TXD pin 1: SPB2DT bit value is output to the SCIF_TXD pin
0
SPB2DT
--
R/W
Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output data. The SCIF_TXD pin output condition is specified by the SPB2IO bit. When the SCIF_TXD pin is designated as an output, the value of the SPB2DT bit is output to the SCIF_TXD pin. The SCIF_RXD pin value is read from the SPB2DT bit regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or manual reset is undefined. 0: Input/output data is low-level 1: Input/output data is high-level
Note: * Only channels 1 and 2. Reserved bit in channel 0.
Rev. 1.0, 02/03, page 573 of 1294
17.3.13 Line Status Register (SCLSR)
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ORER 0 R/W*1
Bit 15 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
0
ORER
0
R/W*
Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Reception in progress, or reception has ended 2 normally* [Clearing conditions] * * Power-on reset or manual reset When 0 is written to ORER after reading ORER = 1
3
1: An overrun error occurred during reception* [Setting condition] *
When the next serial reception is completed while SCFRDR receives 128-byte data (SCFRDR is full)
Notes: *1. Only 0 can be written, to clear the flag. *2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0. *3. The receive data prior to the overrun error is retained in SCFRDR, and the data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1.
Rev. 1.0, 02/03, page 574 of 1294
17.3.14 Serial Error Register (SCRER) SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR. SCRER can always be read from the CPU.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 FER7 FER6 FER5 FER4 FER3 FER2 FER1 FER0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 15 14 13 12 11 10 9 8
Bit Name PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0
Initial Value 0 0 0 0 0 0 0 0
R/W R R R R R R R R
Description Number of Parity Errors These bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits PER7 to PER0 is the number of data bytes in which a parity error occurred. If all 128 bytes of receive data in SCFRDR have parity errors, the value indicated by bits PER7 to PER0 will be 0. Number of Framing Errors These bits indicate the number of data bytes in which a framing error occurred in the receive data stored in SCFRDR. After the ER bit in SCFSR is set, the value indicated by bits FER7 to FER0 is the number of data bytes in which a framing error occurred. If all 128 bytes of receive data in SCFRDR have framing errors, the value indicated by bits FER7 to FER0 will be 0.
7 6 5 4 3 2 1 0
FER7 FER6 FER5 FER4 FER3 FER2 FER1 FER0
0 0 0 0 0 0 0 0
R R R R R R R R
Rev. 1.0, 02/03, page 575 of 1294
17.4
17.4.1
Operation
Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is achieved character by character and in synchronous mode, in which synchronization is achieved with clock pulses. For details on asynchronous mode, see section 17.4.2, Operation in Asynchronous Mode. 128-stage FIFO buffers are provided for both transmission and reception, reducing the CPU overhead, and enabling fast and continuous communication to be performed. SCIF_RTS and SCIF_CTS signals are also provided as modem control signals. The serial transfer format is selected using SCSMR, as shown in table 17.4. The SCIF clock source is determined by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR, as shown in table 17.5. Asynchronous Mode: * Data length: Choice of 7 or 8 bits * Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receivedata-ready state, and breaks, during reception * Indication of the number of data bytes stored in the transmit and receive FIFO registers * Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and can output a clock with frequency of 16 times the bit rate. When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used). Synchronous Mode: * Data length: Fixed at 8 bits * Detection of overrun errors during reception * Choice of internal or external clock as SCIF clock source When internal clock is selected: The SCIF operates on the baud rate generator clock and a serial clock is output to external devices. When external clock is selected: The on-chip baud rate generator is not used and the SCIF operates on the input serial clock.
Rev. 1.0, 02/03, page 576 of 1294
Table 17.4 SCSMR Settings for Serial Transfer Format Selection
SCSMR Settings Bit 7: C/A A 0 Bit 6: CHR 0 Bit 5: PE 0 Bit 3: STOP 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Synchronous mode 8-bit data No Note: * Don't care Yes 7-bit data No Yes Mode Asynchronous mode SCIF Transfer Format Data Length 8-bit data Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No
Table 17.5 SCSMR and SCSCR Settings for SCIF Clock Source Selection
SCSMR Bit 7: C/A A 0 SCSCR Settings Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCIF_CLK Pin Function SCIF does not use SCIF_CLK pin Outputs clock with frequency of 16 times the bit rate External Inputs clock with frequency of 16 times the bit rate Outputs synchronization clock
External
Inputs synchronization clock
Rev. 1.0, 02/03, page 577 of 1294
17.4.2
Operation in Asynchronous Mode
In asynchronous mode, a character that consists of data with a start bit indicating the start of communication and a stop bit indicating the end of communication is transmitted or received. In this mode, serial communication is performed with synchronization achieved character by character. Inside the SCIF, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and receiver have a 128-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception. Figure 17.7 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCIF monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One character in serial communication consists of a start bit (low level), followed by transmit/receive data (LSB-first; from the lowest bit), a parity bit (high or low level), and finally stop bits (high level). In reception in asynchronous mode, the SCIF synchronizes with the fall of the start bit. Receive data can be latched at the middle of each bit because the SCIF samples data at the eighth clock which has a frequency of 16 times the bit rate.
Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 17.7 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, and Two Stop Bits)
Rev. 1.0, 02/03, page 578 of 1294
(1) Data Transfer Format Table 17.6 shows the data transfer formats that can be used. Any of 8 transfer formats can be selected according to the SCSMR settings. Table 17.6 Serial Transfer Formats (Asynchronous Mode)
SCSMR Settings
CHR PE 0 0 STOP 0 1 S 2
Serial Transfer Format and Frame Length
3 4 5 8-bit data 6 7 8 9 10 STOP 11 12
0
0
1
S
8-bit data
STOP STOP
0
1
0
S
8-bit data
P
STOP
0
1
1
S
8-bit data
P
STOP STOP
1
0
0
S
7-bit data
STOP
1
0
1
S
7-bit data
STOP STOP
1
1
0
S
7-bit data
P
STOP
1
1
1
S
7-bit data
P
STOP STOP
Legend: S : Start bit STOP : Stop bit P : Parity bit
Rev. 1.0, 02/03, page 579 of 1294
(2) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCIF_CLK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 17.5. When an external clock is input at the SCIF_CLK pin, the clock frequency should be 16 times the bit rate used. When the SCIF is operated on an internal clock, a clock whose frequency is 16 times the bit rate is output from the SCIF_CLK pin. (3) SCIF Initialization (Asynchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. 1. 2. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in SCFSR has been set. TEND can also be cleared to 0 during transmission, but the data being transmitted will go to the mark state after the clearance. Before setting TE again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case.
3.
Figure 17.8 shows a sample SCIF initialization flowchart.
Rev. 1.0, 02/03, page 580 of 1294
Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0 bits, and MCE in SCFCR, and clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits No
[1] Set the clock selection in SCSCR. Be sure to clear bits TIE, RIE, TE, and RE to 0. [2] Set the data transfer format in SCSMR. [3] Write a value corresponding to the bit rate into SCBRR. (Not necessary if an external clock is used.) [4] Wait at least one bit interval, then set the TE bit or RE bit in SCSCR to 1. Also set the RIE, REIE, and TIE bits. Setting the TE and RE bits enables the SCIF_TXD and SCIF_RXD pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit.
[1]
[2]
[3]
[4]
End of initialization
Figure 17.8 Sample SCIF Initialization Flowchart
Rev. 1.0, 02/03, page 581 of 1294
(4) Serial Data Transmission (Asynchronous Mode) Figure 17.9 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE and TEND flags to 0. The number of transmit data bytes that can be written is 128 - (transmit trigger set number). [2] Serial transmission continuation procedure: No [2] To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR, and then clear the TDFE flag to 0. [3] Break output at the end of serial transmission: No To output a break in serial transmission, clear the SPB2DT bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear the TE bit in SCSCR to 0. In [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR indicated by SCTFDR.
Read TDFE bit in SCFSR No
TDFE = 1? Yes Write transmit data in SCFTDR, and clear TDFE bit and TEND bit in SCFSR to 0
[1]
All data transmitted? Yes Read TEND bit in SCFSR
TEND = 1? Yes Break output? Yes Clear SPB2DT to 0 and set SPB2IO to 1 Clear TE bit in SCSCR to 0
No
[3]
End of transmission
Figure 17.9 Sample Serial Transmission Flowchart In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 128 - (transmit trigger setting).
Rev. 1.0, 02/03, page 582 of 1294
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated. The serial transmit data is sent from the SCIF_TXD pin in the following order. A. Start bit: One 0-bit is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. A format in which a parity bit is not output can also be selected. D. Stop bit(s): One or two 1-bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data after the stop bit is sent, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output from the SCIF_TXD pin. Figure 17.10 shows an example of the operation for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1 Serial data
1 Idle state (mark state)
TDFE
TEND TXI interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler One frame TXI interrupt request
Figure 17.10 Sample SCIF Transmission Operation (Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 1.0, 02/03, page 583 of 1294
4. When modem control is enabled, transmission can be stopped and restarted in accordance with the SCIF_CTS input value. When SCIF_CTS is set to 1 during transmission , the line goes to the mark state after transmission of one frame. When SCIF_CTS is set to 0, the next transmit data is output starting from the start bit. Figure 17.11 shows an example of the operation when modem control is used.
Start bit Serial data SCIF_TXD 0 D0 D1 Parity Stop bit bit D7 0/1 Start bit 0 D0 D1 D7 0/1
SCIF_CTS
Drive high before stop bit
SCIF_CTS) Figure 17.11 Sample Operation Using Modem Control (SCIF_CTS SCIF_CTS (Only in Channels 1 and 2)
Rev. 1.0, 02/03, page 584 of 1294
(5) Serial Data Reception (Asynchronous Mode) Figure 17.12 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception.
[1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the SCIF_RXD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: All data received? Yes Clear RE bit in SCSCR to 0 End of reception [3] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from SCRFDR.
Start of reception
Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR
[1]
ER, DR, BRK or ORER = 1? No Read RDF flag in SCFSR No
Yes
Error handling [2]
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
Figure 17.12 Sample Serial Reception Flowchart (1)
Rev. 1.0, 02/03, page 585 of 1294
Error handling No
ORER = 1? Yes Overrun error handling
[1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data (H'00) is not transferred to SCFRDR. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. When a break handling is completed and a receive signal returns to 1, the receive data transfer resumes.
No
ER = 1? Yes Receive error handling
No
BRK = 1? Yes Break handling
No
DR = 1? Yes Read receive data in SCFRDR
Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0
End
Figure 17.12 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0-start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from SCRSR to SCFRDR.*
Rev. 1.0, 02/03, page 586 of 1294
C. Overrun error check: The SCIF checks that the ORER flag is 0, indicating that no overrun error has occurred.* D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set.* If (b), (c), and (d) checks are passed, the receive data is stored in SCFRDR. Note: Reception continues even when a parity error or framing error occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit or REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 17.13 shows an example of the operation for reception in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0/1 D0 D1 Data D7 Parity Stop bit bit 0/1 0 0/1
1 Serial data
RDF
FER RXI interrupt request One frame
Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler
ERI interrupt request generated by receive error
Figure 17.13 Sample SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty. When SCIF_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger number.The SCIF_RTS output active trigger value is specified by bits 10 to 8 in the FIFO control register (SCFCR). For details, see section 17.3.9, FIFO control register (SCFCR). In addition, SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0. Figure 17.14 shows an example of the operation when modem control is used.
Rev. 1.0, 02/03, page 587 of 1294
Start bit Serial data SCIF_RXD 0 D0 D1 D2
Parity Stop bit bit D7 0/1 1
Start bit 0
SCIF_RTS
SCIF_RTS) Figure 17.14 Sample Operation Using Modem Control (SCIF_RTS SCIF_RTS (Only in Channels 1 and 2) 17.4.3 Operation in Synchronous Mode
Synchronous mode, in which data is transmitted or received in synchronization with clock pulses, is suitable for fast serial communication. Since the transmitter and receiver are independent units in the SCIF, full-duplex communication can be achieved by sharing the clock. Both the transmitter and receiver have a 128-stage FIFO buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer and reception. Figure 17.15 shows the general format for synchronous communication.
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 17.15 Data Format in Synchronous Communication In synchronous serial communication, data on the communication line is output from one fall of the synchronization clock to the next fall. Data is guaranteed to be accurate at the start of the synchronization clock. In serial communication, each character is output starting with the LSB and ending with the MSB. After the MSB is output, the communication line remains in the state of the last data. In synchronous mode, the SCIF receives data in synchronization with the rise of the synchronization clock.
Rev. 1.0, 02/03, page 588 of 1294
(1) Data Transfer Format A fixed 8-bit data format is used. No parity bit can be added. (2) Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCIF_CLK pin can be selected as the SCIF's serial clock, according to the settings of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details of SCIF clock source selection, see table 17.5. When the SCIF is operated on an internal clock, the synchronization clock is output from the SCIF_CLK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When an internal clock is selected in a receive operation only, as long as the RE bit in SCSCR is set to 1, clock pulses are output until the number of receive data bytes in the receive FIFO data register reaches the receive trigger number. (3) SCIF Initialization (Synchronous Mode) Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0, then initialize the SCIF as described below. When changing the operating mode or transfer format, etc., the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the RE bit to 0 does not initialize the RDF, PER, FER, or ORER flag state or change the contents of SCFRDR. Figure 17.16 shows a sample SCIF initialization flowchart.
Rev. 1.0, 02/03, page 589 of 1294
Start of initialization
Clear TE and RE bits in SCSCR to 0 Set TFRST and RFRST bits in SCFCR to 1 to clear the FIFO buffer After reading BRK, DR, and ER flags in SCFSR, write 0 to clear them Set CKE1 and CKE0 bits in SCSCR (leaving TE, RE, TIE, and RIE bits cleared to 0) Set data transfer format in SCSMR Set value in SCBRR Wait 1-bit interval elapsed? Yes Set RTRG1-0 and TTRG1-0 bits in SCFCR, and clear TFRST and RFRST bits to 0 Set external pins to be used (SCIF_CLK, SCIF_TXD, and SCIF_RXD) Set TE and RE bits in SCSCR to 1, and set TIE, RIE, and REIE bits
[1]
[1] Leave the TE and RE bits cleared to 0 until the initialization almost ends. Be sure to clear the TIE, RIE, TE, and RE bits to 0. [2] Set the CKE1 and CKE0 bits. [3] Set the data transfer format in SCSMR. [4] Write a value corresponding to the bit rate into SCBRR. This is not necessary if an external clock is used. Wait at least one bit interval after this write before moving to the next step.
[2]
[3]
[5] Set the external pins to be used. Set SCIF_RXD input for reception and SCIF_TXD output for transmission. The input/output of the SCIF_CLK pin must match the setting of the CKE1 and CKE0 bits. [6] Set the TE or RE bit in SCSCR to 1. Also set the TIE, RIE, and REIE bits to enable the SCIF_TXD, SCIF_RXD, and SCIF_CLK pins to be used. When transmitting, the SCIF_TXD pin will go to the mark state. When receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the SCIF_CLK pin at this point.
[4]
No
[5]
[6]
End of initialization
Figure 17.16 Sample SCIF Initialization Flowchart
Rev. 1.0, 02/03, page 590 of 1294
(4) Serial Data Transmission (Synchronous Mode) Figure 17.17 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Initialization Start of transmission
[1]
[1] SCIF initialization: See sample SCIF initialization flowchart in figure 17.16. [2] SCIF status check and transmit data write:
Read TDFE bit in SCFSR No
[2]
TDFE = 1? Yes Write transmit data to SCFTDR and clear TDFE bit and TEND bit in SCFSR to 0
Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Serial transmission continuation procedeure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0.
All data transmitted? Yes Read TEND flag in SCFSR
No
[3]
TEND = 1? Yes Clear TE bit in SCSCR to 0
No
End of transmission
Figure 17.17 Sample Serial Transmission Flowchart In serial transmission, the SCIF operates as described below. 1. When data is written into SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmitting. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is at least 128 (transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls to or below the transmit trigger number set in SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFOdata-empty interrupt (TXI) request is generated.
Rev. 1.0, 02/03, page 591 of 1294
If clock output mode is selected, the SCIF outputs eight synchronization clock pulses for each data. When the external clock is selected, data is output in synchronization with the input clock. The serial transmit data is sent from the SCIF_TXD pin in the LSB-first order. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit. 4. After serial transmission ends, the SCIF_CLK pin is fixed high. Figure 17.18 shows an example of the operation for transmission in synchronous mode.
Synchronization clock Serial data LSB Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TDFE
TEND
TXI Data written to SCFTDR TXI interrupt interrupt and TDFE flag cleared to 0 request request by TXI interrupt handler
One frame
Figure 17.18 Sample SCIF Transmission Operation in Synchronous Mode
Rev. 1.0, 02/03, page 592 of 1294
(5) Serial Data Reception (Synchronous Mode) Figure 17.19 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching the operating mode from asynchronous mode to synchronous mode without initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags are cleared to 0.
[1] SCIF initialization: Initialization Start of reception [1] See Sample SCIF Initialization Flowchart in figure 17.16. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1. [2] No Read RDF flag in SCFSR No Error handling [3] [3] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial reception continuation procedure: [4] To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading SCRFDR.
Read ORER flag in SCLSR
ORER = 1?
Yes
RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0
No
All data received? Yes Clear RE bit in SCSCR to 0 End of reception
Figure 17.19 Sample Serial Reception Flowchart (1)
Rev. 1.0, 02/03, page 593 of 1294
Error handling No
ORER = 1? Yes Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 17.19 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF is initialized internally in synchronization with the input or output of the synchronization clock. 2. The received data is stored in SCRSR in LSB-to-MSB order. After receiving the data, the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an overrun error is detected in the error check, reception cannot continue. 3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI) request is generated. Figure 17.20 shows an example of the operation for reception in synchronous mode.
Synchronization clock Serial data Bit 7 LSB Bit 0 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RDF
ORER
RXI interrupt request Data read from RXI interrupt SCFRDR and RDF request flag cleared to 0 by RXI interrupt handler BRI interrupt request by overrun error
One frame
Figure 17.20 Sample SCIF Reception Operation in Synchronous Mode
Rev. 1.0, 02/03, page 594 of 1294
(6) Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 17.21 shows a sample flowchart for simultaneous serial data transmission and reception. Use the following procedure for simultaneous serial transmission and reception after enabling the SCIF for both transmission and reception.
[1] SCIF initialization: See Sample SCIF Initialization Flowchart in figure 17.16. Start of transmission and reception [2] SCIF status check and transmit data write: [2] Read SCFSR and check that the TDFE flag is set to 1, then write transmit data to SCFTDR, and clear the TDFE flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [4] SCIF status check and receive data read: Yes [3] No Read RDF flag in SCFSR Error handling Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission and reception continuation procedure: RDF = 1? Yes Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 [4] To continue serial transmission and reception, read RDF flag and SCFRDR, and clear the RDF flag to 0 before receiving the MSB in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0.
Initialization
[1]
Read TDFE flag in SCFSR
No
TDFE = 1? Yes Write transmit data to SCFTDR, and clear TDFE flag in SCFSR to 0
Read ORER flag in SCLSR
ORER = 1?
No
No
All data received? Yes Clear TE and RE bits in SCSCR to 0 [5]
End of transmission and reception
Note: When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1.
Figure 17.21 Sample Simultaneous Serial Transmission and Reception Flowchart
Rev. 1.0, 02/03, page 595 of 1294
17.5
SCIF Interrupt Sources and the DMAC
The SCIF has four interrupt sources: transmit-FIFO-data-empty interrupt (TXI) request, receiveerror interrupt (ERI) request, receive-FIFO-data-full interrupt (RXI) request, and break interrupt (BRI) request. Table 17.7 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. If the TDFE flag in SCFSR is set to 1 when a TXI interrupt is enabled by the TIE bit, a TXI interrupt request and a transmit-FIFO-data-empty request for DMA transfer are generated. If the TDFE flag is set to 1 when a TXI interrupt is disabled by the TIE bit, only a transmit-FIFO-dataempty request for DMA transfer is generated. A transmit-FIFO-data-empty request can activate the DMAC to perform data transfer. If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit, an RXI interrupt request and a receive-FIFO-data-full request for DMA transfer are generated. If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit, only a receive-FIFOdata-full request for DMA transfer is generated. A receive-FIFO-data-full request can activate the DMAC to perform data transfer. Note that generation of an RXI interrupt request or a receiveFIFO-data-full request by setting the DR flag to 1 occurs only in asynchronous mode. When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is generated. If transmission/reception is carried out using the DMAC, set and enable the DMAC before making the SCIF settings. Also make settings to inhibit output of RXI and TXI interrupt requests to the interrupt controller. If output of interrupt requests is enabled, these interrupt requests to the interrupt controller can be cleared by the DMAC regardless of the interrupt handler. By setting the REIE bit to 1 while the RIE bit is cleared to 0 in SCSCR, it is possible to output ERI interrupt requests, but not RXI interrupt requests.
Rev. 1.0, 02/03, page 596 of 1294
Table 17.7 SCIF Interrupt Sources
Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive FIFO data full flag (RDF) or receive data ready flag (DR)* DMAC Activation Not possible Possible Priority on Reset Release High
Interrupt initiated by break flag (BRK) or overrun Not possible error flag (ORER) Interrupt initiated by transmit FIFO data empty flag (TDFE) Possible Low
Note: *An RXI interrupt by setting of the DR flag is available only in asynchronous mode.
17.6
Usage Notes
Note the following when using the SCIF. (1) SCFTDR Writing and the TDFE Flag The TDFE flag in SCFSR is set when the number of transmit data bytes written in SCFTDR has fallen to or below the transmit trigger number set by bits TTRG1 and TTRG0 in SCFCR. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again, even after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from SCTFDR. (2) SCFRDR Reading and the RDF Flag The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR. After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes read in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again even if it is cleared to 0. After the receive data is read, clear the RDF flag readout to 0 in order to reduce the number of data bytes in SCFRDR to less than the trigger number. The number of receive data bytes in SCFRDR can be found from SCRFDR.
Rev. 1.0, 02/03, page 597 of 1294
(3) Break Detection and Processing If a framing error (FER) is detected, break signals can also be detected by reading the SCIF_RXD pin value directly. In the break state the input from the SCIF_RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Although the SCIF stops transferring receive data to SCFRDR after receiving a break, the receive operation continues. (4) Sending a Break Signal The input/output condition and level of the SCIF_TXD pin are determined by bits SPB2IO and SPB2DT in SCSPTR. This feature can be used to send a break signal. After the serial transmitter is initialized and until the TE bit is set to 1 (enabling transmission), the SCIF_TXD pin function is not selected and the value of the SPB2DT bit substitutes for the mark state. The SPB2IO and SPB2DT bits should therefore be set to 1 (designating output and high level) in the beginning. To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low level), and then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized, regardless of the current transmission state, and 0 is output from the SCIF_TXD pin. (5) Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode, the SCIF operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 17.22.
Rev. 1.0, 02/03, page 598 of 1294
16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 Base clock -7.5 clocks +7.5 clocks
Receive data (SCIF_RXD)
Start bit
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 17.22 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.0, 02/03, page 599 of 1294
Thus, the reception margin in asynchronous mode is given by formula (1).
M= (0.5 1 2N ) - (L - 0.5) F | D - 0.5 | (1 + F) x 100 % ..................... (1) N
M: N: D: L: F:
Receive margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2). When D = 0.5 and F = 0:
M = (0.5 - 1 / (2 x 16) ) x 100% = 46.875% .......................................................... (2)
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. (6) When Using the DMAC When using an external clock as the synchronization clock, after SCFTDR is updated by the DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR (see figure 17.23).
SCIF_CLK t TDFE
SCIF_TXD
D0
D1
D2
D3
D4
D5
D6
D7
Note: When the SCIF is operated on an external clock, set t > 4.
Figure 17.23 Example of Synchronization Clock Transfer by DMAC
Rev. 1.0, 02/03, page 600 of 1294
Section 18 SIM Card Module (SIM)
The smart card interface supports IC cards (smart cards) conforming to the ISO/IEC 7816-3 (Identification Card) specification.
18.1
Features
The SIM has the following features. * Communication functions Asynchronous half-duplex transmission Protocol selectable between T = 0 and T = 1 modes Data length: 8 bits Parity bit generation and check Extra guard time selectable Output clock cycles per etu selectable Transmission of error signal (parity error) in receiver mode with T = 0 Detection of error signal and automatic character repetition in transmitter mode with T = 0 Minimum character interval 11 etu selectable for T = 1 Direct convention/inverse convention selectable Output clock fixable in high or low state * Baud rate freely specifiable with internal baud rate generator * Four types of interrupt factor Transmit data empty, receive data full, transmit/receive error, transmission complete * DMA transfer The direct memory access controller (DMAC) can be activated to be used for data transfer using a transmit data empty DMA transfer request or a receive data full DMA transfer request. The receiver can observe the interval between the start of two successive characters. [Legend] etu (elementary time unit): Time for 1-bit transfer
Rev. 1.0,02/03, page 601 of 1294
Figure 18.1 shows a block diagram of the SIM.
SIM internal bus
Bus interface
Peripheral bus
SIRDR
SITDR
SISMR Transmit/ receive control SISCR SISSR SISCMR SISC2R SIWAIT SIGRD
SIBRR SISMPL Baud rate generator
SIRSR Parity check SIM_D SIM_CLK
SITSR Parity generation
Pck Serial clock ERI TXI RXI TEI Receive data full Interrupt controller
SIM_RST SISCMR : Smart card mode register SIRSR : Receive shift register SIRDR : Receive data register SITSR : Transmit shift register SITDR : Transmit data register SISMR : Serial mode register SISCR : Serial control register SISC2R SISSR SIBRR SIWAIT SIGRD SISMPL
Transmit data empty : Serial control 2 register : Serial status register : Bit rate register : Wait time register : Guard extension register : Sampling register
DMA controller
Figure 18.1 Block Diagram of SIM
18.2
Input/Output Pins
The pin configuration of the SIM is shown in table 18.1. Table 18.1 Pin Configuration
Name Transmit/receive data Clock output Smart card reset Abbreviation SIM_D SIM_CLK SIM_RST I/O Input/Output Output Output Function
Transmit/receive data input/output
Clock output Smart card reset output
Rev. 1.0,02/03, page 602 of 1294
18.3
Register Descriptions
SIM has the following registers. For the addresses of these registers and the register states in various processing states, refer to section 32, List of Registers. Table 18.2 Register Configuration (1)
Register Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial control 2 register Wait time register Guard extension register Sampling register Abbrev. SISMR SIBRR SISCR SITDR SISSR SIRDR SISCMR SISC2R SIWAIT SIGRD SISMPL R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W P4 Address H'FE48 0000 H'FE48 0002 H'FE48 0004 H'FE48 0006 H'FE48 0008 H'FE48 000A H'FE48 000C H'FE48 000E H'FE48 0010 H'FE48 0012 H'FE48 0014 Area 7 Address H'1E48 0000 H'1E48 0002 H'1E48 0004 H'1E48 0006 H'1E48 0008 H'1E48 000A H'1E48 000C H'1E48 000E H'1E48 0010 H'1E48 0012 H'1E48 0014 Size 8 8 8 8 8 8 8 8 16 8 16 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0,02/03, page 603 of 1294
Table 18.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'20 H'07 H'00 H'FF H'84 H'00 H'01 H'00 H'0000 H'00 H'0173 Manual Reset by RESET Pin/WDT/ Multiple Exception H'20 H'07 H'00 H'FF H'84 H'00 H'01 H'00 H'0000 H'00 H'0173 Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Register Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial control 2 register Wait time register Guard extension register Sampling register
Abbrev. SISMR SIBRR SISCR SITDR SISSR SIRDR SISCMR SISC2R SIWAIT SIGRD SISMPL
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin.
Rev. 1.0,02/03, page 604 of 1294
18.3.1
Serial Mode Register (SISMR)
SISMR is an 8-bit readable/writable register that selects settings for the communication format of the smart card interface.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 PE 1 R 4 O/E 0 R/W 3 0 R 2 0 R 1 0 R 0 0 R
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0. Parity Enable This bit is always read as 1.The write value should always be 1. Parity Mode Selects whether even or odd parity is to be used when adding a parity bit and checking parity. 0: Even parity* 2 1: Odd parity*
1
5
PE
1
R
4
O/E
0
R/W
Notes: *1. When even parity is specified, the
transmitter will add a parity bit if the number of transmitted characters (1s) is odd, so that the total number of set bits (1s) is always even.
The receiver checks whether the total number of set bits (1s), including a parity bit and received characters, is even. *2. When odd parity is specified, the
transmitter will add a parity bit if the number of transmitted characters (1s) is even, so that the total number of set bits (1s) is always odd.
The receiver checks whether the total number of set bits (1s), including a parity bit and received characters, is odd. 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0,02/03, page 605 of 1294
18.3.2
Bit Rate Register (SIBRR)
SIBRR is an 8-bit readable/writable register that sets the transmission/reception bit rate.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 1 0
BRR2 BRR1 BRR0 1 R/W 1 R/W 1 R/W
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
Explanation Reserved These bits are always read as 0. The write value should always be 0. These bits set the transmit/receive bit rates 2 to 0.
2 1 0
BRR2 BRR1 BRR0
1 1 1
R/W R/W R/W
The SIBRR setting can be determined from the following formula.
SIM_CLK = Pck 2 (brr + 1)
The units of Pck (peripheral clock) and SIM_CLK output clock are MHz. brr is the value specified in BRR[2:0]. 18.3.3 Serial Control Register (SISCR)
SISCR is an 8-bit readable/writable register that enables or disables transmission or reception operation, the serial clock output, and interrupt requests for the smart card interface.
Bit: 7 TIE Initial value: R/W: 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 3 2 1 0
WAIT TEIE CKE1 CKE0 _IE 0 0 0 0 0 R/W R/W R/W R/W R/W
Rev. 1.0,02/03, page 606 of 1294
Bit 7
Bit Name TIE
Initial Value 0
R/W R/W
Description Transmit Interrupt Enable Enables or disables transmit data empty interrupt (SIMTXI) requests when serial transmit data is transferred from SITDR to SITSR, and the TDRE flag in SISSR is set to 1. 0: Disables transmit data empty interrupt (SIMTXI) requests* 1: Enables transmit data empty interrupt (SIMTXI) requests Note: * SIMTXI can be canceled by clearing either the TDRE flag or TIE to 0.
6
RIE
0
R/W
Receive interrupt enable Enables or disables receive data full interrupt (SIMRXI) requests, and transmit/receive error interrupt (SIMERI) requests due to parity errors, overrun errors, and error signal status, when serial receive data is transferred from SIRSR to SIRDR, and the RDRF flag in SISSR register is set to 1. 0: Disables receive data full interrupt (SIMRXI) requests 12 and transmit/receive error interrupt (SIMERI) requests* * 1: Enables receive data full interrupt (SIMRXI) requests 2 and transmit/receive error interrupt (SIMERI) requests* Notes *1. SIMRXI and SIMERI interrupt requests can be canceled by clearing the RDRF flag or the PER, ORER or ERS flag or the RIE bit to 0. *2. Wait error interrupt (SIMERI) requests are enabled and disabled using the WAIT_IE bit in SISCR.
5
TE
0
R/W
Transmit Enable Enables/disables serial transmission operations. 0: Disables transmission* 2 1: Enables transmission*
1
Notes: *1. The TDRE flag in SISSR register is fixed at 1. *2. In this state, if transmit data is written to SITDR, the transmission operation is started. Before setting the TE bit to 1, SISMR and SISCMR must always be set to determine the transmission format.
Rev. 1.0,02/03, page 607 of 1294
Bit 4
Bit Name RE
Initial Value 0
R/W R/W
Description Receive Enable Enables/disables serial reception. 0: Disables reception* 2 1: Enables reception*
1
Notes: *1. Note that clearing the RE bit to 0 has no effect on the RDRF, PER, ERS, ORER, or WAIT_ER flags. The state of these flags will be maintained. *2. If the start bit is detected in this state, serial reception is initiated. Before setting the RE bit to 1, SISMR and SISCMR registers must always be set, to determine the reception format. 3 WAIT_IE 0 R/W Wait Enable Enables or disables wait error interrupt requests. 0: Disables wait error interrupt (SIMERI) requests 1: Enables wait error interrupt (SIMERI) requests 2 TEIE 0 R/W Transmit end interrupt enable Enables or disables transmission end interrupt (SIMTEI) requests when transmission ends and the TEND flag is set to 1. 0: Disables transmission end interrupt (SIMTEI) requests* 1: Enables transmission end interrupt (SIMTEI) requests* Note: * After the 1 in the TDRE flag in SISSR is read, SIMTEI can be cancelled either by writing transmit data to SITDR and then clearing the TEND bit, or by clearing the TEIE bit to 0. 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 Select the clock source for the smart card interface, and enables or disables clock output from the SIM_CLK pin. 00: Output pin fixed at low level output 01: Output pin set for clock output 10: Output pin fixed at high level output 11: Output pin set for clock output
Rev. 1.0,02/03, page 608 of 1294
18.3.4
Transmit Shift Register (SITSR)
SITSR is a shift register for transmitting serial data. The smart card interface transfers transmit data from SITDR to the SITSR register, and then sends the data in order from the LSB or MSB to the SIM_D pin to perform serial data transmission. After one-byte data has been transmitted, the next data to be transmitted is automatically transferred from SITDR to SITSR, and transmission begins. When the TDRE flag in the SISSR is set to 1, no data is transferred from SITDR to SITSR. It is not possible to read/write a SITSR directly from a CPU or DMAC. 18.3.5 Transmit Data Register (SITDR)
SITDR is an 8-bit readable/writable register that stores data for serial transmission. When the smart card interface detects a vacancy in SITSR, transmit data written to SITDR is transferred to SITSR, and serial transmission is initiated. Consecutive serial transmission is possible by writing the next piece of transmit data to SITDR while SITSR serial data is being transmitted.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
SITD7 SITD6 SITD5 SITD4 SITD3 SITD2 SITD1 SITD0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Bit 7 to 0
Bit Name SITD 7 to 0
Initial Value All 1
R/W R/W
Description Transmit Data Store data for serial transmission.
Rev. 1.0,02/03, page 609 of 1294
18.3.6
Serial Status Register (SISSR)
SISSR is an 8-bit readable/writable register that indicates the operating state of the smart card interface.
Bit: 7 6 5 4 1 WAIT PER TEND _ER 0 1 0 R/W R R/W 3 2 0 0 R
TDRE RDRF ORER ERS Initial value: R/W: 1 R/W 0 R/W 0 R/W 0 R/W
Bit 7
Bit Name TDRE
Initial Value 1
R/W R/W
Description Transmit Data Register Empty Indicates that data was transferred from SITDR to SITSR, and that the next set of serial transmit data can be written to SITDR. 0: Indicates that valid transmit data is written to the SITDR. [Clearing Conditions] * * When the TE bit in SISCR is 1, and data is written to SITDR When 0 is written to the TDRE bit
1: Indicates that there is no valid transmit data in SITDR. [Setting Conditions]* * * * On reset When the TE bit in SISCR is 0 When data is transferred from SITDR to SITSR, and data can be written to SITDR
Note: * Writing 1 will retain the original value.
Rev. 1.0,02/03, page 610 of 1294
Bit 6
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full 1 Indicates that received data is stored in SIRDR* . 0: Indicates that no valid received data is stored in SIRDR. [Clearing Conditions] * * * On reset When data is read from SIRDR When 0 is written to the RDRF bit
2
1: Indicates that valid received data is stored in SIRDR. [Setting Condition]* * When serial reception is completed normally, and received data is transferred from SIRSR to SIRDR. Note: *1. In the T = 0 mode, when the receiver detects a parity error, it retains the previous state without affecting the SIRDR contents and RDRF flag. On the other hand, in the T = 1 mode, when the receiver detects a parity error, it transfers the received data to SIRDR, and sets the RDRF flag to 1. In both the T = 0 and T = 1 modes, clearing the RE bit in SISCR to 0 will retain the previous state without affecting the SIRDR contents and RDRF flag. *2. Writing 1 will retain the original value.
Rev. 1.0,02/03, page 611 of 1294
Bit 5
Bit Name ORER
Initial Value 0
R/W R/W
Description Overrun Error Indicates that an overrun error resulting in abnormal termination has occurred during reception.. 0: Indicates that reception is in progress, or that reception 1 was completed normally* [Clearing Conditions] * * On reset When 0 is written to ORER
2 3
1: Indicates that an overrun error occurred during reception* [Setting Condition]* *
When the next serial reception is completed in the RDRF = 1 state. Notes: *1. Clearing the RE bit in SISCR to 0 will retain the previous state without affecting the ORER flag. *2. SIRDR loses the data received before the overrun error but retains the data received at the time the overrun error occurred. Furthermore, if ORER is set to 1, then subsequent serial reception cannot continue. *3. Writing 1 will retain the original value. 4 ERS 0 R/W Error Signal Status This flag indicates the status of error signals returned from the receiver during transmission. In the T = 1 mode, this bit is not set. 0: Indicates that an error signal indicating detection of a parity error was not sent from the receiver. [Clearing Conditions] * * On reset When 0 is written to ERS
1: Indicates that an error signal indicating detection of a parity error was sent from the receiver. [Setting Condition] * When an error signal is sampled. Note: Clearing the TE bit in SISCR to 0 will retain the previous state without affecting the ERS flag.
Rev. 1.0,02/03, page 612 of 1294
Bit 3
Bit Name PER
Initial Value 0
R/W R/W
Description Parity Error Indicates that a parity error has occurred during reception, resulting in abnormal termination. 0: Indicates that reception is in progress, or that reception 1 was completed normally.* [Clearing Condition] * * On reset When 0 is written to PER
2
1: Indicates that a parity error occurred during reception.* [Setting Condition] *
When the number of logic 1 digits combined in the receive data and parity bit does not match the setting of the even/odd parity specified by the serial mode register's (SISMR) O/E bit during reception. Notes: *1. Clearing the RE bit in SISCR to 0 will retain the previous state without affecting the PER flag. *2. In the T = 0 mode, the receiver does not transfer the data received when a parity error occurs to SIRDR, and sets the RDRF flag. On the other hand, in the T = 1 mode, the data received when a parity error occurs is sent to SIRDR, and the RDRF flag is set. When a parity error occurs, clear the PER flag to 0 before the sampling timing for the next parity bit. When PER is set to 1, data reception can continue. However, the PER flag will not be cleared when reception is completed successfully.
Rev. 1.0,02/03, page 613 of 1294
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End Indicates that transmission is ended. The TEND flag is read-only, and cannot be written. 0: Indicates that transmission is in progress [Clearing Condition] * Transmit data is transferred from SITDR to SITSR, and serial transmission is initiated.
1: Indicates that transmission is ended [Setting Conditions] * * On reset When ERS = 0 (normal transmission) after transmission of one byte of serial characters and a parity bit Note: * The TEND flag is set 1 etu before the end of the guardtime.
Rev. 1.0,02/03, page 614 of 1294
Bit 1
Bit Name
WAIT_ER
Initial Value 0
R/W R/W
Description Wait Error Indicates the wait timer error status. 0: Indicates that the interval between the start of two successive characters has not exceeded the etu set by SIWAIT. [Clearing Conditions] * * On reset When 0 is written to WAIT_ER while its value is 1
1: Indicates that the interval between the start of two successive characters has exceeded the etu set by SIWAIT. [Setting Conditions] * In T = 0 mode, when the interval between the start of two successive characters exceeds the etu (value of 60 x SIWAIT: working wait time).
*
In T = 1 mode, when the interval between the start of two successive characters exceeds the etu (SIWAIT value: Guardtime). Notes: *1. Even if the RE bit in SISCR is cleared to 0, the WAIT_ER flag is unaffected, and the previous state is maintained. *2. In T = 0 mode, changing the RE bit from 0 to 1 may not set the WAIT_ER bit, even if the setting conditions for the WAIT_ER bit are satisfied. In this condition, the WAIT_ER bit is set at the timing of 60 x (SCWAIT + n) etu after the last transmission or reception. n is a whole number and it depends on the timing at which the RE bit is set. *3. In T = 0 mode, to avoid making the WAIT_ER bit set at the timing of 60 x (SCWAIT + n) etu after the last transmission or reception, the following procedure should be followed: Change the protocol bit (PB) in the smart card mode register (SISCMR) from 0 to 1 and again change the PB bit to 0. In T = 1 mode, to avoid making the WAIT_ER bit set at the timing of (SCWAIT) etu after the last reception, the following procedure should be followed: Change the PB bit in SISCMR from 1 to 0 and again change the PB bit to 1.
Rev. 1.0,02/03, page 615 of 1294
Bit 0
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should also always be 0.
[Legend]etu: Elementary Time Unit
18.3.7
Receive Shift Register (SIRSR)
SIRSR is a register for reception of serial data. The smart card interface receives serial data input from the SIM_D pin in order, from the LSB or MSB, and sets it in SIRSR, converting it to parallel data. When reception of one byte of data is completed, the data is automatically transferred to SIRDR. The CPU cannot directly read or write SIRSR. 18.3.8 Receive Data Register (SIRDR)
SIRDR is an 8-bit read-only register that stores received serial data. When reception of one byte of serial data is completed, the smart card interface transfers the received serial data from SIRSR to SIRDR for storage, and completes the reception operation. Thereafter, SIRSR can receive data. In this way, SIRSR and SIRDR constitute a double buffer, enabling continuous reception of data. SIRDR cannot be written from the CPU.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
SIRD7 SIRD6 SIRD5 SIRD4 SIRD3 SIRD2 SIRD1 SIRD0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R
Bit 7 to 0
Bit Name SIRD 7 to 0
Initial Value All 0
R/W R
Description Receive Data These bits store received serial data.
Rev. 1.0,02/03, page 616 of 1294
18.3.9
Smart Card Mode Register (SISCMR)
SISCMR is an 8-bit readable/writable register that selects smart card interface functions.
Bit: Initial value: R/W: 7 0 R 6 LCB 0 R/W 5 PB 0 R/W 4 0 R 3 2 1 RST 0 R/W 0 SMIF 1 R/W
SDIR SINV 0 R/W 0 R/W
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0. Last Character When this bit is set to 1, the guardtime is 2 etu, and the setting of the guard extension register is invalid. 0: The guardtime is determined by the guard value 1: The guardtime is 2 etu register
6
LCB
0
R/W
5
PB
0
R/W
Protocol Selects the T = 0 or T = 1 protocol. 0: The smart card interface operates according to the T = 0 protocol 1: The smart card interface operates according to the T = 1 protocol
4
0
R
Reserved This bit is always read as 0. The write value should also always be 0. Smart Card Data Transfer Direction Selects the format for serial/parallel conversion. 0: Transmit the SITDR contents LSB-first Received data is stored in SIRDR LSB-first. 1: Transmit the SITDR contents MSB-first Received data is stored in SIRDR MSB-first.
3
SDIR
0
R/W
Rev. 1.0,02/03, page 617 of 1294
Bit 2
Bit Name SINV
Initial Value 0
R/W R/W
Description Smart Card Data Inversion Specifies inversion of the data logic level. In combination with the function of bit 3, used for transmission to and reception from an inverse convention card. SINV does not affect the parity bit. 0: Transmit the SITDR contents without change Store received data in SIRDR without change 1: Invert and transmit the SITDR data Invert and store received data in SIRDR
1
RST
0
R/W
Smart Card Reset Controls the output of the SIM_RST pin of the smart card interface. 0: The SIM_RST pin of the smart card interface outputs low level. 1: The SIM_RST pin of the smart card interface outputs high level.
0
SMIF
1
R/W
Smart Card Interface Mode Select This bit is always read as 1. The write value should also always be 1.
[Legend]
etu: Elementary Time Unit
Rev. 1.0,02/03, page 618 of 1294
18.3.10 Serial Control 2 Register (SISC2R) SISC2R is an 8-bit readable/writable register that enables or disables receive data full interrupt (SIMRXI) requests.
Bit: Initial value: R/W: 7 EIO 0 R/W 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Bit 7
Bit Name EIO
Initial Value 0
R/W R/W
Description Error Interrupt Only When the EIO bit is 1, even if the RIE bit is set to 1, a receive data full interrupt (SIMRXI) request is not sent to the CPU. When the DMAC is used with this setting, the CPU processes only SIMERI requests. Receive data full interrupt (SIMRXI) requests are enabled or disabled by the RIE bit setting. Reserved These bits are always read as 0. The write value should also always be 0.
6 to 0
All 0
R
18.3.11 Guard Extension Register (SIGRD) SIGRD is an 8-bit readable/writable register that sets the time added for guardtime.
Bit: 7 SIG RD7 0 R/W 6 SIG RD6 0 R/W 5 SIG RD5 0 R/W 4 SIG RD4 0 R/W 3 SIG RD3 0 R/W 2 SIG RD2 0 R/W 1 SIG RD1 0 R/W 0 SIG RD0 0 R/W
Initial value: R/W:
Rev. 1.0,02/03, page 619 of 1294
Bit 7 to 0
Bit Name SIGRD 7 to 0
Initial Value All 0
R/W R/W
Description Guard Extension Indicates the time added for guardtime after transmitting a character to the smart card. The interval between the start of two successive characters is 12 etu (no addition) when this register value is H'00, is 13 etu when the value is H'01, and so on, up to 266 etu for H'FE. If the value of this register is H'FF, the interval between the start of two successive characters is 11 etu in T = 1 mode and is 12 etu in T = 0 mode.
[Legend] etu: Elementary Time Unit
18.3.12 Wait Time Register (SIWAIT) SIWAIT is a 16-bit readable/writable register. If the interval between the start of two successive characters exceeds the value set (in etu units), a wait time error is generated.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA SIWA IT15 IT14 IT13 IT12 IT11 IT10 IT9 IT8 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 15 to 0
Bit Name SIWAIT 15 to 0
Initial Value All 0
R/W R/W
Description Wait Time Register T=0 In this mode, the Wait Time Register can set a working wait time. If the interval between a character being received and the start character that has previously been received/transmitted exceeds (60 x the value set in this register) etu, the WAIT_ER flag is set to 1. However, when SIWAIT=H'0000, the WAIT_ER flag will be set after 60 etu. T=1 In this mode, the Wait Time Register can set a character wait time. If the interval between the start of two successive characters received exceeds the etu (the value set in this register), the WAIT_ER bit flag is set to 1. However, when SIWAIT=H'0000, the WAIT_ER flag will be set after 1 etu.
[Legend]
etu: Elementary Time Unit
Rev. 1.0,02/03, page 620 of 1294
18.3.13 Sampling Register (SISMPL) SISMPL is a 16-bit readable/writable register that sets the number of serial clock cycles per etu.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 9 8 SISM SISM SISM PL10 PL9 PL8 0 0 1 R/W R/W R/W 7 6 5 SISM SISM SISM PL7 PL6 PL5 0 1 1 R/W R/W R/W 4 3 2 1 0 SISM SISM SISM SISM SISM PL4 PL3 PL2 PL1 PL0 1 0 0 1 1 R/W R/W R/W R/W R/W
Bit 15 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Setting for the number of serial clock cycles per etu The number of serial clock cycles per etu is (SISMPL value + 1). The value written to SISMPL should always be H'0007 or greater.
10 to 0
SISMPL 10 to 0
H'173
R/W
[Legend] etu: Elementary Time Unit
18.4
Operation
The main functions of the SMI are as follows. 1. One frame consists of eight data bits and one parity bit. 2. The transmitter inserts the guardtime, specified by SIGRD and the LCB and PB bits in SISCMR, between the end of each parity bit and the beginning of the next frame. 3. When detecting a parity error, the receiver in T = 0 mode outputs low level for 1 etu as an error signal, after 10.5 etu has passed since the start bit was received. 4. When sampling an error signal, the transmitter in T = 0 mode automatically repeats the disputed data after a delay of at least 2 etu. 5. Only asynchronous communication functions are supported; there is no clock-synchronized communication function. 18.4.1 Data Format
Figure 18.2 shows the data format used by the smart card interface. The smart card interface performs a parity check for each frame during reception. When detecting a parity error, the receiver in T = 0 mode returns an error signal to the transmitter, requesting data repetition. The transmitter samples error signals and repeats the disputed data.
Rev. 1.0,02/03, page 621 of 1294
When detecting a parity error, the receiver in T = 1 mode does not return an error signal. The transmitter does not sample error signals or repeat the disputed data.
When no parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitter output When a parity error occurs in T=0 mode Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Transmitter output When a parity error occurs in T=1 mode Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Receiver output
Transmitter output Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal
Figure 18.2 Data Format Used by the Smart Card Interface The operation sequence is as follows. 1. When the SIM is not in use, the data line is in the high-impedance state, fixed at high level by the pull-up resistance. 2. The transmitter starts transmission of one frame of data. The data frame begins with the start bit (Ds: low level). This is followed by eight data bits (D0 to D7) and the parity bit (Dp). 3. The SIM then returns the data line to high impedance. The data line is held at high level by the pull-up resistance. 4. The receiver performs a parity check. If detecting no parity error and receiving the data normally, the receiver waits for the next frame, without taking further action. If a parity error has occurred, the receiver outputs an error signal (DE: low level) for requesting data repetition in T = 0 mode. After outputting an error signal for the specified duration, the receiver again sets the signal line to high impedance. The signal line returns to high level by the pull-up resistance. In T = 1 mode, however, the receiver outputs no error signal when a parity error occurs. 5. If the transmitter does not receive an error signal, it transmits the next frame. If the transmitter in T = 0 mode receives an error signal, it repeats the disputed data as in step 2 above. In T = 1 mode, however, the transmitter receives no error signals and performs no repetition.
Rev. 1.0,02/03, page 622 of 1294
18.4.2
Register Settings
Table 18.3 shows a map of the bits in the registers used by the smart card interface. Set 0 or 1 to a bit if indicated as 0 or 1 in the following table. Set a bit without 0/1 indication according to below instructions.
Table 18.3 Register Settings for the Smart Card Interface
Bit Register SISMR SIBRR SISCR SITDR SISSR SIRDR SISCMR SISC2R SIWAIT SIGRD SISMPL 0 EIO LCB 0 PB 0 0 0 TDRE RDRF ORER ERS Bit 7 0 0 TIE Bit 6 0 0 RIE Bit 5 PE 0 TE Bit 4 O/E 0 RE Bit 3 0 0 WAIT_IE SITD[7:0] PER SIRD[7:0] SDIR 0 SINV 0 RST 0 SMIF 0 TEND WAIT_ER 0 Bit 2 0 BRR2 TEIE Bit 1 0 BRR1 CKE1 Bit 0 0 BRR0 CKE0
SIWAIT[15:0] (16-bit register) SIGRD[7:0] SISCMPL[10:0] (16-bit register, but bits 15 to 11 are 0)
(1) Serial mode register (SISMR) setting When the IC card is set for the direct convention, the O/E bit is set to 0; for the inverse convention, it is set to 1. (2) Bit rate register (SIBRR) setting Sets the bit rate. For the method of computing settings, refer to section 18.4.3, Clocks. (3) Serial control register (SISCR) settings The different interrupts can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE bits. By setting either the TE or RE bit to 1, transmission or reception is selected. The CKE1 and CKE0 bits are used to select the clock output state. For details, refer to section 18.4.3, Clocks.
Rev. 1.0,02/03, page 623 of 1294
(4) Smart card mode register (SISCMR) settings When the IC card is set for the direct convention, both the SDIR and SINV bits are set to 0; for the inverse convention, both are set to 1. The SMIF bit is always set to 1. Figure 18.3 shows the register settings and initial character waveform examples for two types of IC cards (a direct-convention type and an inverse-convention type). For the direct-convention type, the logical level 1 is assigned to the Z state, and the logical level 0 to the A state, and transmission and reception are performed LSB-first. The data of the above initial character is then H'3B. Even parity is used according to the smart card specification, and so the parity bit is 1. For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical level 0 to the Z state, and transmission and reception are performed MSB-first. The data of the above initial character is then H'3F. Even parity is used according to the smart card specification, and so the parity bit is 0, assigned to the Z state. Inversion by the SINV bit setting only applies to data bits D7 to D0. To invert the parity bit, specify odd parity through the SISMR.O/E bit, both for transmission and reception.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state
(a) Direct convention (SDIR = SINV=O/E = 0)
(Z)
A Ds
Z D7
Z D6
A D5
A D4
A D3
A D2
A D1
A D0
Z Dp
(Z) state
(b) Inverse convention (SDIR = SINV=O/E = 1)
Figure 18.3 Examples of Initial Character Waveforms
Rev. 1.0,02/03, page 624 of 1294
18.4.3
Clocks
Only the internal clock generated by the on-chip baud rate generator can be used as the transmission/reception clock in the smart card interface. The bit rate is set using SIBRR and SISMPL, using the formula indicated below. Examples of bit rates are shown in table 18.4. Here, when CKE0 = 1 is used to select the clock output, a clock signal is output from the SIM_CLK pin with frequency equal to (SISMPL+1) times the bit rate. B = Pck x10 / {(S+1) x 2 (N+1)}
6
Where B: the bit rate (bits/s) Pck: the operating frequency of the peripheral module [MHz] S: the SISMPL setting (0 S 2047) N: the SIBRR setting (0 N 7). Table 18.4 Example of Bit Rates (bits/s) for SIBRR Settings (Pck = 33.3 MHz, SISMPL = 371)
SIBRR Setting 7 6 5 4 3 2 1 0 SIM_CLK Frequency (MHz) 2.06 2.36 2.75 3.30 4.13 5.50 8.25 16.50 Bit Rate (bits/s) 5544 6336 7392 8871 11089 14785 22177 44355
Rev. 1.0,02/03, page 625 of 1294
18.4.4
Data Transmission/Reception Operation
(1) Initialization Prior to data transmission and reception, the procedure shown in figure 18.4 should be used to initialize the smart card interface. Initialization is also necessary when switching from transmitter mode to receiver mode, and when switching from receiver mode to transmitter mode. An example of the initialization process is shown in the flow chart of figure 18.4.
Initialization Clear the TE, RE bits in SISCR to 0 Clear the ERS, PER, ORER, and WAIT_ER flags in SISSR to 0 Set the parity using the O/E bit in SISMR Set the LCB, PB, SMIF, SDIR, and SINV bits in SISCMR Set SIBRR, SISMPL, SIWAIT, and SIGRD Set the clock using the CKE1 and CKE0 bits in SISCR. Clear the TIE, RIE, TE, RE, TEIE and WAIT_IE flags to 0. Wait Has a 1-bit interval elapsed? Yes Set the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits in SISCR End (7) No (1) (1) Clear the TE and RE bits in SISCR to 0. (2) Clear the error flags PER, ORER, ERS, and WAIT_ER in SISSR to 0. (3) Set the parity bit (O/E bit) in SISMR. (3) (4) Set the LCB, PB, SMIF, SDIR, and SINV bits in SISCMR. (5) Set the value corresponding to the bit rate in SIBRR. Set SISMPL, SIWAIT, SIGRD. (6) Set the clock source select bits (CKE1, CKE0) in SISCR. At this time, the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits are set to 0. If the CKE0 bit is set to 1, a clock signal is output from the SIM_CLK pin. (7) After waiting at least 1 etu, set the TIE, RIE, TE, RE, TEIE, and WAIT_IE bits in SISCR.
(2)
(4)
(5)
(6)
Figure 18.4 Example of Initialization Flow
Rev. 1.0,02/03, page 626 of 1294
(2) Serial data transmission Data transmission in smart card mode includes error signal sampling and repetition processing. An example of transmission processing is shown in figure 18.5.
Initialization Start transmission
(1)
(1) (2) No
Follow the procedure of item 1 in section 18.4.4, and initialize the smart card interface. Confirm that the ERS bit (error flag) in SISSR is cleared to 0. Repeat (2) and (3) in the figure until it can be confirmed that the TDRE flag in SISSR is set to 1.
ERS=0? Yes
(2)
Error processing No TDRE=1? Yes Write transmission data to SITDR No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1&& TDRE=1? Yes Clear TE bit in SISCR to 0 Transmission end (6) (4) (3)
(3)
(4) Write the transmission data to SITDR, and perform the transmission. At this time, the TDRE flag is automatically cleared to 0. When transmission of the start bit is begun, the TEND flag is automatically cleared to 0, and the TDRE flag is automatically set to 1. (5) When performing continuous data transmission, return to (2). (6) When transmission is ended, clear the TE bit to 0.
(5)
Figure 18.5 Example of Transmission Processing
Rev. 1.0,02/03, page 627 of 1294
(3) Serial data reception An example of data reception processing in smart card mode is shown in figure 18.6.
Initialization
(1)
(1) Follow the procedure of item 1 in section 18.4.4, and initialize the smart card interface. (2) Confirm that the PER, ORER, and WAIT_ER flags in SISSR are 0. If one of these flags is set, after performing the prescribed reception error processing, clear the PER, ORER, and WAIT_ER flags to 0. (3) Repeat (2) and (3) in the figure until it can be confirmed that the RDRF flag is set to 1.
Start reception
PER=0&&ORER=0 &&WAIT_ER=0? Yes
No
(2)
Error processing No RDRF=1? Yes (3)
(4) Read received data from SIRDR. (5) When performing continuous data reception, return to step (2). (6) When reception is ended, clear the RE bit to 0.
Read received data from SIRDR No All data received? Yes Clear RE bit in SISCR to 0
(4)
(5)
Note: If during reception a parity error occurs and PER is set to 1, in T=0 mode the received data is not transferred to SIRDR, and so this data cannot be read.
(6)
Reception end
Figure 18.6 Example of Reception Processing
Rev. 1.0,02/03, page 628 of 1294
(4) Switching modes When switching from receiver mode to transmitter mode, after confirming that reception has been completed, and then set RE = 0 and TE = 1. Completion of reception can be confirmed through the RDRF flag. When switching from transmitter mode to receiver mode, after confirming that transmission has been completed, and then set TE = 0 and RE = 1. Completion of transmission can be confirmed through the TDRE and TEND flags. (5) Interrupt operations The smart card interface has four types of interrupt sources: transmit data empty interrupt (SIMTXI) requests, transmit/receive error interrupt (SIMERI) requests, receive data full interrupt (SIMRXI) requests, and transmission end interrupt (SIMTEI) requests. Table 18.5 describes the interrupt sources for the smart card interface. Each of the interrupt requests can be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SISCR and the EIO bit in SISC2R. In addition, each interrupt request can be sent independently to the interrupt controller. Table 18.5 Smart Card Interface Interrupt Sources
Operating State Transmitter mode Normal operation Flags TDRE TEND Error Receiver mode Normal operation Error ERS RDRF ORER, PER WAIT_ER Mask Bits TIE TEIE RIE RIE, EIO RIE WAIT_IE Interrupt Sources SIMTXI SIMTEI SIMERI SIMRXI SIMERI SIMERI
(6) Data transfer using DMAC The smart card interface enables reception and transmission in T=0 and T=1 modes using DMAC. In transmission, when the TDRE flag in SISSR is set to 1, a transmit data empty DMA transfer request is issued. If a transmit data empty DMA transfer request is set in advance as a DMAC startup factor, the DMAC can be started and made to transfer data when a transmit data empty DMA transfer request occurs. In T = 0 mode, if an error signal is received during transmission, the disputed data is automatically repeated. This repetition generates no DMA transfer request, so it is possible to transmit the number of bytes assigned to the DMAC. For error handling with an interruput request to the CPU in transmission using the DMAC, set the TIE bit to 0 to disable an SIMTXI request, and set the RIE bit to 1 to enable an SIMERI request. Clear the ERS flag by sending an interrupt request to the CPU since it is not automatically cleared once set when an error signal was received.
Rev. 1.0,02/03, page 629 of 1294
The receiver issues a receive data full DMA transfer request when the RDRF flag in SISSR is set to 1. It is possible to start the DMAC to transfer data with a receive data full DMA transfer request by setting this request as a DMAC startup factor in advance. In T = 0 mode, if a parity error occurs during reception, a data repeat request is issued. Since the RDRF flag is not set and a DMA transfer request is not issued, it is possible to receive the number of bytes assigned to the DMAC. For error handling with an interrupt to the CPU in reception using the DMAC, set the RIE and EIO bits to 1 to disable an SIMRXI interrupt and to enable only an SIMERI request. Clear the PER, ORER, and WAIT_ER flags by sending an interrupt request to the CPU since they are not automatically cleared once set by a receive error. For transmission/reception using the DMAC, the DMAC should be configured to be enabled before configuring the smart card interface.
18.5
Usage Notes
The following matters should be noted when using the smart card interface. 18.5.1 Receive data Timing
When the SISMPL register holds its initial value, the smart card interface operates at a serial clock frequency (SIM_CLK) 372 times the transfer rate. During reception, the smart card interface samples the falling edge of the start bit using the serial SIM_CLK for internal synchronization. Received data is captured internally at the center of one etu (at the rising edge of the 186th SIM_CLK pulse when one etu takes 372 SIM_CLK cycles). This is shown in figure 18.7.
372 clock pulses 186 clock pulses 0 Serial clock (SIM_CLK) Received data Start bit 185 371 0 185 371 0
D0
D1
Synchronization sampling timing
Data sampling timing
Figure 18.7 Received Data Sampling Timing in Smart Card Mode
Rev. 1.0,02/03, page 630 of 1294
18.5.2
Repetition when the Smart Card Interface is in Receiver Mode (T = 0)
Figure 18.8 shows repetition operations when the smart card interface is in receiver mode. (1) to (5) in figure 18.8 correspond to items 1 to 5 described below. 1. If checking of the received parity bit detects an error, the PER bit in SISSR is automatically set to 1. If the RIE bit in SISCR is set for enable, an SIMERI request is issued. The PER bit in SISSR should be cleared to 0 before the sampling timing for the next parity bit. 2. The RDRF bit in SISSR is not set for frames in which a parity error occurs. 3. If checking of the received parity bit detects no error, the PER bit in SISSR is not set. 4. If checking of the received parity bit detects no error, it is assumed that reception was completed normally, and the RDRF bit in SISSR is automatically set to 1. If the RIE bit in SISCR is 1 and the EIO bit is 0, an SIMRXI request is generated. 5. If a normal frame is received, the pin is maintained in a high-impedance state at the timing for transmission of error signals.
nth transfer frame Repeat frame n + 1th transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
(DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 DP Ds D0 D1 D2 D3 D4 (5)
RDRF (2) PER (1) (3) (4)
Figure 18.8 Repetition in the Smart Card Interface Receiver Mode 18.5.3 Repetition when the Smart Card Interface is in Transmitter Mode (T = 0)
Figure 18.9 shows repetition operations when the smart card interface is in transmitter mode. (1) to (4) in figure 18.9 correspond to items 1 to 4 described below. 1. After completion of transmission of one frame, if an error signal is returned from the receiver, the ERS bit in SISSR is set to 1. If the RIE bit in SISCR is set to enable, an SIMERI request is issued. The ERS bit in SISSR should be cleared to 0 before the sampling timing for the next parity bit. 2. In T = 0 mode, the TEND bit in SISSR is not set for a frame when an error signal indicating an error is received. 3. If no error signal is returned from the receiver, the ERS bit in SISSR is not set. 4. If an error signal is not returned from the receiver, it is assumed that transmission of one frame, including repetition, is completed, and the TEND bit in SISSR is set to 1. At this time, if the TIE bit in SISCR is set to enable, a TEI interrupt request is issued.
Rev. 1.0,02/03, page 631 of 1294
nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE TDRE Transmission from SITDR to SITSR TEND (2) ERS (1)
Repeat frame Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
n+1th transfer frame (DE) Ds D0 D1 D2 D3 D4
Transmission from SITDR to SITSR (4) (3)
Figure 18.9 Repetition Standby Mode (clock stopped) when the Smart Card Interface is in Transmitter Mode
Rev. 1.0,02/03, page 632 of 1294
18.5.4
Transmit End Interrupt
If the TEIE bit is always set to 1 during continuous transmission, unnecessary transmit end interrupts (SIMTEI) occur because the TEND bit is set to 1 every time transmission is completed. To avoid unnecessary SIMTEI requests, the TEIE bit in SISCR should be set to 1 only after the last transmit data is written to SITDR and SITSR starts transmission. Figure 18.10 shows the signal waveforms when TEIE is set to 1.
Transfer frame (DE) (DE) Transfer frame (DE) Last frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
TDRE TEND
Unnecessary TEND set timing TEIE
SIMTEI request
TEIE set timing
Figure 18.10 TEIE Set Timing 18.5.5 Standby Mode Switching
When switching between the smart card interface mode and standby mode, in order to maintain the clock duty, the following switching procedure should be used. Figure 18.11 shows standby mode switching procedure. (1) to (7) in figure 18.11 correspond to items 1 to 7 described below. * When changing from smart card interface mode to standby mode:
1. Write 0 to the TE and RE bits in SISCR, to stop transmission and reception operations. At the same time, set the CKE1 bit to the value for the output-fixed state in standby mode. 2. Write 0 to the CKE0 bit in SISCR to stop the clock. 3. Wait for one clock cycle of the serial clock. During this interval, the duty is maintained, and the clock output is fixed at the specified level. 4. Make the transition to standby mode.
Rev. 1.0,02/03, page 633 of 1294
*
When returning from standby mode to the smart card interface mode:
5. Cancel the standby state. 6. Set the CKE1 bit in SISCR to the value of the output-fixed state at the beginning of standby (the current SIM_CLK pin state). 7. Write 1 to the CKE0 bit in SISCR to output a clock signal. Clock signal generation begins at normal duty.
Normal mode Standby mode Normal mode
SIM_CLK
(1) (2) (3)
(4)
(5) (6) (7)
Figure 18.11 Procedure for Stopping the Clock and Restarting 18.5.6 Power-On and Clock Output
In order to maintain the clock duty from power-on, the following switching procedure should be used. 1. The clock output pin is set to an input port as the initial state and is pulled up in the chip. 2. Select the SIM through IPSELR in the PFC. 3. Use the CKE1 bit in SISCR to specify the fixed output. 4. Set the CKE0 bit in SISCR to 1 to start clock output. 18.5.7 Pin Connections
An example of pin connections for the smart card interface is shown in figure 18.12. In communication with the smart card, transmission and reception are performed using a single data transmission line. The data transmission line should be pulled up by a resistance on the power supply VDDQ side. When using the clock generated by the smart card interface with the IC card, the SIM_CLK pin output is input to the CLK pin of the IC card. If an internal clock of the IC card is used, this connection is not needed.
Rev. 1.0,02/03, page 634 of 1294
20k SIM_D Data line I/O
Smart card interface
SIM_CLK
Clock line
CLK
SIM_RST
Reset line
RST
This LSI
Note: For details, refer to ISO/IEC7816-3.
Smart card
Figure 18.12 Example of Smart Card Interface Pin Connections
Rev. 1.0,02/03, page 635 of 1294
Rev. 1.0,02/03, page 636 of 1294
Section 19 Hitachi I C Interface
This LSI contains an on-chip 2-channel I C bus interface compatible with the Philips I C bus (Inter 2 IC Bus) interface. It should be noted, however, the register structure used to control the I C bus differs from that of the Philips implementation.
2 2
2
19.1
Features
2
* Supports the Philips I C bus interface. * Multi-master capability. * 7- or 10-bit address compatible master. * 7-bit slave address. * Fast mode compatible. * Adaptable to a wide range of system clock frequencies. * Supports 16-stage FIFO buffer mode. Figure 19.1 shows a connection example for the I C bus interface.
2
Rev. 1.0, 02/03, page 637 of 1294
I/O buffer I2C_SCL Clock Generator
Clock Filter
Master
I/O buffer I2C_SDA
Data Filter
Slave
Bus interface
Tx DATA Control/Status Register Rx DATA
Figure 19.1 I C Bus Interface Block Diagram
2
19.2
Input/Output Pins
2
Table 19.1 lists the pins used in the I C bus interface. Table 19.1 I C Bus Interface
Channel 0 Pin Name I2C0_SCL I2C0_SDA 1 I2C1_SCL I2C1_SDA Direction Input/Output Input/Output Input/Output Input/Output
2
2
Description I C 0 serial clock input output pin* I C 0 serial data input output pin* I C 1 serial clock input output pin* I C 1 serial data input output pin*
2 2 2 2
Note: *SCL/SDA output on the I C bus open drain pin.
19.3
Register Descriptions
2
All registers in the I C bus interface module are mapped to the register bus interface. For address and processing status of these registers, refer to section 32, List of Registers. Note that the channel numbers are omitted in the description.
Rev. 1.0, 02/03, page 638 of 1294
Table 19.2 Register Configuration (1)
Ch. Register Name 0 Slave control register 0 Master control register 0 Slave status register 0 Master status register 0 Slave interrupt enable register 0 Abbrev. ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 R/W R/W R/W
1
P4 Address H'FE14 0000 H'FE14 0004
Area 7 Address H'1E14 0000 H'1E14 0004 H'1E14 0008 H'1E14 000C H'1E14 0010 H'1E14 0014 H'1E14 0018 H'1E14 001C H'1E14 0020 H'1E14 0024 H'1E14 0024 H'1E14 0028 H'1E14 002C H'1E14 0030 H'1E14 0034 H'1E14 0038 H'1E15 0000 H'1E15 0004 H'1E15 0008 H'1E15 000C H'1E15 0010 H'1E15 0014 H'1E15 0018 H'1E15 001C H'1E15 0020 H'1E15 0024 H'1E15 0024 H'1E15 0028 H'1E15 002C H'1E15 0030 H'1E15 0034 H'1E15 0038
Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
R/(W)* H'FE14 0008 R/(W)*2 H'FE14 000C R/W H'FE14 0010 H'FE14 0014 H'FE14 0018 H'FE14 001C H'FE14 0020 H'FE14 0024 H'FE14 0024 H'FE14 0028 H'FE14 002C H'FE14 0030 H'FE14 0034 H'FE14 0038 H'FE15 0000 H'FE15 0004
1
Master interrupt enable register 0 ICMIER0 R/W Clock control register 0 Slave address enable register 0 ICCCR0 ICSAR0 R/W R/W R/W R/W R/W R/W R/W R/W
Master address enable register 0 ICMAR0 Receive data register 0 Transmit data register 0 FIFO control register 0 FIFO status register 0 FIFO interrupt enable register 0 ICRXD0 ICTXD0 ICFCR0 ICFSR0 ICFIER0
Receive FIFO data count register 0 ICRFDR0 R Transmit FIFO data count register 0 ICTFDR0 R
1
Slave control register 1 Master control register 1 Slave status register 1 Master status register 1 Slave interrupt enable register 1
ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1
R/W R/W
R/(W)* H'FE15 0008 R/(W)*2 H'FE15 000C R/W H'FE15 0010 H'FE15 0014 H'FE15 0018 H'FE15 001C H'FE15 0020 H'FE15 0024 H'FE15 0024 H'FE15 0028 H'FE15 002C H'FE15 0030 H'FE15 0034 H'FE15 0038
Master interrupt enable register 1 ICMIER1 R/W Clock control register 1 Slave address enable register 1 ICCCR1 ICSAR1 R/W R/W R/W R/W R/W R/W R/W R/W
Master address enable register 1 ICMAR1 Receive data register 1 Transmit data register 1 FIFO control register 1 FIFO status register 1 FIFO interrupt enable register 1 ICRXD1 ICTXD1 ICFCR1 ICFSR1 ICFIER1
Receive FIFO data count register 1 ICRFDR1 R Transmit FIFO data count register 1 ICTFDR1 R
Rev. 1.0, 02/03, page 639 of 1294
Table 19.2 Register Configuration (2)
Standby Power-on Reset by Manual Reset by Sleep by Sleep by Software/ RESET Pin/WDT/ RESET Pin/WDT/ Instruction/Deep by H-UDI Multiple Exception Sleep Hardware Each Module
Ch. Register Name
Abbrev.
0
Slave control register 0 Master control register 0 Slave status register 0 Master status register 0 Slave interrupt enable register 0 Master interrupt enable register 0 Clock control register 0 Slave address enable register 0 Master address enable register 0 Receive data register 0 Transmit data register 0 FIFO control register 0 FIFO status register 0 FIFO interrupt enable register 0 Receive FIFO data count register 0 Transmit FIFO data count register 0
ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 ICMIER0 ICCCR0 ICSAR0 ICMAR0 ICRXD0 ICTXD0 ICFCR0 ICFSR0 ICFIER0 ICRFDR0 ICTFDR0 ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1 ICMIER1 ICCCR1 ICSAR1 ICMAR1 ICRXD1 ICTXD1 ICFCR1 ICFSR1 ICFIER1 ICRFDR1 ICTFDR1
H'0000 0000 H'0000 0000*3 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000*3 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000*3 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000*3 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
*
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
1
Slave control register 1 Master control register 1 Slave status register 1 Master status register 1 Slave interrupt enable register 1 Master interrupt enable register 1 Clock control register 1 Slave address enable register 1 Master address enable register 1 Receive data register 1 Transmit data register 1 FIFO control register 1 FIFO status register 1 FIFO interrupt enable register 1 Receive FIFO data count register 1 Transmit FIFO data count register 1
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. *1. Bits 4 to 0 allow only a write of 0 to clear the flags. *2. Bits 6 to 0 allow only a write of 0 to clear the flags. *3. Bits 6 and 5 are undefined.
Rev. 1.0, 02/03, page 640 of 1294
19.3.1
Bit: Initial value: R/W: Bit: Initial value: R/W:
Slave Control Register (ICSCR)
31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 SDBS 0 R/W 18 0 R 2 SIE 0 R/W 17 0 R 1 16 0 R 0
GCAE FNA 0 R/W 0 R/W
Bit 31 to 4
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
3
SDBS
0
R/W
Slave Data Buffer Select This bit is used to select the data buffer. The data buffer has two modes; the FIFO buffer mode and the single buffer mode. Clearing SDBS to 0 will select the FIFO buffer mode. In the receive mode, while the RDF flag is 1 with the receive byte count stored in the FIFO buffer equal to or greater than the byte count specified by RTRG3 to RTRG0, SCL is held low. Reading the receive data from the FIFO buffer will clear the RDF flag to 0 and release SCL from low level. Setting SDBS to 1 will select the single buffer mode. SCL will be held low from the moment the receive data register receives a data packet until SDR is cleared to 0. 0: FIFO buffer mode 1: Single buffer mode
2
SIE
0
R/W
Slave Interface Enable Ensure to set this bit to 1 to have the slave to operate. If this bit is low, the slave interface is reset. Setting the MIE bit to 1 will set this bit to 1.
1
GCAE
0
R/W
General Call Acknowledgement Enable Ensure to set this bit to 1 when the master requires the slave to acknowledge a transmission of a general call address. Rev. 1.0, 02/03, page 641 of 1294
Bit 0
Bit Name FNA
Initial Value 0
R/W R/W
Description Force Non-Acknowledge In the slave receiver mode, the level on the FNA bit is sent to the transmitter as the acknowledge signal. FNA is 0 while the data packet is being received, and set to 1 on completion of data reception. The force non-acknowledge is sent to the master during slave reception. After having received the last required byte in a data packet, the slave communicates to the master with not driving acknowledge (NACK). The master issues a stop on to the bus after receiving a NACK. Setting FNA to 1 will not effect the acknowledging of slave addresses. This I2C module assumes that the slave receiver returns NACK by FNA = 1 in order to handle an error associated with system failure. Therefore, the low period of SCL is not extended for returning NACK. The FNA value on reception of the last bit of one byte determines whether or not the slave receiver returns NACK. Namely, to have the slave return NACK after transfer of a specific byte, FNA must be set to 1 on completion of the transfer of the preceding byte.
19.3.2
Slave Status Register (ICSSR)
The status bits (bit 0 to bit 6) of the slave status register are cleared by writing 0 to the respective status bit positions in the receive status state. Each bit is held at 1 until reset by a write of 0; however, the GCAR and STM bits are the exception.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 SSR 19 0 R 3 SDE 18 0 R 2 SDT 17 0 R 1 SDR 16 0 R 0 SAR 0 R/W*
GCAR STM 0 R 0 R
0 0 0 0 R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 642 of 1294
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
6
GCAR
0
R
General Call Address Received Indicates that the address received from the bus is a general call address (00H). This bit does not cause an interrupt. This bit is automatically cleared to 0 by hardware when the SIE bit (bit 2 in the slave control register) is 0 or when the SSR bit (bit 4 in the slave status register) is set to 1.
5
STM
0
R
Slave Transmit Mode Current slave transmit mode (read or write). Setting this bit to 1 indicates a write operation, and clearing this bit to 0 indicates a read. This status bit does not cause an interrupt. This bit is automatically cleared by hardware when the SIE bit (bit 2 in the slave control register) is 0 or when the SSR bit (bit 4 in the slave status register) is set to 1.
4
SSR
0
R/W*
Slave Stop Received A stop has been output to the bus. This status bit becomes active after the rising edge of SDA during the stop bit.
3
SDE
0
R/W*
Slave Data Empty Transmit data has been loaded into the shift register. At the start of data byte transmission, the contents of the ICTXD register are loaded into a shift register ready for the data to be passed onto the bus. This status bit indicates that this has taken place and that the ICTXD register is again ready to receive further data. This status bit becomes active on the falling edge of SCL before the first data bit. In the single buffer mode, this bit must be reset each time a new data has been written to the ICTXD register. This is because the slave holds SCL low to stall the bus, if it reaches the start of a slave transmit cycle and this status bit is still set. In the FIFO buffer mode, this bit is not used.
Rev. 1.0, 02/03, page 643 of 1294
Bit 2
Bit Name SDT
Initial Value 0
R/W R/W*
Description Slave Data Transmitted A byte of data has been transmitted on the bus. This status bit becomes active after the falling edge of SCL during the last data bit.
1
SDR
0
R/W*
Slave Data Received A byte of data has been received from the bus and is available in the receive data register. This bit becomes active after the falling edge of SCL during the last data bit. After data has been read from the ICRXD register, this bit must be reset in single buffer mode. This bit is not used in the FIFO buffer mode. When SDBS is set to 1, SCL will be held low from the moment the receive data register acquires the data packet up until SDR is cleared.
0
SAR
0
R/W*
Slave Address Received Indicates that the slave has recognized its own address on the bus (defined by the contents of the slave address register). If the general call acknowledgement enable bit in the slave control register is enabled, then this status bit could also indicate the reception of a general call address on the bus. In that case, bit GCAR of this register is used to differentiate the receipt of a general call address. Bit STM indicates whether the access is a read (high) or a write (low). This status becomes active after the falling edge of SCL during the last address bit. The slave holds SCL low at the start of the ACK phase until this bit is reset by software.
Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written to, it is ignored.
Rev. 1.0, 02/03, page 644 of 1294
19.3.3
Bit: Initial value: R/W: Bit: Initial value: R/W:
Slave Interrupt Enable Register (ICSIER)
31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
SSRE SDEE SDTE SDRE SARE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
4
SSRE
0
R/W
Slave Stop Receive Interrupt Enable 0: The SSR interrupt is disabled 1: The SSR interrupt is enabled
3
SDEE
0
R/W
Slave Data Empty Interrupt Enable 0: The SDE interrupt is disabled 1: The SDE interrupt is enabled
2
SDTE
0
R/W
Slave Data Transmit Interrupt Enable 0: The SDT interrupt is disabled 1: The SDT interrupt is enabled
1
SDRE
0
R/W
Slave Data Receive Interrupt Enable 0: The SDR interrupt is disabled 1: The SDR interrupt is enabled
0
SARE
0
R/W
Slave Address Receive Interrupt Enable 0: The SAR interrupt is disabled 1: The SAR interrupt is enabled
Rev. 1.0, 02/03, page 645 of 1294
19.3.4
Bit:
Slave Address Register (ICSAR)
31 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Initial value: R/W: Bit:
0 R 15 -
SADD0 SADD0 SADD0 SADD0 SADD0 SADD0 SADD0 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
6 to 0
SADD0_6 to All 0 SADD0_0
R/W
Slave Address This is the unique 7-bit address allocated to the 2 slave on the I C bus. The slave interface looks for a match between this address and the first seven bits transmitted as the slave address, at the beginning of a data packet transmission.
19.3.5
Bit: Initial value: R/W: Bit: Initial value: R/W:
Master Control Register (ICMCR)
31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 TSBE 0 R/W 17 0 R 1 FSB 0 R/W 16 0 R 0 ESG 0 R/W
MDBS FSCL FSDA OBPC MIE 0 R/W R/W R/W 0 R/W 0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
Rev. 1.0, 02/03, page 646 of 1294
Bit 7
Bit Name MDBS
Initial Value 0
R/W R/W
Description Master Data Buffer Select This bit is used to select the data buffer. The data buffer has the FIFO buffer mode and the single buffer mode. Clearing MDBS to 0 will select theFIFO buffer mode. In the receive mode, while the RDF flag is 1 with the receive byte count in the FIFO buffer reaches the byte count specified by RTRG3 to RTRG0, SCL is held low. Reading the receive data from the FIFO buffer will clear the RDF flag to 0 and release SCL from low level. Setting MDBS to 1 will select the single buffer mode. SCL will be held low from the moment the receive data register receives a data packet until the MDR flag is cleared to 0.
6
FSCL
R/W
Force SCL Controls the state of the I2C_SCL pin. Reading this bit will return the value reflecting the current state of I2C_SCL. When OBPC is 1, this bit directly controls SCL on the bus. Since this bit reflects the value on the I2C_SCL pin directly, the read value (level) of this bit (including the reset level) changes depending on the I2C_SCL level.
5
FSDA
R/W
Force SDA Controls the state of the I2C_SDA pin. Reading this bit will return the value reflecting the busy 2 state on the I C bus. When OBPC is 1, this bit directly controls SDA on the bus. The read value (level) of this bit (including the 2 reset level) reflects the busy state on the I C bus. 0: The I C bus is not busy 2 1: The I C bus is busy
2
4
OBPC
0
R/W
Override Bus Pin Control Setting OBPC to 1 will have FSDA and FSCL in this register control the SDA and SCL lines directly. This mode is used for testing purposes only.
3
MIE
0
R/W
Master Interface Enable Setting MIE to 1 will enable the master interface.
Rev. 1.0, 02/03, page 647 of 1294
Bit 2
Bit Name TSBE
Initial Value 0
R/W R/W
Description Start Byte Transmission Enable Setting TSBE to 1 will have the master transmit a start byte (01H) onto the bus after each start or restart is issued. The start byte is used for interfacing with a microcomputer with a lower 2 operating frequency which supports to the I C bus interface.
1
FSB
0
R/W
Force Stop onto the Bus Setting FSB to 1 will have the master issue a stop onto the bus at the end of the current transfer. If ESG is also 1, the master immediately issues a start and begins transmitting a new data packet. If ESG is 0, the master enters the idle state. Set FSB to 1 when the TEND flag is set to 1 during transmission in the FIFO buffer mode, or when the RDF flag is set to 1 during reception in the FIFO buffer mode. In single buffer mode, when the last bit of a byte 2 is transmitted/received, the I C module latches the FSB value and enters the STOP state. Therefore, to stop the transfer after a specified number of bytes are transferred, the FSB bit must be set to 1 before the last byte is transferred.
0
ESG
0
R/W
Enable Start Generation Setting ESG to 1 will have the master start transmission of a data packet. If the bus is idle when ESG is set to 1, the master issues a start onto the bus and then issues the slave address. If the master is transferring data when ESG is set to 1, the master issues a restart before transmitting the slave address at the end of that data byte transfer. In the case of data packet transmission, ESG must be reset by software after the slave address is transmitted; if not reset, a restart is issued after each time the transmission is completed.
Rev. 1.0, 02/03, page 648 of 1294
19.3.6
Master Status Register (ICMSR)
The status bits of the master status register (bits 0 to 6) are cleared by writing 0 to the respective status bit positions in the reception states. Each status bit remains 1 until reset by writing 0.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 MNR 21 0 R 5 MAL 20 0 R 4 MST 19 0 R 3 MDE 18 0 R 2 MDT 17 0 R 1 MDR 16 0 R 0 MAT
0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
6
MNR
0
R/W*
Master NACK Received MNR = 1 indicates that the master has received a NACK response (SDA is high during the acknowledge cycle on the bus) during an address or data transmission.
5
MAL
0
R/W*
Master Arbitration Lost MAL = 1 in the multiple-master system indicates that the master has lost bus arbitration for other masters. In this case, MIE is reset and master interface is disabled.
4
MST
0
R/W*
Master Stop Transmission MST = 1 indicates that the master has sent a stop onto the bus. A stop can be sent either as a result of the setting of the forced stop bit in the control register, or from a NACK being received from a slave during data packet reception from a slave.
Rev. 1.0, 02/03, page 649 of 1294
Bit 3
Bit Name MDE
Initial Value 0
R/W R/W*
Description Master Data Empty At the start of a byte-data transmission, the contents of the transmit data register are loaded to a shift register, which is ready for passing data onto the bus. MDE = 1 indicates that this load operation has taken place and the transmit data register is ready to receive further data. In the master transmit mode, the MDE and MAT bits are simultaneously set to 1 after the slave address has been sent. In this case, clear the MDE and MAT bits to 0 after clearing the ESG bit of the ICMCR to 0. The data transmission is then resumed.
2
MDT
0
R/W*
Master Data Transmission The master has transmitted a byte of data to the slave on the bus. This status bit becomes active after the falling edge of SCL during the last data bit transmission.
1
MDR
0
R/W*
Master Data Reception The master has received a byte of data from the bus and the receive data register is ready. This status bit becomes active after the falling edge of SCL during the last data bit reception. In the single buffer mode, this status bit must be reset after data has been read from the receive data register. In the FIFO buffer mode, this bit is not used. When MDBS = 1, SCL is held low from the moment the receive data register starts receiving data packets until the MDR bit is cleared to 0. In the master receive mode, the MDE and MAT bits are simultaneously set to 1 after the slave address has been sent. In this case, clear the MDE and MAT bits to 0 after clearing the ESG bit of the ICMCR to 0. The data transmission is then resumed.
0
MAT
0
R/W*
Master Address Transmission The master has transmitted the slave address byte of a data packet. This bit becomes active after the falling edge of SCL during the output of the ack bit which is sent after an address.
Rev. 1.0, 02/03, page 650 of 1294
Note: * This bit can be written or read. When 0 is written to, the bit is initialized. When 1 is written to, it is ignored.
19.3.7
Bit: Initial value: R/W: Bit: Initial value: R/W:
Master Interrupt Enable Register (ICMIER)
31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
MNRE MALE MSTE MDEE MDTE MDRE MATE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
6
MNRE
0
R/W
Master NACK Received Interrupt Enable 0: The MNR interrupt is disabled 1: The MNR interrupt is enabled
5
MALE
0
R/W
Master Arbitration Lost Interrupt Enable 0: The MAL interrupt is disabled 1: The MAL interrupt is enabled
4
MSTE
0
R/W
Master Stop Transmission Interrupt Enable 0: The MST interrupt is disabled 1: The MST interrupt is enabled
3
MDEE
0
R/W
Master Data Empty Interrupt Enable 0: The MDE interrupt is disabled 1: The MDE interrupt is enabled
2
MDTE
0
R/W
Master Data Transmission Interrupt Enable 0: The MDT interrupt is disabled 1: The MDT interrupt is enabled
1
MDRE
0
R/W
Master Data Receive Interrupt Enable 0: The MDR interrupt is disabled 1: The MDR interrupt is enabled
0
MATE
0
R/W
Master Address Transmission Interrupt Enable 0: The MAT interrupt is disabled 1: The MAT interrupt is enabled
Rev. 1.0, 02/03, page 651 of 1294
19.3.8
Bit:
Master Address Register (ICMAR)
31 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Initial value: R/W: Bit:
0 R 15 -
SADD1 SADD1 SADD1 SADD1 SADD1 SADD1 SADD1 STM1 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 to 1
SADD1_6 to All 0 SADD1_0 STM1 0
R/W
Slave Address This is the address of the slave the master is to communicate with. Slave Transfer Mode This bit indicates in which mode the slave is to operate. This bit sets the operating mode (transmit or receive mode) of the slave to the external slave device specified by the slave address (SADD1) sent from the master. The slave device is automatically set to the transmit/receive mode by hardware according to the received STM1 value. 0: Write operation 1: Read operation
0
R/W
19.3.9
Bit: Initial value: R/W: Bit: Initial value: R/W:
Clock Control Register (ICCCR)
31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 0 R/W 0 R/W 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 CDF 0 R/W 0 R/W 0 R/W 0 R/W 16 0 R 0
SCGD 0 R/W 0 R/W
Rev. 1.0, 02/03, page 652 of 1294
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 to 2
SCGD
All 0
R/W
SCL Clock Generation Divider In master mode operation, the SCL clock is generated from the internal clock frequency using the SCGD value as the division ratio. In slave mode operation, if SCL is held low to stall the bus by data overflow, this clock is also generated from the internal clock. Accordingly, SCGD must be programmed for master and slave operating modes. The formula expressing the relationship is: Equation 2 SCL rate calculation SCL freq = IICck / (20 + SCGD * 8) Recommended settings for CDF and SCGD for 2 various CPU rates and the two I C bus speeds are given in table 19.3.
1, 0
CDF
All 0
R/W
Clock Division Factor The internal clocks for most of the blocks in the I C bus interface module are divided from peripheral 2 bus clock. The internal I C clock is generated from the peripheral clock using the value of CDF as the division ratio: 2 Equation 1 I C internal clock frequency calculation IICck = Pck / (1 + CDF) The minimum setup and hold times on the SMA line relative to the SCL line on the bus should be met. The clock frequency is to ensure that the glitch filtering will operate with glitches of up to 50 ns (as 2 described in the fast mode I C specifications). Note: CDF must be set to a value that the clock frequency (IICck) is less than 20 MHz.
2
Table 19.3 CDF and SCGD Recommended Values
100 kHz Pck 33 MHz Error 25 MHz Error 2 0.97% CDF 3 -1.79% 8 0 -8.08824% SCGD 8 CDF 2 -1.79% 6 400 kHz SCGD 1
Rev. 1.0, 02/03, page 653 of 1294
19.3.10 Receive/Transmit Data Registers (ICRXD/ICTXD) Reading from or writing to this register means accessing different physical internal registers. When data is to be transmitted, data in the shift register is loaded to TXD. After data has been 2 received into the shift register from the I C bus, data is loaded to RXD. * Receive Data Register (ICRXD) (Single Buffer Mode)
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 0 R/W 0 R/W 0 R/W 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 RXD 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 to 0
RXD
All 0
R/W
Read Receive Data Data received by master or slave.
* Transmit Data Register (ICTXD) (Single Buffer Mode)
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 0 R/W 0 R/W 0 R/W 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 TXD 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 to 0
TXD
All 0
R/W
Write Transmit Data Data transmitted by master or slave.
When the FIFO buffer is selected by the SDBS bit of ICSCR or the MDBS bit of ICMCR, the operation is as follows:
Rev. 1.0, 02/03, page 654 of 1294
* Receive Data Register (ICRXD) (FIFO Buffer Mode) ICRXD is a 16-stage FIFO register for storing the receive data. When 1-byte data is received, the receive data is transferred to ICRXD from the shift register, and reception ends. After that, the ICRXD is ready to receive and consecutive receive operations of up to 16 bytes of data are possible. When 16 bytes of receive data are stored, the FIFO receive register is full. ICRXD is read only and cannot be written to by the CPU. When the receive FIFO register is completely empty, reading ICRXD will return an undefined value. When the receive FIFO register is full, the subsequent data is lost.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R R R R R 23 R 7 22 R 6 21 R 5 20 R 4 RXD R R R R 19 R 3 18 R 2 17 R 1 16 R 0
* Transmit Data Register (ICTXD) (FIFO Buffer Mode) ICTXD is a 16-stage FIFO register for storing the transmit data. When the data is written to the ICTXD and the shift register is empty, the data is transferred from ICTXD to the shift register and transmission starts. ICTXD is write only and cannot be read from by the CPU. When the register is full with 16 bytes of data, the subsequent data cannot be written to, and the written value is ignored.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 W 15 W 30 W 14 W 29 W 13 W 28 W 12 W 27 W 11 W 26 W 10 W 25 W 9 W 24 W 8 W W W W W 23 W 7 22 W 6 21 W 5 20 W 4 TXD W W W W 19 W 3 18 W 2 17 W 1 16 W 0
19.3.11 FIFO Control Register (ICFCR) ICFCR is a register for resetting the byte count and setting the number of trigger data in transmit and receive FIFO registers, respectively. ICFCR can always be read from and written to by the CPU.
Rev. 1.0, 02/03, page 655 of 1294
Bit: Initial value: R/W: Bit: Initial value: R/W:
31 0 R 15 0 R
30 0 R 14 0 R
29 0 R 13 0 R
28 0 R 12 0 R
27 0 R 11 0 R
26 0 R 10 0 R
25 0 R 9 0 R
24 0 R 8 0 R
23 0 R 7
22 0 R 6
21 0 R 5
20 0 R 4
19 0 R 3
18 0 R 2
17 0 R 1
16 0 R 0
RTRG3 RTRG2 RTRG1 RTRG0 TTRG1 TTRG0 RFRST TFRST
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved. These bits are always read as 0. The write value should always be 0.
7 6 5 4
RTRG3 RTRG2 RTRG1 RTRG0
0 0 0 0
R/W R/W R/W R/W
Receive FIFO Data Count Trigger These bits specify the receive byte count to set ICFSR.RDF. The RDF flag is set to 1 when the receive byte count in ICRXD reaches the trigger byte count set in these bits. The following settings are available: 0000: 1 0001: 2 0010: 3 0011: 4 0100: 5 0101: 6 0110: 7 0111: 8 1000: 9 1001: 10 1010: 11 1011: 12 1100: 13 1101: 14 1110: 15 1111: 16
Rev. 1.0, 02/03, page 656 of 1294
Bit 3 2
Bit Name TTRG1 TTRG0
Initial Value 0 0
R/W R/W R/W
Description Transmit FIFO Data Count Trigger These bits specify the receive byte count to set ICFSR. TDFE. The RDF flag is set to 1 when the receive byte count in ICTXD is equal to or smaller than the trigger byte count set in these bits. The following settings are available: 00: 8 (8)* 01: 4 (12) 10: 2 (14) 11: 0 (16)
1
1
RFRST
0
R/W
Receive FIFO Data Register Reset Disables the receive data in ICRXD and resets ICRXD to the empty state. 0: The reset operation* is disabled 1: The reset operation is enabled
2
0
TFRST
0
R/W
Transmit FIFO Data Register Reset Disables the receive data in ICTXD and resets ICTXD to the empty state. 0: The reset operation* is disabled 1: The reset operation is enabled
2
Notes: *1. Values in parentheses ( ) indicate the number of empty stages in the transmit FIFO data register (ICTXD) in each case. *2. At power-on reset and manual reset, the reset operation is performed.
19.3.12 FIFO Status Register (ICFSR) ICFSR is a 32-bit register that indicates the operation state of the I C. ICFSR can always be written to and read from the CPU. However, writing 1 to the TEND, RDF and TDFE flags is not allowed. It is possible to write 0 to clear the flags.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 17 0 R 1 16 0 R 0
2
TEND RDF TDFE 0 R/W 0 R/W 1 R/W
Rev. 1.0, 02/03, page 657 of 1294
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved. These bits are always read as 0, and the write value should always be 0.
2
TEND
0
R/W
Transmit End Indicates the end of transmission with no valid data in ICTXD when the last bit of the character is transmitted. 0: Indicates transmission in progress [Clear conditions] * * Power-on reset, or manual reset When transmit data is written to ICTXD and 0 to the TEND flag.
1: Indicates transmission end [Set conditions] * When there is no transmit data in ICTXD when the last bit of the 1-byte character is transmitted.
1
RDF
0
R/W
Receive FIFO Data Full Indicates that the receive data is transferred from the shift register to ICRXD, and the byte count in ICRXD reaches the receive trigger byte count set in the RTRG3 to RTRG0 bits in ICFCR. When RDF is set to 1, the receive operation stops. Reading the receive data from ICRXD and clearing RDF to 0 will resume a receive operation. 0: Indicates that the byte count in ICRXD is smaller than the receive trigger byte count. [Clear condition] * * Power-on reset, or manual reset Reading from ICRXD has made the byte count in ICRXD smaller than the receive trigger byte count, and 0 is written to RDF.
1: Indicates that the byte count in ICRXD reaches the receive trigger byte count. [Set condition] * The byte count in ICRXD exceeds the receive 1 trigger byte count.*
Rev. 1.0, 02/03, page 658 of 1294
Bit 0
Bit Name TDFE
Initial Value 1
R/W R/W
Description Transmit FIFO Data Empty Indicates that the transmit data can be written to ICTXD, the data is transferred from ICTXD to the shift register, and the byte count in ICTXD is equal to or smaller than the trigger byte count set in the TTRG1 and TTRG0 bits of ICFCR. 0: Indicates that the byte count in ICTXD exceeds the transmit trigger byte count. [Clear condition] * When the byte count in ICTXD exceeds the transmit trigger byte count, and 0 is written to the TDFE bit.
1: Indicates that the byte count in ICTXD is equivalent to or smaller than the transmit trigger byte count. [Set condition] * * Power-on reset, or manual reset The byte count in ICTXD becomes equivalent to or smaller than the transmit trigger byte 2 count. *
Notes: *1 ICRXD is a 16-byte FIFO register. When RDF = 1, it is possible to read data of at least the receive trigger byte count. Reading empty ICRXD will return an undefined value. The receive byte count in ICRXD is indicated by ICRFDR. *2 ICTXD is a 16-byte FIFO register. When TDFE = 1, the maximum byte count that can be written to ICTXD is 16 minus the transmit trigger byte count. If the written byte count exceeds the maximum, the excess data is ignored. The byte count in ICTXD is indicated by ICTFDR.
19.3.13 FIFO Interrupt Enable Register (ICFIER) ICFIER is a register that enables or disables interrupt request from the FIFO operation source. ICFIER can always be read from and written to by the CPU.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 TEIE 0 R/W 17 0 R 1 RXIE 0 R/W 16 0 R 0 TXIE 0 R/W
Rev. 1.0, 02/03, page 659 of 1294
Bit 31 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved. These bits are always read as 0, and the write value should always be 0.
2
TEIE
0
R/W
Transmit End Interrupt Enable Enables or disables the generation of the transmit end interrupt (TEI) when the TEND flag of ICFSR is set to 1. 0: The transmit end interrupt (TEI) is disabled 1: The transmit end interrupt (TEI) is enabled
1
RXIE
0
R/W
Receive Interrupt Enable Enables or disables the generation of the receive data full interrupt (RXI) when the RDF flag of ICFSR is set to 1. 0: The receive data full interrupt (RXI) is disabled 1: The receive data full interrupt (RXI) is enabled
0
TXIE
0
R/W
Transmit Interrupt Enable Enables or disables the generation of the transmit FIFO data empty interrupt (TXI) when serial transmit data is transferred from ICTXD to the shift register, the byte count in ICTXD is equal to or smaller than the transmit trigger byte count, and the TDFE flag of ICFSR is set to 1. 0: The transmit FIFO data empty interrupt (TXI) is disabled 1: The transmit FIFO data empty interrupt (TXI) is enabled
19.3.14 Receive FIFO Data Count Register (ICRFDR) ICRFDR is a 32-bit register that indicates the byte count in ICRXD. The lower 5 bits indicate the number of receive bytes in ICRXD. ICRFDR can always be read by the CPU. H'0000 0000 indicates that ICRXD contains no receive data, while H'0000 0010 indicates that it is full of receive data.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 R4 0 R 19 0 R 3 R3 0 R 18 0 R 2 R2 0 R 17 0 R 1 R1 0 R 16 0 R 0 R0 0 R
Rev. 1.0, 02/03, page 660 of 1294
19.3.15 Transmit FIFO Data Count Register (ICTFDR) ICTFDR is a 32-bit register that indicates the byte count stored in ICTXD. The lower 5 bits indicates the number of transmit bytes in ICTXD. ICTFDR can always be read by the CPU. H'0000 0000 indicates that ICTXD contains no transmit data, while H'0000 0010 indicates the it is full of transmit data.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 T4 0 R 19 0 R 3 T3 0 R 18 0 R 2 T2 0 R 17 0 R 1 T1 0 R 16 0 R 0 T0 0 R
19.4
19.4.1
Operation
Data and Clock Filters
2
These blocks filter out glitches on signals coming from the I C bus. A glitch with a duration of up to one clock cycle is rejected. (See the description of the clock control register for details of 2 internal clock). This is specified for the faster I C bus rate (400 kHz) but does not violate the 2 slower I C bus rate specification. These blocks also perform resynchronization of bus signals to the internal clock. 19.4.2 Clock Generator
2
The clock generator has two functions. Firstly, it generates the SCL I C bus clock under command of the master or slave interface. Secondly, it controls the internal clock rate, used by filtering blocks and the master and slave interfaces. This operates as a clock-enable signal to the registers in the filter, master, and slave interfaces. 19.4.3 Master and Slave Interfaces
Master and slave interfaces run independently and in parallel. The master interface controls the 2 2 transmission of address and data on the I C bus. The slave interface monitors the I C bus and takes part in transmissions if its programmed address is seen on the bus. Both interfaces communicate with the control register and the status registers independently. Only one interrupt line comes from 2 the I C bus interface module; the source could be either the master or the slave.
Rev. 1.0, 02/03, page 661 of 1294
19.4.4
Software Status Interlocking
2
To make software interface to the I C bus interface module as robust and simple as possible, some statuses are interlocked in the master and slave interface operations. The status bits involved are described below. (1) MDR and SDR (Single Buffer Mode) MDR and SDR are set to 1 when data is received. Clear these bits to 0 after reading the receive data register. If data is received while MDR and SDR are 1, hardware recognizes that unread data remains in the receive data register, automatically holds SCL at low level and suspends data transfer. In this case, clearing these bits to 0 after reading the receive data will resume transfer. When receiving data consecutively, be sure to clear MDR and SDR to 0 after reading the receive data register. (2) MDE and SDE (Single Buffer Mode) When the slave or master is about to start transmission of data (from the transmit data register) 2 onto the I C bus, the MDE and SDE status bits may still remain 1. In such case, the SCL line must be held low until these bits are reset to 0. The MDE and SDE bits being set to 1 indicate 2 that the data has already been transmitted from the transmit data register onto the I C bus. To write data into the transmit data register that is ready for the next transmission, the software must clear MDE and SDE to 0. However, this is not required for the first byte transmission onto the bus. (3) MAL When the master has lost arbitration, the MAL bit in the master status register is set to 1 and the MIE bit in the master control register is reset to 0. At this point, the master mode is 2 disabled and the I C bus interface is set to operate in the slave mode. When master operation is restarted, data transfer from the master begins after the MAL bit has been cleared to 0. (4) SAR The SAR status bit is set to 1 when the slave has recognized its address output to the I C bus. At this point, the slave interface drives the SCL line to be low until the SAR status bit is reset to 0. This is particularly important when a slave transmit is about to take place on the bus. When the slave transmits the data from the transmit data register, the software responds to the SAR status by writing the required data into the transmit data register and resetting the SAR status bit to 0. This allows the slave interface to carry on access. When the slave is about to receive data, the software may not have completed reading of data loaded by the previous access from the receive data register. The problem is that the new
Rev. 1.0, 02/03, page 662 of 1294
2
access may overwrite the valid data still held in the receive data register. However, this can be avoided by using the SAR status bit. The software should reset the SAR bit to 0 (if it is set to 1) only after completing a read from the receive data register. Then the receive data register will not be overwritten. (5) Writing to ICTXD and the TDFE Flag (FIFO Buffer Mode) The TDFE flag of ICFSR is set to 1 when the byte count in ICTXD is equal to or smaller than the transmit trigger byte count by TTRG1 and TTRG0 bits of ICFCR. After TDFE is set, the transmit data can be written for the number of empty bytes in ICTXD. This allows efficient continuous transmission. When the byte count in ICTXD is below the transmit trigger count, the TDFE flag is automatically set to 1 even if the flag is cleared to 0. Accordingly, clear the TDFE flag to 0 only when the byte count in ICTXD exceeds the transmit trigger byte count. The transmit byte count in ICTXD can be informed by ICTFDR. (6) Reading from ICRXD and the RDF Flag (FIFO Buffer Mode) The RDF flag of ICFSR is set to 1 when the receive byte count in ICRXD reaches the receive trigger byte count by RTRG3 to RTRG0 bits of ICFCR. After RDF is set, the receive data for the trigger byte count can be read from ICRXD. This allows efficient continuous reception. When the byte count in ICRXD is equivalent to or greater than the trigger count after a read, the RDF flag is cleared to 0 even if it is set to 1 again. Accordingly, read the RDF flag as 1 and then clear it to 0 after reading all data. The receive byte count in ICRXD can be informed by ICRFDR. 19.4.5 I C Bus Data Format
2 2
Figure 19.2 shows the bus timing of the I C bus interface. Table 19.4 describes legend in figure 19.2.
SDA
SCL S
1-7 SLA
8 R/W
9 A
1-7 DATA
2
8
9 A
1-7
8
9 P A/A
DATA
Figure 19.2 I C Bus Timing
Rev. 1.0, 02/03, page 663 of 1294
Table 19.4 Legend in I C Bus Data Format
Symbol S SLA R/W Description Start condition. The master device drives SDA from high to low level while SCL is high level. Slave address. The slave address is selected by the master device. Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Data acknowledge. Data receive device drives SDA to low level. The slave device returns a data acknowledge signal in master transmit mode. Transfer data. The data consists of 8 bits, which are transferred from MSB. Stop condition. The master device drives SDA from low to high level while SCL is high level.
2
A DATA P
19.4.6
7-Bit Address Format
Figure 19.3 shows the format of data transfer from the master to the slave device (master data transmit format). Figure 19.4 shows the data transfer format (master data receive format) in which the master device read data on and after the second byte from the slave device.
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
Data transferred (n bytes + ACKNOWLEDGE) 0 (Write) : From MASTER to SLAVE : From SLAVE to MASTER A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) S = Start condition P = Stop condition
Figure 19.3 Master Data Transmit format
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
Data transferred (n bytes + ACKNOWLEDGE) 1 (Read)
Figure 19.4 Master Data Receive format Figure 19.5 shows the combination transfer format in which the data transfer direction changes during one transfer.
Rev. 1.0, 02/03, page 664 of 1294
When changing the direction at the first transfer, retransmit command (Sr), the slave address and the R/W signal are transmitted. In this case, the R/W signal is set to the direction opposite to the first transfer direction.
S
SLAVE ADDRESS
R/W
A DATA
A/A
Sr
SLAVE ADDRESS
R/W
A DATA
A/A
P
Read or Write
(n bytes +ACK.)*
Read or Write Sr = Restart condition
(n bytes +ACK.)*
Direction of transfer may change at this point
Note: * Transfer direction of data and acknowledge bits depend on R/W bits.
Figure 19.5 Combination Transfer Format of Master Transfer 19.4.7 10-Bit Address Format
Description is given below on the 10-bit address transfer format supported in the master mode. This format has three transfer methods as the 7-bit address transfer format. Figure 19.6 shows the data transfer format. The set value of the master address register is output in one byte following the first transfer condition (S). The value set in transmit data register (ICTXD) is transmitted as a slave address in the second byte. Data transfer on and after the third byte is done in the same way as the 7-bit address data transmission.
11110XX S SLAVE ADDRESS 1st 7 bits of 1st byte 0 (write) R/W A1 SLAVE ADDRESS A2 2nd byte DATA A DATA A/A P
Data transferred (n bytes + ACKNOWLEDGE)
Figure 19.6 10-Bit Address Data Transfer Format
Rev. 1.0, 02/03, page 665 of 1294
Figure 19.7 show the data receive format. Address transmission of two bytes in the data receive format is done in the same way as in the data transfer format. Then, retransmit condition (Sr) is transmitted and the value set in the master address register is output. At this time, STM1 must be set to 1 (receive mode). Data transfer is done in the same way as in the 7-bit address data receive format.
11110XX S SLAVE ADDRESS 1st 7bits of 1st byte 0 (Write) R/W A1 SLAVE ADDRESS A2 2nd byte
11110XX Sr SLAVE ADDRESS 1st 7bits of 1st byte 1 (Read) Data transferred (n bytes + ACKNOWLEDGE) R/W A3 DATA A DATA AP
Figure 19.7 10-Bit Address Data Receive Format Figure 19.8 shows the data transmit/receive combination format In the data transmit/receive combination format, data is transmitted after an address is transmitted with the first two bytes. Then, retransmit condition (Sr) is transmitted instead of stop condition (P). After Sr is transmitted, the procedure is the same as that in the data receive format.
11110XX S SLAVE ADDRESS 1st 7bits of 1st byte 0 (Write) R/W A1 SLAVE ADDRESS A2 2nd byte Data transferred DATA A DATA A/A
11110XX Sr SLAVE ADDRESS 1st 7 bits of 1st byte 1 (Read) Data transferred R/W A3 DATA A DATA AP
Figure 19.8 10-Bit Address Transmit/Receive Combination Format 19.4.8 Master Transmit Operation (Single Buffer Mode)
This section describes the transmit procedure and operations in master transmit mode. Figures 19.9 to 19.11 are the timing charts in master transmit mode. Setting the MDBS bit to 1 in the 2 master control register has the I C module enter single buffer mode. However, there is a timing restriction on a write of the second and following bytes to the ICTXD register and a set of the FSB bit to 1. For details, see 19.7, Usage Notes.
Rev. 1.0, 02/03, page 666 of 1294
1. For initial setting, set clock control bits in the clock control register and interrupt generation bits in the master interrupt enable register, according to the slave address, transmit data, and the transmit speed. Since the slave mode is also required even when only the master mode is used, set the device address to the slave address register. 2. Monitor the FSDA bit in the master control register. Confirm that the bit is low, which means 2 that the other I C device is not using the bus. After confirmation, set the MIE bit and ESG bit in the master control register to 1 to start master transmission. 3. After the signals for indicating the transmit start condition, the slave address, and the data transfer direction are transmitted, an interrupt indicated by the MDE bit and the MAT bit in the master status register is generated in the timing of (1) in figure 19.9. At this time, clear the ESG bit to 0. The master device holds SCL low to suspend data transmission until the MDE bit is cleared to 0. 4. Interrupt indicated by the SAR is generated in the timing of (3) in figure 19.9. If the IRQ processing of the slave device is delayed, the slave device extends the SCL period to suspend data transmission (in the timing of (7) in figure 19.9). The slave device drives SDA low at the ninth clock and returns ACK. 5. Data transmission is done in units of eight bits plus one bit of ACK, i.e., in units of nine bits. An interrupt by MDE (bit 3) is generated at the ninth clock before starting data transfer (in the timing of (2) in figure 19.9). An interrupt by MDT (bit 2) is generated at the eighth clock after 1-byte data transfer (in the timing of (4) in figure 19.9). Clear MDE to 0 after setting transmit data. An interrupt by the SDR bit (slave data reception) is generated at the eighth clock (in the timing of (6) in figure 19.9). Clear the SDR bit to 0 after the slave device reads the receive data. If this processing is delayed, the slave device extends the SCL period to suspend data transmission (in the timing of (8) in figure 19.9). 6. To end data transfer, an interrupt by the MNR (bit 6) in the master status register is generated at the ninth clock while the ACK signal from the slave device is 1 (NACK) (in the timing of (5) in figure 19.9). The master device outputs a data transfer end condition when receiving the NACK. When the master device completes the data transmission, set FSB (bit 1) to 1 in the master control register to output a force stop condition. When the last bit of a byte is 2 transmitted/received, the I C module latches the FSB value and enters the stop state. Therefore, to stop the transfer after a specified byte is transferred, the FSB bit must be set to 1 before the last byte data is transferred. The FSB bit must be set to 1 before the last byte is transferred. In master transmit mode, after the last byte is set, the MST (master stop transmission) bit is checked using an interrupt or polling. At this time, the MNR (master NACK reception) is checked. When the NACK is returned, an error routine is executed to re-transmit the last byte data.
7.
The timings of (1) to (6) in figure 19.9 are generated after the falling edge of the clock signal.
Rev. 1.0, 02/03, page 667 of 1294
SDA SCL S SDA (Master output) SDA (Slave output)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
1
2
3
4
5
6
7
8
9
1
ACK
Master IRQ (1) Slave IRQ (3) (7) SDA SCL SDA (Master output) SDA (Slave output) (4) (2) Slave IRQ (6) (8) (5) (2) 9 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7
1
2
3
4
5
6
7
8
9
1
ACK
Master IRQ
Figure 19.9 Data Transfer Mode Timing Chart 19.4.9 Master Receiver Operation (Single Buffer Mode)
Data receive procedure and operation in master receiver mode is described below. Figure 19.10 shows the operation timing in master data receive mode. Setting the MDBS bit in the master 2 control register makes the I C module enter single buffer mode. 1. In master data receive mode, operation is the same as that in master data transmit mode as to transmit of a slave address and a 1-byte signal indicating the data transfer direction. At this time, however, select 1 (receive) for the data transfer direction. 2. The slave device automatically enters data transmission mode by the signal that indicates the data transfer direction and transmits 1-byte data in synchronization with the SCL clock output from the master device. The master device generates an interrupt by MDR (bit 1) at the eighth clock (in the timing of (2) in figure 19.10). Clear the MDR bit to 0 after the master device reads receive data. If this processing is delayed, the slave device extends the SCL period to suspend data transmission. (in the timing of (3) in figure 19.10.)
Rev. 1.0, 02/03, page 668 of 1294
3. The slave device generates an interrupt by SDT (bit 2) indicating 1-byte data transfer end at the eighth clock (in the timing of (2) in figure 19.10) and an interrupt by SDE (bit 3) indicating data empty at the ninth clock (in the timing of (1) in figure 19.10). Clear SDE to 0 after writing slave transmit data to TXD. 4. To end data transfer, set FSB (bit 1) to 1 in the master control register in the master device to 2 output a transfer end (force stop). When the last bit of a byte is transmitted/received, the I C module latches the FSB value and enters the stop state. Therefore, to stop the transfer after a specified byte data is transferred, the FSB bit must be set before the last byte is transferred. If the last byte is not correct, the protocol layer notifies the slave device that re-transmission is needed. The timings of (1) to (3) in figure 19.10 are generated at the falling edge of the clock signal.
SDA
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
SCL SDA (Master output) SDA (Slave output) Master IRQ
9
1
2
3
4
5
6
7
8
9
1
ACK
Slave IRQ (1)
(2) (1) (3)
Figure 19.10 Data Receive Mode Timing Chart 19.4.10 Standby Mode Communications are unavailable in standby mode because clock supply stops. When entering the standby mode, terminate communications and check the status of the registers using the steps described below. Carry out the following steps if communications are in progress: 1. When completing communication in I C master mode, check that the MST bit of ICMSR is 1 and clear the MIE bit of ICMCR to 0. 2. When completing communication in I C slave mode, check that SSR bit of ICSSR is 1 and clear SIE bit of ICSCR to 0. Carry out the following steps if communications are NOT in progress:
Rev. 1.0, 02/03, page 669 of 1294
2 2
1. Check that the MIE bit of ICMCR is 0. 2. Check that the SIE bit of ICSCR is 0. 3. Monitor the status of the FSCL and FSDA bits of ICMCR to check that FSCL is 1 and FSDA is 0. (Determine the timing for monitoring according to the SCL frequency to be used). When the MIE and SIE bits are 1, check that communications are not in progress and clear these bits to 0.
19.5
FIFO Mode Operation
In FIFO mode, the 16-stage FIFO buffer can be used. Registers related to the FIFO mode are ICFCR, ICFSR, ICFIER, ICRFDR, and ICTFDR. For details, refer to the description of these registers. In FIFO mode, interrupt overhead can be reduced since transfer is performed in units of bytes specified by ICFCR. 19.5.1 Master Transmitter Operation (FIFO Buffer Mode)
1. The MDE bit and the MAT bit are set to 1 at the same timing, as in single buffer mode. At this time, the ESG bit should be cleared to 0. The master device holds SCL low level until the MDE bit is cleared to 0 in order to suspend data transfer. 2. The FSB should be set to 1 when the transmit end flag (TEND) is set to 1. For example, to transmit 3-byte data, write the 3 bytes to the FIFO and transmit the data. Then set the FSB bit to 1 after the transmit completion is notified by an TEND interrupt. 19.5.2 1. 2. 3. Master Receiver Operation (FIFO Buffer Mode)
Clear the ESG bit to 0 when the RDF bit is set to 1 by receiving data for the byte count specified by the register. The receive byte count specified by the RTRG bits in ICFCR can be selected from 1 to 16. When the receive byte count reaches the specified count, an RDF interrupt is generated (RXIE = 1) and receive operation is stopped. The ACK signal is automatically returned until the RDF bit is set to 1. Read all the receive data in the receive FIFO by the CPU when the RDF interrupt occurs. (Dummy-reading or reading before an RDF interrupt generation is not allowed.) However, if issuing a STOP condition is needed, carry out step 6. To resume receive operations, read all the receive data in the receive FIFO with FSB = 0 and then clear the RDF flag in ICFSR to 0. (Modify the RTRG bits before clearing the RDF flag, if necessary.) In order to issue a STOP condition, set the FSB bit to 1 and wait at least on bit period. Then read all the receive data in the receive FIFO and clear the RDF flag to 0. (The FSB bit must be set only in this timing).
4.
5.
6.
Rev. 1.0, 02/03, page 670 of 1294
7.
In order to forcibly stop the receive operation before the receive byte count reaches the RTRG setting, manually control (start/stop) the FSCL bit and the FSDA bit in ICMCR and read data for the receive byte count indicated by ICRFDR from the receive FIFO.
19.6
19.6.1
Programming Examples
Master Transmitter (Single Buffer Mode)
2
In order to set up the master interface to transmit a data packet on the I C bus, take the following steps. (1) Load the clock control register: (a) Set SCL clock generation divider (SCGD) to 01h. (SCL frequency of 400 kHz) (b) Set clock division ratio to 2h. 2 (Peripheral clock: 33 MHz and I C internal clock (IICck): 11 MHz) (2) Load the master control register, first data byte and address: (a) Set address of slave being accessed to the master address register and the STM1 bit (write mode: 0). (b) Set the first byte to be transmitted to the transmit data register. (c) Set the master control register to 89h. (MDBS = 1, MIE = 1, and ESG = 1) (3) Wait for the address to be output: (a) Wait for master events (interrupts by the MAT and MDE bits in the master status register). (b) Set the master control register to 88h (the master device holds the SCL low level until the MDE bit is cleared in order to suspend the data transmission). If only one data byte is to be transmitted, set the master control register 8Ah. (This enables the stop generation). This generates a stop on the bus as soon as one byte has been transmitted. (c) Reset the MAT and MDE bits to 0. (4) Monitor the progress of data byte transmission: (a) Set the next byte to the transmit data register. (This must be done before the first byte is completely output.) (b) Wait for a master event (the MDE bit in the master status register). (c) Reset the MDE bit. Clear the MDE bit after setting the last transmit byte. After transmission of the last byte is started, MDE is generated. Before clearing the MDE bit, set 8Ah in the master control register (this must be done before the last transmission byte is completely output).
Rev. 1.0, 02/03, page 671 of 1294
(Set the force stop bit.) (5) Wait for the end of transmission: (a) Wait for a master event (the MST bit in the master status register). (b) Reset the MST bit after checking MNR (master NACK received). 19.6.2 Master Receiver (Single Buffer Mode)
2
In order to set up the master interface to receive a data packet on the I C bus, take the following steps. (1) Load the clock control register: (a) Set SCL clock generation divider (SCGD) to 01h. (SCL frequency of 400 kHz) (b) Set clock division factor (CDF) is set to 2h. (Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz) (2) Load the master control register and address: (a) Set address of slave being accessed to master address register and the STM1 bit (read mode: 1). (b) Set the Master Control Register to 89h. (MDBS = 1, MIE = 1, and ESG = 1) (3) Wait for the address to be output: (a) Wait for master events (interrupts by the MAT bit and MDR bit in the master status register). (b) Set the master control register to 88h (the master device keeps the SCL low level until the MDR bit is cleared in order to suspend the data reception). If only one data byte is to be transmitted, set the master control register 8Ah. (This enables the stop generation). This generates a stop on the bus as soon as one byte has been received. (c) Reset the MAT bit to 0. (4) Monitor the progress of data byte reception: (a) Wait for a master event (the MDR bit in the master status register). (b) Read data from receive data register. If the byte preceding the last byte transmitted by the slave device is to be received, for the last one-byte receive interrupt, i.e., MDR interrupt, (c) Set the master control register to 8Ah. (Set the force stop control bit). (d) Reset the MDR bit. (5) Wait for the end of transmission:
Rev. 1.0, 02/03, page 672 of 1294
(a) Execute processing of the last byte receive interrupt (MDR), i.e., extract the data and clear MDR. (b) Wait for a master device's event (the MST bit in the master status register). (c) Reset the MST bit to 0. 19.6.3 Master Transmitter--Restart--Master Receiver (Single Buffer Mode)
2
In order to set up the master interface for transmitting data packets to the I C bus, issuing a restart, and reading data back from the slave, take the following steps. (1) Load the clock control register: (a) Set SCL clock generation divider (SCGD) 01h. (SCL frequency of 400 kHz) (b) Set clock division ratio (CDF) is set to 2h. (Off-chip clock(sysclockfreq): 33MHz, on-chip clock (clockfreq): 11 MHz) (2) Load the master control register and address: (a) Set address of slave being accessed to the master address register and the STM1 bit (write mode: 0). (b) Set the master control register to 89h. (MDBS = 1, MIE = 1, and ESG = 1) (3) Wait for the address to be output: (a) Wait for master device's events (interrupts by the MAT bit and the MDE bit in the master status register). (b) Set address of slave being accessed to the master address register and the STM1 bit (read mode: 1). If the enable start generation bit in the master control register is still set to 1, the master will issue a restart at the end of the byte transmission. Since the new address has been loaded as described above, the bus direction will be turned around. (c) Reset the MAT bit to 0. (4) Wait for the address to be output: (a) Wait for master device's events (interrupts by the MAT bit and the MDR bit of the master status register). (b) Set the master control register to 88h. (The master device holds the SCL low level in order to suspend the data reception until the MDR bit is cleared to 0). (c) Reset the MAT bit to 0. (5) Monitor the progress of data byte reception: (a) Wait for a master event (the MDR bit in the master status register).
Rev. 1.0, 02/03, page 673 of 1294
Read data from the receive data register. If next byte is to be the data immediately preceding the last byte transmitted by the slave device, for the receive interrupt for the byte immediately preceding the last one-byte, i.e., MDR interrupt, (b) Set the master control register 8Ah. (Set the force stop control bit.) (c) Reset the MDR bit to 0. (6) Wait for the end of transmission: (a) Execute processing of the last byte receive interrupt (MDR), i.e., extract the data and clear MDR. (b) Wait for the master device's event (the MST bit in the master status register). (c) Reset the MST bit to 0. 19.6.4 Master Transmitter (FIFO Buffer Mode)
Operation example: 1. Set the clock rate to ICCCR. 2. Set the slave address, etc. to ICMAR. 3. Write transmission data to ICTXD (up to 16 bytes can be written). 4. Clear the TDFE flag. 5. ICMCR=H'0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0. (At this point, the slave address 2 is output onto I C bus.) 6. Wait for MAT to be set to 1, and clear ESG, MAT, and MDE to 0. (Transmission data has been output until FIFO becomes empty.) 7. Wait for TDFE to be set to 1, and write subsequent transmit data to ICTXD. ICFSR=H'0000 0000 (Clear the flag.) (Repeat) 8. Wait for TEND to be set to 1, and set FSB to 1. 9. Clear the TEND flag to 0.
19.6.5
Master Receiver (FIFO Buffer Mode)
Operation example: 1. Set the clock rate to ICCCR. 2. Set the slave address, etc. to ICMAR. 3. Set the RDF trigger value to ICFCR.
Rev. 1.0, 02/03, page 674 of 1294
4. ICMCR=H'0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0. (At this point, the slave address 2 is output onto I C bus.) 5. Wait for MAT, and clear ESG. 6. ICFSR=H'0000 0000 (Clear the flag.) 7. Wait for TDFE, and read the data received from ICRXD. ICFSR=H'0000 0000 (clear the flag) (Repeat) If setting FSB to 1, wait for one bit period after setting RDF to 1 and read the data received from ICRXD. 8. Set FSB to 1. 9. ICFSR=H'0000 0000 (Clear the flag.)
19.7
19.7.1
Usage Notes
Restriction 1
For a master transmitter in single buffer mode, the following restriction should be taken into account. There is a restriction on a write of the second and following bytes to ICTXD register and a set of FSB to 1. Details are discussed it in the following paragraphs. For details of master transmitter operation in single buffer mode, see 19.4.8, Master Transmitter Operation (Single Buffer Mode). This section mainly describes flag manipulation in relation to the restriction. Below shown are operational examples for transmission of one-byte, two-byte, and three-byte data. When two or more bytes are transmitted, writing of the second and third bytes is subject to the timing restriction. Meanwhile, single-byte data transmission has no timing restriction. When transmitting three or more bytes, delay manipulation of the third byte transmission will remove the timing restriction on writing of the succeeding transmit bytes. (Transmission is stopped with the MDE flag being set to 1.) (1) One-byte data transmission Figure 19.11 shows an operational example of one-byte data transmission. Write data 1 before clearing the MAT and MDE flags to 0 in (2) (for example, in initial setting preceding the issue of start conditions.). Once the MDE flag is cleared, data transmission starts. Set the FSB flag to 1 at the timing between (1) and (3) (for example, before the MAT and MDE flags are cleared in (2)).
Rev. 1.0, 02/03, page 675 of 1294
MAT flag MDE flag MDT flag S SLAVE ADDRESS Write data1 Set FSB Software (1) (2) Clear MAT and MDE [Legend] S: Start condition P: Stop condition A: Acknowledge (3) A DATA1 AP I2C bus Hardware
Figure 19.11 Operational Example of One-byte Data Transmission
(2) Two-byte data transmission Figure 19.12 shows an operational example of two-byte data transmission. Write data 1 before clearing the MAT and MDE flags to 0 in (2) (for example, in initial setting preceding the issue of start conditions.). Once the MDE flag is cleared, data transmission starts.
[Restriction]
Write data 2 within eight SCL clock cycles after clearing the MAT and MDE flags in (2).
Otherwise, data 1 is transmitted twice. If it is impossible to write data 2 within eight SCL clock cycles due to long interrupt processing time, use FIFO buffer mode. Set the FSB flag to 1 at the timing between (4) and (5) (for example, when the MDE flag is set to 1).
Rev. 1.0, 02/03, page 676 of 1294
MAT flag MDE flag MDT flag S SLAVE ADDRESS Write data1 A DATA2 Write data2 Set FSB Software (1) (2) Clear MAT and MDE [Legend] S: Start condition P: Stop condition A: Acknowledge (3) (4) (5) A DATA2 AP I2C bus Hardware
Figure 19.12 Operational Example of Two-byte Data Transmission
(3) Transmission of three or more bytes Figure 19.13 shows an operational example of three-byte data transmission. Write data 1 before clearing the MAT and MDE flags in (2) (for example, in initial setting preceding the issue of start conditions). Once the MDE flag is cleared, data transmission starts. [Restriction] Write data 2 within eight SCL clock cycles after clearing the MAT and MDE flags in (2).
Otherwise, data 1 is transmitted twice. If interrupt processing time is too long to write data 2 within eight SCL clock cycles, use FIFO buffer mode. Write data 3 only after the timing of (8), and hold the MDE flag as 1 until the timing of (8). (If MDE is set to 1 in (4), refrain from writing data 3 and hold MDE as 1 until (8)). After delaying a write of data 3, write the succeeding transmit data and set FSB to 1 at the moment of a transmission stop with MDE =1. Then the fourth and succeeding bytes can be transmitted without time restriction. To get the timing of (8) ((5) + extra time (1 SCL): it may be longer depending on the system), use the MDT flag. To get the timing at which the MDT flag is set in (5), clear the MDT flag to 0 beforehand within eight SCL clock cycles after the MDT flag is first set to 1 (between (6) and (7)). If it is difficult to make the timing of (8), use FIFO buffer mode.
Rev. 1.0, 02/03, page 677 of 1294
MAT flag MDE flag MDT flag S SLAVE ADDRESS Write data1 A DATA1 Write data2 A DATA2 A Write data3 Set FSB (1) (2) Clear MAT and MDE [Legend] S: Start condition P: Stop condition A: Acknowledge (6) (3) (4) Clear MDT (7) (5) (10) (9) Clear MDE and MDT (8) Software DATA3 AP I2C bus Hardware
Figure 19.13 Operational Example of Three-byte Data Transmission
An example of transmission of data exceeding three bytes is as follows:
MDE flag MDT flag Hardware
DATA3 Write data4
A
DATA4 Write data5
A
DATA5
AP
I2C bus
Set FSB (11) (10) (13) (14) (15) (9) Clear MDE and MDT [Legend] S: Start condition P: Stop condition A: Acknowledge (12) Clear MDE and MDT (16) Clear MDE and MDT (17) (18) Software
Figure 19.14 Operation Example of Four or More Byte Data Transmission
19.7.2
Restriction 2
2
For the STOP operation in I C master mode, there is a timing restriction on FSB setting.
Rev. 1.0, 02/03, page 678 of 1294
Single buffer mode assumes to carry out a predefined number of byte transfers. The current circuit fetches the value of the FSB bit when the last bit of one byte is transmitted or received, and proceeds to the STOP operation. Consequently, to stop communications after the transfer of a specified number of bytes, the FSB bit should be set to 1 before the last byte is transferred. This timing, however, contains a problem. In transmission mode, FSB is set to 1 BEFORE an ACK/NACK to the last byte is checked. For this, the following software actions are required. * Software Actions The FSB bit must be set before the last eight bits are transmitted or received as mentioned above. In the case of transmission, ACK/NACK to the last byte needs to be checked. For example, the software should operate as follows. In master transmitter mode, the software checks the MST (transmission end) bit by interrupt or polling after the last byte is set. At the same time, it checks MNR (master NACK received). If NACK is returned, it makes a branch to the error routine where the last byte is retransmitted. In master receiver mode, the software ends reception after confirming that the last byte has been received. However, if the last byte has any defect, it issues a retransmission request by the upper protocol.
Rev. 1.0, 02/03, page 679 of 1294
Rev. 1.0, 02/03, page 680 of 1294
Section 20 Serial Sound Interface (SSI) Module
The serial sound interface (SSI) module is a module designed to send or receive audio data interface with a variety of devices offering Philips format compatibility. It also provides additional modes for other common formats, as well as support for a burst and multi-channel mode.
20.1
Features
The SSI has the following features. * Number of channels: Two channels (maximum) * Operating modes: Compressed mode and non-compressed mode The compressed mode is used for continuous bit stream transfer The non-compressed mode supports all serial audio streams divided into channels. * The SSI module is configured as any of a transmitter or receiver. The serial bus format can be used in the compressed and non-compressed mode. * Asynchronous transfer between the buffer and the shift register * Division ratios of the serial bus interface clock can be selected. * Data transmission/reception can be controlled from the DMAC or interrupt. Figure 20.1 is a block diagram of the SSI module.
Rev. 1.0, 02/03, page 681 of 1294
SSI bridge bus Interrupt request SSI module Control circuit Register SSICR SSISR SSITDR SSIRDR Data buffer DMA request
Serial audio bus SSI_SDATA MSB
Barrel shifter
Shift register
LSB
SSI_SCK Bit counter
SSI_WS
Serial clock control Divider
HAC_BIT_CLK
Figure 20.1 Block Diagram of SSI Module
20.2
Input/Output Pins
Table 20.1 lists the pin configurations relating to the SSI module. Table 20.1 Pin Configuration
Name SSI_SCK0 SSI_WS0 SSI_SDATA0 HAC_BIT_CLK0 SSI_SCK1 SSI_WS1 SSI_SDATA1 HAC_BIT_CLK1 Number of Pins 1 1 1 1 1 1 1 1 I/O Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input Function Serial bit clock Word select Serial data input/output Divider input clock (oversampling clock) Serial bit clock Word select Serial data input/output Divider input clock (oversampling clock)
Rev. 1.0, 02/03, page 682 of 1294
20.3
Register Descriptions
The SSI module has the following registers. As for addresses of these registers and register status in each processing state, see section 32 List of Registers. Note that the initial value of SSISR is determined depending on the settings of the SCKD and CKDV bits in SSICR after the clock is supplied. Distinction with channels is omitted for the description of this document. Table 20.2 Register Configuration (1)
Ch. 0 Register Name Control register 0 Status register 0 Transmit data register 0 Receive data register 0 1 Control register 1 Status register 1 Transmit data register 1 Receive data register 1 Abbrev. SSICR0 SSISR0 SSITDR0 SSIRDR0 SSICR1 SSISR1 SSITDR1 SSIRDR1 R/W R/W R/W*1 R R R/W R/W* R R
1
P4 Address HFE68 0000 HFE68 0004 HFE68 0008 HFE68 000C HFE69 0000 HFE69 0004 HFE69 0008 HFE69 000C
Area 7 Address H1E68 0000 H1E68 0004 H1E68 0008 H1E68 000C H1E69 0000 H1E69 0004 H1E69 0008 H1E69 000C
Size 32 32 32 32 32 32 32 32
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck
Table 20.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Ch. Register Name Abbrev. H-UDI Manual Reset by RESET Pin/WDT/ Multiple Exception Sleep by Sleep Instruction/ by Deep Sleep Hardware by Software/ Each Module Standby
0
Control register 0 Status register 0 Transmit data register 0 Receive data register 0
SSICR0 SSISR0 SSITDR0
H0000 0000 H0000 0000 Retained H0200 0003 H0200 0003 Retained H0000 0000 H0000 0000 Retained
*
Retained Retained Retained Retained Retained Retained Retained Retained
SSIRDR0 H0000 0000 H0000 0000 Retained SSICR1 SSISR1 SSITDR1 H0000 0000 H0000 0000 Retained H0200 0003 H0200 0003 Retained H0000 0000 H0000 0000 Retained
1
Control register 1 Status register 1 Transmit data register 1 Receive data register 1
SSIRDR1 H0000 0000 H0000 0000 Retained
Notes: *
When exiting hardware standby mode, this module is entered in the power-on reset state by the RESET pin. *1 Bits 27 and 26 allow a write of 0 only to clear the flag.
Rev. 1.0, 02/03, page 683 of 1294
20.3.1
Control Register (SSICR)
SSICR is a 32-bit readable/writable register that controls the IRQ, selects each polarity status, and sets operating mode.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15
SCKD
30 R 14
SWSD
29 R 13
SCKP
28
DMEN
27
UIEN
26
OIEN
25
IIEN
24
DIEN
23
CHNL1
22
CHNL0
21
DWL2
20
DWL1
19
DWL0
18
SWL2
17
SWL1
16
SWL0
0 R/W 12
SWSP
0 R/W 11
SPDP
0 R/W 10
SDTA
0 R/W 9
PDTA
0 R/W 8
DEL
0 R/W 7
BREN
0 R/W 6 0 R/W
0 R/W 5
CKDV
0 R/W 4 0 R/W
0 R/W 3
MUEN
0 R/W 2
CPEN
0 R/W 1
TRMD
0 R/W 0
EN
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. DMA Enable Enables or disables the DMA request. 0: DMA request disabled. 1: DMA request enabled.
31 to 29
28
DMEN
0
R/W
27
UIEN
0
R/W
Underflow Interrupt Enable 0: Underflow interrupt disabled 1: Underflow interrupt enabled
26
OIEN
0
R/W
Overflow Interrupt Enable 0: Overflow interrupt disabled 1: Overflow interrupt enabled
25
IIEN
0
R/W
Idle Mode Interrupt Enable 0: Idle interrupt disabled 1: Idle interrupt enabled
24
DIEN
0
R/W
Data Interrupt Enable 0: Data interrupt disabled 1: Data interrupt enabled
23 22
CHNL1 CHNL0
0 0
R/W R/W
Channels These bits indicate the number of channels in each system word. These bits are ignored if CPEN = 1. 00: 1 channel per system word 01: 2 channels per system word 10: 3 channels per system word 11: 4 channels per system word
Rev. 1.0, 02/03, page 684 of 1294
Bit 21 20 19
Bit Name DWL2 DWL1 DWL0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Data Word Length These bits indicate the encoded number of bits in a data word. These bits are ignored if CPEN = 1. 000: 8 Bits 001: 16 Bits 010: 18 Bits 011: 20 Bits 100: 22 Bits 101: 24 Bits 110: 32 Bits 111: Setting prohibited
18 17 16
SWL2 SWL1 SWL0
0 0 0
R/W R/W R/W
System Word Length These bits indicate the encoded number of bits in a system word. These bits are ignored if CPEN = 1. 000: 8 Bits 001: 16 Bits 010: 24 Bits 011: 32 Bits 100: 48 Bits 101: 64 Bits 110: 128 Bits 111: 256 Bits
15
SCKD
0
R/W
Serial Bit Clock Direction 0: Serial clock input, slave mode 1: Serial clock output, master mode
14
SWSD
0
R/W
Serial WS Direction 0: Serial word select input, slave mode 1: Serial word select output, master mode
Rev. 1.0, 02/03, page 685 of 1294
Bit 13
Bit Name SCKP
Initial Value 0
R/W R/W
Description Serial Clock Polarity 0: SSI_WS and SSI_SDATA change on falling edge of SSI_SCK (sampled on rising edge of SCK) 1: SSI_WS and SSI_SDATA change on rising edge of SSI_SCK (sampled on falling edge of SCK)
SCKP = 0 SSI_SDATA input SSI_SCK sampling timing in receive rising edge mode (TRMD = 0) SSI_SDATA output change timing in transmit mode (TRMD = 1) SSI_SCK falling edge SCKP = 1 SSI_SCK falling edge SSI_SCK rising edge SSI_SCK falling edge SSI_SCK rising edge
SSI_WS input sampling in SSI_SCK slave mode (SWSD = 0) rising edge SSI_WS output change timing in master mode (SWSD = 1) SSI_SCK falling edge
12
SWSP
0
R/W
Serial WS Polarity The function of this bit depends on whether the SSI module is in non-compressed mode or compressed mode. CPEN = 0 (Non compressed mode): 0: SSI_WS is low for the first channel, high for the second channel 1: SSI_WS is high for the first channel, low for the second channel CPEN = 1 (Compressed mode): 0: SSI_WS is active high flow control. WS = high means data should be transferred, low means data should not be transferred. 1: SSI_WS is active low flow control. WS = low means data should be transferred, high means data should not be transferred.
Rev. 1.0, 02/03, page 686 of 1294
Bit 11
Bit Name SPDP
Initial Value 0
R/W R/W
Description Serial Padding Polarity This bit is ignored if CPEN = 1. 0: Padding bits are low 1: Padding bits are high
10
SDTA
0
R/W
Serial Data Alignment This bit is ignored if CPEN = 1. 0: Serial data is transmitted/ received first, followed by padding bits. 1: Padding bits are transmitted/ received first, followed by serial data.
9
PDTA
0
R/W
Parallel Data Alignment This bit is ignored if CPEN = 1. If the data word length = 32, 16 or 8 then this bit has no meaning. This bit is applied to SSIRDR in receive mode and to SSITDR in transmit mode. 0: Parallel data (SSITDR or SSIRDR) is left aligned 1: Parallel data (SSITDR or SSIRDR) is right aligned * DWL = 000 (data word length: 8 bits), PDTA ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus. Four data words are transmitted/received in each 32-bit access. The first data word is stored in bits 7 to 0, the second from bits 15 to 8, the third from bits 23 to 16 and the last data word is stored in bits 31 to 24. * DWL = 001 (data word length: 16 bits), PDTA ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus. Two data words are transmitted/received in each 32-bit access. The first data word is stored in bits 15 to 0 and the second data word is stored in bits 31 to 16.
Rev. 1.0, 02/03, page 687 of 1294
Bit
Bit Name
Initial Value
R/W
Description * DWL = 010, 011, 100, 101 (data word length: 18, 20, 22 and 24 bits), PDTA = 0 (left aligned) The data bits which are used in SSIRDR or SSITDR are the following: Bits 31 to (32 - number of bits having data word length specified by DWL). If DWL = 011 then data word length is 20 bits and bits 31 to 12 are used of either SSIRDR or SSITDR. All other bits are ignored or reserved. * DWL = 010, 011, 100, 101 (data word length: 18, 20, 22 and 24 bits), PDTA = 1 (right aligned) The data bits which are used in SSIRDR or SSITDR are the following: Bits (number of bits having data word length specified by DWL - 1) to 0. If DWL = 011 then data word length is 20 bits and bits 19 to 0 are used of either SSIRDR or SSITDR. All other bits are ignored or reserved. * DWL = 110 (data word length: 32 bits), PDTA ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus.
8
DEL
0
R/W
Serial Data Delay 0: 1 clock cycle delay between SSI_WS and SSI_SDATA 1: No delay between SSI_WS and SSI_SDATA This bit is ignored if CPEN = 1. A one-clock cycle delay is not supported when the SSI module is configured to be a slave transmitter (SWSD = 0 and TRMD = 1). In this situation, this bit should be set to 0.
Rev. 1.0, 02/03, page 688 of 1294
Bit 7
Bit Name BREN
Initial Value 0
R/W R/W
Description Burst Mode Enable 0: Burst mode is disabled. 1: Burst mode is enabled. Burst mode is used in conjunction with compressed mode (CPEN = 1). When burst mode is enabled the SSI_SCK signal is gated. Clock pulses are output only when there is valid serial data being output on SSI_SDATA.
6 to 4
CKDV
All 0
R/W
Serial Oversampling Clock Division Ratio These bits define the division ratio between oversampling Clock (HAC_BIT_CLK) and the serial bit clock. These bits are ignored if SCKD = 0. The Serial Bit Clock is used for the shift register and is provided on the SSI_SCK pin. 000: (Serial bit clock frequency = oversampling clock frequency/1) 001: (Serial bit clock frequency = oversampling clock frequency/2) 010: (Serial bit clock frequency = oversampling clock frequency/4) 011: (Serial bit clock frequency = oversampling clock frequency/8) 100: (Serial bit clock frequency = oversampling clock frequency/16) 101: Setting prohibited 110: Setting prohibited 111: Setting prohibited
3
MUEN
0
R/W
Mute Enable When in transmit mode (TRMD = 1), by making MUEN = 1, the output of SSI_SDATA will be in low level. 0: The SSI module is not muted. 1: The SSI module is muted.
2
CPEN
0
R/W
Compressed Mode Enable 0: Compressed mode disabled 1: Compressed mode enabled
1
TRMD
0
R/W
Transmit/Receive Mode Select 0: The SSI module is in receive mode 1: The SSI module is in transmit mode
0
EN
0
R/W
SSI Module Enable 0: The SSI module is disabled 1: The SSI module is enabled
Rev. 1.0, 02/03, page 689 of 1294
20.3.2
Status Register (SSISR)
SSISR is configured by status flags that indicate the operating status of the SSI module and bits that indicate the current channel number and word number.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28
DMRQ
27
UIRQ
26
OIRQ
25
IIRQ
24
DIRQ
23 R 7 R
22 R 6 R
21 R 5 R
20 R 4 R
19 R 3
CHNO1
18 R 2
CHNO0
17 R 1
SWNO
16 R 0
IDST
0 R 12 R
0 0 R/W* R/W* 11 R 10 R
1 R 9 R
0 R 8 R
0 R
0 R
1 R
1 R
Bit
Bit Name
Initial Value
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. DMA Request Status Flag This status flag allows the CPU to see the status of the DMA request of SSI module. TRMD = 0 (Receive Mode): * * If DMRQ = 1 then SSIRDR has unread data. If SSIRDR is read then DMRQ = 0 until there is new unread data. If DMRQ = 1, SSITDR requests data to be written to continue the transmission onto the audio serial bus. Once data is written to SSITDR then DMRQ = 0 until further transmit data is requested.
31 to 29
28
DMRQ
0
R
TRMD = 1 (Transmit Mode): *
*
Rev. 1.0, 02/03, page 690 of 1294
Bit 27
Bit Name UIRQ
Initial Value 0
R/W R/W*
Description Underflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a lower rate than the required rate. This bit is set to 1 regardless of the setting of UIEN bit. In order to clear it to 0, write 0 in it. If UIRQ = 1 and UIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): If UIRQ = 1, it indicates that SSIRDR was read out before DMRQ and DIRQ bits would indicate the existence of new unread data. In this instance, the same received data may be stored twice by the host, which can lead to destruction of multi-channel data. When TRMD = 1 (Transmit Mode): If UIRQ = 1, it indicates that the transmitted data was not written in SSITDR. By this, the same data may be transmitted one time too often, which can lead to destruction of multi-channel data. Consequently, erroneous SSI data will be output, which makes this error more serious than underflow in the receive mode. Note: When underflow error occurs, the data in the data buffer will be transmitted until the next data is written in.
Rev. 1.0, 02/03, page 691 of 1294
Bit 26
Bit Name OIRQ
Initial Value 0
R/W R/W*
Description Overflow Error Interrupt Status Flag This status flag indicates that the data has been supplied at a higher rate than the required rate. This bit is set to 1 regardless of the setting of OIEN bit. In order to clear it to 0, write 0 in it. If OIRQ = 1 and OIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): If OIRQ = 1, it indicates that the previous unread data had not been read out before new unread data was written in SSIRDR. This may cause the loss of data, which can lead to destruction of multi-channel data. When TRMD = 1 (Transmit Mode): If OIRQ = 1, it indicates that SSITDR had data written in before the data in SSITDR was transferred to the shift register. This may cause the loss of data, which can lead to destruction of multi-channel data. Note: When overflow error occurs, the data in the data buffer will be overwritten by the next data sent from the SSI interface.
25
IIRQ
1
R
Idle Mode Interrupt Status Flag This status flag indicates whether the SSI module is in the idle status. This bit is set to 1 regardless of the setting of IIEN bit, so that polling will be possible. The interrupt can be masked by clearing IIEN bit to 0, but writing 0 in this bit will not clear the interrupt. If IIRQ = 1 and IIEN = 1, then an interrupt will be generated. 0: The SSI module is not in the idle status. 1: The SSI module is in the idle status.
Rev. 1.0, 02/03, page 692 of 1294
Bit 24
Bit Name DIRQ
Initial Value 0
R/W R
Description Data Interrupt Status Flag This status flag indicates that the SSI module requires that data be either read out or written in. This bit is set to 1 regardless of the setting of DIEN bit, so that polling will be possible. The interrupt can be masked by clearing DIEN bit to 0, but writing 0 in this bit will not clear the interrupt. If DIRQ = 1 and DIEN = 1, then an interrupt will be generated. When TRMD = 0 (Receive Mode): 0: No unread data exists in SSIRDR. 1: Unread data exists in SSIRDR. When TRMD = 1 (Transmit Mode): 0: The transmit buffer is full. 1: The transmit buffer is empty, and requires that data be written in SSITDR.
23 to 4
R
Reserved These bits are always read as an undefined value. The write value should always be 0. Channel Number The number indicates the current channel. When TRMD = 0 (Receive Mode): This bit indicates to which channel the current data in SSIRDR belongs. When the data in SSIRDR is updated by transfer from the shift register, this value will change. When TRMD = 1 (Transmit Mode): This bit indicates the data of which channel should be written in SSITDR. When data is copied to the shift register, regardless whether the data is written in SSITDR, this value will change.
3 2
CHNO1 CHNO0
0 0
R R
Rev. 1.0, 02/03, page 693 of 1294
Bit 1
Bit Name SWNO
Initial Value 1
R/W R
Description Serial Word Number The number indicates the current word number. When TRMD = 0 (Receive Mode): This bit indicates which system word the current data in SSIRDR is. Regardless whether the data has been read out from SSIRDR, when the data in SSIRDR is updated by transfer from the shift register, this value will change. When TRMD = 1 (Transmit Mode): This bit indicates which system word should be written in SSITDR. When data is copied to the shift register, regardless whether the data is written in SSITDR, this value will change.
0
IDST
1
R
Idle Mode Status Flag Indicates that the serial bus activity has ceased. This bit is cleared if EN = 1 and the Serial Bus is currently active. This bit can be set to 1 automatically under the following conditions. SSI = Serial bus master transmitter (SWSD = 1 and TRMD = 1): This bit is set to 1 if no more data has been written to SSITDR and the current system word has been completed. It can also be set to 1 by clearing the EN bit after sufficient data has been written to SSITDR to complete the system word currently being output. SSI = Serial bus master receiver (SWSD = 1 and TRMD = 0): This bit is set to 1 if the EN bit is cleared and the current system word is completed. SSI = Slave transmitter/ receiver (SWSD = 0): This bit is set to 1 if the EN bit is cleared and the current system word is completed. Note: If the external device stops the serial bus clock before the current system word is completed then this bit will never be set.
Note: * These bits are readable/writable bits. If writing 0, these bits are initialized, although writing 1 is ignored.
Rev. 1.0, 02/03, page 694 of 1294
20.3.3
Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted. Data written to SSITDR is transferred to the shift register as it is required for transmission. If the data word length is less than 32 bits then its alignment should be as defined by the PDTA control bit. Reading this register will return the data in the buffer.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
20.3.4
Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores the received data. Data in SSIRDR is transferred from the shift register as each data word is received. If the data word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in SSICR.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
Rev. 1.0, 02/03, page 695 of 1294
20.4
20.4.1
Operation
Bus Format
The SSI module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus formats can be one of eight major modes as shown in table 20.3. Table 20.3 Bus Formats of SSI Module
CHNL[1:0] DWL[2:0] SWL[2:0]
SWSD
MUEN
SWSP
TPMD
SCKD
CPEN
Bus Format Non-Compressed Slave Receiver Non-Compressed Slave Transmitter Non-Compressed Master Receiver Non-Compressed Master Transmitter Compressed Slave Receiver Compressed Slave Transmitter Compressed Master Receiver Compressed Master Transmitter
0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1
0 0 1 1 0/1 0/1 0/1 0/1
0 0 1 1 0 0 1 1
Control bits
Configuration bits
Control bits
Ignored
Configuration bits
SCKP
SPDP
PDTA
SDTA
OIEN
DIEN
UIEN
DEL
IIEN
EN
Ignored
20.4.2
Non-Compressed Modes
The non-compressed mode is designed to support all serial audio streams which are split into channels. It can support Philips, Sony and Matsushita modes as well as many more variants on these modes. (1) Slave Receiver This mode allows the SSI module to receive serial data from another device. The clock and word select signals used for the serial data stream are also supplied from an external device. If these signals do not conform to the format as specified in the SSI module then operation is not guaranteed.
Rev. 1.0, 02/03, page 696 of 1294
(2) Slave Transmitter This mode allows the SSI module to transmit serial data to another device. The clock and word select signals used for the serial data stream are also supplied from an external device. If these signals do not conform to the format as specified in the SSI module then operation is not guaranteed. (3) Master Receiver This mode allows the SSI module to receive serial data from another device. The clock and word select signals are internally derived from the HAC_BIT_CLK input clock. The format of these signals is as defined in the SSI module. If the incoming data does not conform to the defined format then operation is not guaranteed. (4) Master Transmitter This mode allows the SSI module to transmit serial data to another device. The clock and word select signals are internally derived from the HAC_BIT_CLK input clock. The format of these signals is as defined in the configuration bits in the SSI module. (5) Configuration Fields - Word Length Related All configuration bits relating to the word length of SSICR are valid in non-compressed modes. There are many configurations that the SSI module can support and it is not sensible to show all of the Serial Data formats in this document. Some of the combinations are shown below for the popular formats by Philips, Sony, and Matsushita. 1. Philips Format
Figures 20.2 and 20.3 show the supported Philips protocol both with padding and without. Padding occurs when the data word length is smaller than the system word length.
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00 System word length = data word length
SSI_SCK
SSI_WS LSB LSB MSB +1 System word 1 = data word 1 LSB LSB next sample +1 System word 2 = data word 2
SSI_SDATA
prev. sample MSB
Figure 20.2 Philips Format (with no Padding)
Rev. 1.0, 02/03, page 697 of 1294
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSI_SCK
SSI_WS
SSI_SDATA
MSB
LSB
MSB
LSB
Next
Data word 1 System word 1
Padding
Data word 2 System word 2
Padding
Figure 20.3 Philips Format (with Padding) Figure 20.4 shows the format used by Sony. Figure 20.5 shows the format used by Matsushita. Padding is assumed in both cases, but may not be present in a final implementation if the system word length equals the data word length. 2. Sony Format
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 0 System word length > data word length
SSI_SCK
SSI_WS
SSI_SDATA
MSB Data word 1
LSB Padding
MSB
LSB
Next Padding
Data word 2 System word 2
System word 1
Figure 20.4 Sony Format (with Serial Data First, Followed by Padding Bits)
Rev. 1.0, 02/03, page 698 of 1294
3.
Matsushita Format
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 00, SPDP = 0, SDTA = 1 System word length > data word length SSI_SCK
SSI_WS
SSI_SDATA
Prev.
MSB
LSB
MSB
LSB
Padding
Data word 1 System word 1
Padding
Data word 2 System word 2
Figure 20.5 Matsushita Format (with Padding Bits First, Followed by Serial Data) (6) Multi-Channel Formats Some devices extend the definition of the specification by Philips and allow more than 2 channels to be transferred within two system words. The SSI module supports the transfer of 4, 6 and 8 channels by the use of the CHNL, SWL and DWL bits. It is important that the system word length (SWL) is greater than or equal to the number of channels (CHNL) times the data word length (DWL). Table 20.4 shows the number of padding bits for each of the valid configurations. If a setup is not valid it does not have a number in the following table and has instead a dash.
Rev. 1.0, 02/03, page 699 of 1294
Table 20.4 Number of Padding Bits for Each Valid Configuration
Padding Bits Per System Word CHNL [1:0] 00 Decoded Channels per System Word 1 SWL [2:0] 000 001 010 011 100 101 110 111 01 2 000 001 010 011 100 101 110 111 10 3 000 001 010 011 100 101 110 111 11 4 000 001 010 011 100 101 110 111 DWL[2:0] Decoded Word Length 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 8 16 24 32 48 64 128 256 000 8 0 8 16 24 40 56 120 248 -- 0 8 16 32 48 112 240 -- -- 0 8 24 40 104 232 -- -- -- 0 16 32 96 224 001 16 -- 0 8 16 32 48 112 240 -- -- -- 0 16 32 96 224 -- -- -- -- 0 16 80 208 -- -- -- -- -- 0 64 192 010 18 -- -- 6 14 30 46 110 238 -- -- -- -- 12 28 92 220 -- -- -- -- -- 10 74 202 -- -- -- -- -- -- 56 184 011 20 -- -- 4 12 28 44 108 236 -- -- -- -- 8 24 88 216 -- -- -- -- -- 4 68 196 -- -- -- -- -- -- 48 176 100 22 -- -- 2 10 26 42 106 234 -- -- -- -- 4 20 84 212 -- -- -- -- -- -- 62 190 -- -- -- -- -- -- 40 168 101 24 -- -- 0 8 24 40 104 232 -- -- -- -- 0 16 80 208 -- -- -- -- -- -- 56 184 -- -- -- -- -- -- 32 160 110 32 -- -- -- 0 16 32 96 224 -- -- -- -- -- 0 64 192 -- -- -- -- -- -- 32 160 -- -- -- -- -- -- 0 128
Rev. 1.0, 02/03, page 700 of 1294
In the case of the SSI module configured as a transmitter then each word that is written to SSITDR is transmitted in order on the serial audio bus. In the case of the SSI module configured as a receiver each word received on the Serial Audio Bus is presented for reading in order by SSIRDR. Figures 20.6 to 20.8 show how 4, 6 and 8 channels are transferred on the serial audio bus. Note that there are no padding bits in the first example, serial data is transmitted/received first and followed by padding bits in the second example, and padding bits are transmitted/received first and followed by serial data in the third example. This selection is purely arbitrary.
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 01, SPDP = don't care, SDTA = don't care System word length = data word length x 2 SSI_SCK SSI_WS SSI_SDATA
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
Data word 1
Data word 2
Data word 3
Data word 4
Data word 1
Data word 2
Data word 3
Data word 4
System word 1
System word 2
System word 1
System word 2
Figure 20.6 Multichannel Format (4 Channels, No Padding)
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 10, SPDP = 1, SDTA = 0 System word length = data word length x 3 SSI_SCK SSI_WS SSI_SDATA
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
Padding
Data word 1
Data word 2 System word 1
Data word 3
Data word 4
Data word 5 System word 2
Data word 6
Figure 20.7 Multichannel Format (6 Channels with High Padding)
Rev. 1.0, 02/03, page 701 of 1294
Padding
SCKP = 0, SWSP = 0, DEL = 0, CHNL = 11, SPDP = 0, SDTA = 1 System word length > data word length x 4
SSI_SCK SSI_WS SSI_SDATA
Padding
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Data word 1
Data word 2
Data word 3
Data word 4
Padding
Data word 5
Data word 6
Data word 7
Data word 8
System word 1
System word 2
Figure 20.8 Multichannel Format (8 Channels, with Padding Bits First, Followed by Serial Data, with Padding) (7) Configuration Fields - Signal Format Fields There are several more configuration bits in non-compressed mode which will now be demonstrated. These bits are NOT mutually exclusive, however some configurations will probably not be useful for any other device. They are demonstrated by referring to the following basic sample format shown in figure 20.9.
SWL = 6 bits (not attainable in SSI module, demonstration only) DWL = 4 bits (not attainable in SSI module, demonstration only) CHNL = 00, SCKP = 0, SWSP = 0, SPDP = 0, SDTA = 0, PDTA = 0, DEL = 0, MUEN = 0 4-bit data samples continuously written to SSITDR are transmitted onto the serial audio bus.
SSI_SCK
SSI_WS
1st channel
2nd channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Key for this and following diagrams: Arrow head indicates sampling point of receiver TDn 0 1 Bit n in SSITDR means a low level on the serial bus (padding or mute) means a high level on the serial bus (padding)
Figure 20.9 Basic Sample Format (Transmit Mode with Example System/Data Word Length)
Rev. 1.0, 02/03, page 702 of 1294
In figure 20.9, system word length of 6 bits and a data word length of 4 bits are used. Neither of these are possible with the SSI module but are used only for clarification of the other configuration bits. 1. Inverted Clock
As basic sample format configuration except SCKP = 1
SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 20.10 Inverted Clock 2. Inverted Word Select
As basic sample format configuration except SWSP = 1
SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31
Figure 20.11 Inverted Word Select 3. Inverted Padding Polarity
As basic sample format configuration except SPDP = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31 TD30 TD29 TD28
1
1
TD31
Figure 20.12 Inverted Padding Polarity
Rev. 1.0, 02/03, page 703 of 1294
4.
Padding Bits First, Followed by Serial Data, with Delay
As basic sample format configuration except SDTA = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
Figure 20.13 Padding Bits First, Followed by Serial Data, with Delay 5. Padding Bits First, Followed by Serial Data, without Delay
As basic sample format configuration except SDTA = 1 and DEL = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
Figure 20.14 Padding Bits First, Followed by Serial Data, without Delay 6. Serial Data First, Followed by Padding Bits, without Delay
As basic sample format configuration except DEL = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30 TD29 TD28
0
0
TD31 TD30
Figure 20.15 Serial Data First, Followed by Padding Bits, without Delay
Rev. 1.0, 02/03, page 704 of 1294
7.
Parallel Right Aligned with Delay
As basic sample format configuration except PDTA = 1 SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
TD2
TD1
TD0
0
0
TD3
Figure 20.16 Parallel Right Aligned with Delay 8. Mute Enabled
As basic sample format configuration except MUEN = 1 (TD data ignored) SSI_SCK
SSI_WS
1st Channel
2nd Channel
SSI_SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20.17 Mute Enabled 20.4.3 Compressed Modes
The compressed mode is used to transfer a continuous bit stream. This would typically be a compressed bit stream which requires downstream decoding. In streaming mode (burst mode not enabled) there is no concept of a data word. However in order to receive and transmit it is necessary to transfer between the serial bus and word formatted memory. Therefore the word boundary selection is arbitrary during receive/transmit and must be dealt with by another module. When burst mode is enabled then data bits being transmitted can be identified by virtue of the fact that the serial clock output is only activated when there is a word to be output and only the required number of clock pulses necessary to clock out each 32-bit word are generated. The serial bit clock stops at a low level when SSICR.SCKP = 0, and at a high level when SSICR.SCKP = 1. Note burst mode is only valid in the context of the SSI module being a transmitter of data. Burst mode data cannot be received by this module. Data is transmitted and received in blocks of 32 bits, and the first bit received/transmitted bit is bit 31 when stored in memory.
Rev. 1.0, 02/03, page 705 of 1294
The word select pin in this mode does not act as a system word start signal as in non-compressed mode, but instead is used to indicate that the receiver can receive another data burst, or the transmitter can transmit another data burst. Figures 20.18 and 20.19 show the compressed mode data transfer, with burst mode disabled, and enabled, respectively.
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 0, SWSP = 0, BREN = 0 SSI_SCK
SSI_WS
SSI_SDATA
MSB Data word 1
LSB MSB Data word 2
LSB Null data
MSB Data word 3
LSB
Figure 20.18 Compressed Data Format, Slave Transmitter, Burst Mode Disabled
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 0, SWSP = 0, BREN = 1 SSI_SCK
SSI_WS MSB Data word 1 LSB MSB Data word 2 LSB Null data MSB Data word 3 LSB
SSI_SDATA
Figure 20.19 Compressed Data Format, Slave Transmitter, and Burst Mode Enabled (1) Slave Receiver This mode allows the module to receive a serial bit stream from another device and store it in memory. The shift register clock can be supplied from an external device or from an internal clock. The word select pin is used as an input flow control. Assuming that SWSP = 0 if SSI_WS is high then the module will receive the bit stream in blocks of 32 bits, one data bit per clock. If SSI_WS goes low then the module will complete the current 32-bit block and then stop any further reception, until SSI_WS goes high again.
Rev. 1.0, 02/03, page 706 of 1294
(2) Slave Transmitter This mode allows the SSI module to transfer a serial bit stream from internal memory to another device. The shift register clock can be supplied from an external device or from an internal clock. The word select pin is used as an input flow control. Assuming that SWSP = 0, if SSI_WS is high then the module will keep transferring the data in the TD buffer to the shift register and transmitting it in blocks of 32 bits, one data bit per clock. If SSI_WS goes low then the module will complete the current 32-bit block and then cease any further transmission, until SSI_WS goes high again. (3) Master Receiver This mode allows the SSI module to receive a serial bit stream from another device and store it in memory. The shift register clock can be supplied from an external device or from an internal clock. The word select pin is used as an output flow control. The module always asserts the word select signal to indicate it can receive more data continuously. It is the responsibility of the host CPU to ensure it can transmit data to the SSI module in time to ensure no data is lost. (4) Master Transmitter This mode allows the module to transmit a serial bit stream from internal memory to another device. The shift register clock can be supplied from an external device or from an internal clock. The word select pin is used as an output flow control. The module always asserts the word select signal to indicate it will transmit more data continuously. Word select signal is not asserted until the first word is ready to transmit however. It is the responsibility of the receiving device to ensure it can receive the serial data in time to ensure no data is lost. When the configuration for data transfer is completed, the SSI module can work with the minimum interaction with CPU. The CPU specifies settings for the SSI module and DMAC then handles overflow/ underflow interrupts if required. 20.4.4 Operation Modes
There are three modes of operation: configuration, enabled and disabled. Figure 20.20 shows the transition diagram between these operation modes.
Rev. 1.0, 02/03, page 707 of 1294
reset Module configration (after reset)
EN = 0 (IDST = 1)
EN = 1 (IDST = 0)
Module disabled (waiting until bus inactive)
Module enabled (normal tx/rx) EN = 0 (IDST = 0)
Figure 20.20 Transition Diagram between Operation Modes (1) Configuration Mode This mode is entered after the module is released from reset. All required settings in the control register should be defined in this mode, before the SSI module is enabled by setting the EN bit. Setting the EN bit causes the SSI module to enter the module enabled mode. (2) Module Enabled Mode Operation of the module in this mode depends on the selected operating mode. For details, see section 20.4.5, Transmit Operation and section 20.4.6, Receive Operation. 20.4.5 Transmit Operation
Transmission can be controlled in one of two ways: either DMA or an interrupt driven. DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or overflow of data or DMAC transfer end is notified by using an interrupt. The alternative is using the interrupts that the SSI module generates to supply data as required. This mode has a higher interrupt load as the SSI module is only double buffered and will require data to be written at least every system word period. When the SSI module has been enabled for transmission, at least one longword must be written to the transmit register before disabling the transmitter (In 16-bit mode, two 16-bit words will be transmitted; in 8-bit mode, 4 bytes will be transmitted. For all other data sizes, one data word will be transmitted, e.g., 18 bits for 18-bit mode.) Failure to do this will result in a lockup, which requires a power-on or manual reset.
Rev. 1.0, 02/03, page 708 of 1294
When disabling the SSI module, the SSI clock* must be supplied continuously until the module enters in the idle state, indicated by the IIRQ bit. Figure 20.21 shows the transmit operation in the DMA controller mode. Figure 20.22 shows the transmit operation in the Interrupt controller mode. Note: * SCKD = 0: Clock input through the SSI_SCK pin SCKD = 1: Clock input through the HAC_BIT_CLK pin (1) Transmission Using DMA Controller
Start Release reset, specify configuration bits in SSICR Setup DMA controller to provide data as required for transmission Enable SSI module, enable DMA, enable error interrupts Wait for interrupt from DMAC or SSI Use SSI status register bits to realign data after underflow/overflow EN = 1, DMEN = 1, UIEN = 1, OIEN = 1 Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
SSI error interrupt? No No Has DMAC Tx data been completed? Yes Yes
Yes
More data to be send? No Disable SSI module, disable DMA disable error interrupt, enable Idle interrupt Wait for idle interrupt from SSI module End EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Figure 20.21 Transmission Using DMA Controller
Rev. 1.0, 02/03, page 709 of 1294
(2) Transmission using Interrupt Data Flow Control
Start Release reset, specify configuration bits in SSICR Enable SSI module, enable data interrupt, enable error interrupts For n = ( (CHNL + 1) x 2) Loop Wait for interrupt from SSI Use SSI status register bits to realign data after underflow/overflow Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
Data interrupt? Yes Load data of channel n
No
Next Channel
Yes
More data to be send? No Disable SSI module, disable data interrupt, disable error interrupt, enable Idle interrupt Wait for Idle interrupt from SSI module End EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Figure 20.22 Transmission using Interrupt Data Flow Control
Rev. 1.0, 02/03, page 710 of 1294
20.4.6
Receive Operation
As with transmission the reception can be controlled in one of two ways: either DMA or an interrupt driven. Figures 20.23 and 20.24 show the flow of operation. When disabling the SSI module, the SSI clock* must be supplied continuously until the module enters in the idle state, which is indicated by the IIRQ bit. Note: * SCKD = 0: Clock input through the SSI_SCK pin SCKD = 1: Clock input through the HAC_BIT_CLK pin
Rev. 1.0, 02/03, page 711 of 1294
(1) Reception Using DMA Controller
Start Release reset, specify configuration bits in SSICR Setup DMA controller to transfer data from SSI module to memory Enable SSI module, enable DMA, enable error interrupts Wait for interrupt from DMAC or SSI Use SSI status register bits to realign data after underflow/overflow EN = 1, DMEN = 1, UIEN = 1, OIEN = 1 Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
SSI Error interrupt? No No Has DMAC Rx data been completed? Yes Yes More data to be received? No Disable SSI module, disable DMA disable error interrupt, enable Idle interrupt Wait for idle interrupt from SSI module End
Yes
EN = 0, DMEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Figure 20.23 Reception using DMA Controller
Rev. 1.0, 02/03, page 712 of 1294
(2) Reception using Interrupt Data Flow Control
Start Specify TRMD, EN, SCKD, SWSD, MUEN, DEL, PDTA, SDTA, SPDP, SWSP, SCKP, SWL, DWL, CHNL
Release reset, specify configuration bits in SSICR
Enable SSI module, enable data interrupt, enable error interrupts
EN = 1, DIEN = 1, UIEN = 1, OIEN = 1
Wait for interrupt from SSI
SSI Error interrupt? No Read data from receive data register
Yes
Use SSI status register bits to realign data after underflow/overflow
Yes
More data to be received? No Disable SSI module, disable data interrupt, disable error interrupt, enable idle interrupt EN = 0, DIEN = 0 UIEN = 0, OIEN = 0, IIEN = 1
Wait for idle interrupt from SSI module
End
Figure 20.24 Reception using Interrupt Data Flow Control
Rev. 1.0, 02/03, page 713 of 1294
When an underflow or overflow error condition is met, the CHNO[1:0] and SWNO bits can be used to recover the SSI module to a known status. When an underflow or overflow occurs, the host CPU can read the number of channels and the number of system words to determine what point the serial audio stream has reached. In the transmitter case, the host CPU can skip forward through the data it wants to transmit until it finds the sample data that matches what the SSI module is expecting to transmit next, and so resynchronize with the audio data stream. In the receiver case, the host CPU can skip forward storing null sample data until it is ready to store the sample data that the SSI module is indicating that it will receive next to ensure consistency of the number of received data, and so resynchronize with the audio data stream. 20.4.7 Serial Clock Control
This function is used to control and select which clock is used for the serial bus interface. If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode, then the bit clock that is used in the shift register is derived from the SSI_SCK pin. If the serial clock direction is set to output (SCKD = 1), the SSI Module is in clock master mode, and the shift register uses the bit clock derived from the HAC_BIT_CLK input pin or its clock divided. This input clock is then divided by the ratio in the serial oversampling clock division ratio (CKDV) bit in SSICR and used as the bit clock in the shift register. In either case, the SSI_SCK pin output is the same as the bit clock.
20.5
20.5.1
Usage Note
Restrictions when an Overflow Occurs during Receive DMA Operation
If an overflow occurs during receive DMA operation, the module must be reactivated. If an overflow occurs, recover the module according to the following procedure. 1. Ensure an overflow occurs through an overflow error interrupt or overflow error status flag (the OIRQ bit in SSISR). 2. Terminate the DMA by writing 1 to the RDS bit in DMAACR. At this time, confirm the DMA is terminated by reading in the RDS bit (0 can be read). 3. Disable the DMA in the SSI module to halt its operation by writing 0 to the EN bit and DMEN bit in SSICR. 4. Confirm the remaining number of the DMA by reading the DMAARXTCNT to reset the start address of the DMA and number of transfers (MDAARXDAR/DMAARXTCR). 5. Clear the overflow status flag by writing 0 to the OIRQ bit. 6. Reactivate the DMAC by writing 1 to the RDE bit in DMAACR. 7. Reactivate the module by enabling the SSI module and DMA again.
Rev. 1.0, 02/03, page 714 of 1294
Section 21 USB Host Module (USB)
The USB Host Controller module supports Open Host Controller Interface (Open HCI) Specification for the Universal Serial Bus (USB) as well as the Universal Serial Bus specification ver.1.1. The Open HCI Specification for the USB is a register-level description of Host Controller for the USB. It is necessary to refer Open HCI specification to develop drivers for this USB Host Controller and hardware. Abbreviations used in this section are shown below. HC: host controller HCD: host controller driver
21.1
Features
The USB host module has the following features. * Supports the register set compliant with the Open Host Controller Interface (Open HCI) Specification Release 1.0* * Compatible with the Universal Serial Bus Ver.1.1 Specifications. * Supports full speed (12 Mbps) mode and low speed (1.5 Mbps) mode as USB transfer speeds * Supports four transfer modes (control transfer, bulk transfer, interrupt transfer, and isochronous transfer) * Supports the overcurrent detection circuit * Supports 127 endpoints at the maximum * One USB port * On-chip 8-kbyte SRAM used as shared memory which is defined in the OpenHCI specification Note: * Part of registers is not supported. For details, see section 21.3, Register Descriptions and section 21.6, Restrictions on HcRhDescriptorA.
Rev. 1.0, 02/03, page 715 of 1294
Figure 21.1 shows a block diagram of the USB host module.
USB interrupt USB control registers HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 UCLK
USB bridge bus
Host controller (HC)
USB_PENC USB_OVC
Bus interface
USB_DP USB_DM
USB bus transceiver/reciever Shared memory (8 kbytes)
Legend: HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED
: Host controller interface revision register : Control register : Command status register : Interrupt status register : Interrupt enable register : Interrupt disable register : Host controller communication area pointer register : Period current ED pointer register : Control head ED pointer register : Control current ED pointer register : Bulk head ED pointer register
HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1
: Bulk current ED pointer register : Done queue head pointer register : Frame interval register : Frame remaining register : Frame number register : Periodic start register : Low speed threshold register : Root hub descriptor A register : Root hub descriptor B register : Root hub status register : Root hub port status 1 register
Figure 21.1 Block Diagram of USB Host Module
Rev. 1.0, 02/03, page 716 of 1294
21.2
Input/Output Pins
Table 21.1 shows the pin configuration of the USB host module. Table 21.1 Pin Configuration
Pin Name D+ D- Power enable Overcurrent UCLK Abbreviation USB_DP USB_DM USB_PENC USB_OVC UCLK I/O Function
Input/Output Root hub port D+ transceiver pin Input/Output Root hub port D- transceiver pin Output Input Input Power-on enable control pin for root hub port Overcurrent detection pin for root hub port USB operating clock (input clock of 48.0000 MHz 0.05%)
21.3
Register Descriptions
The USB host module has the following registers. These registers can be accessed only in longwords. Access in bytes or words is prohibited. For details on register addresses and register states during each process, see section 32, List of Registers. When a clock is not input from the UCLK pin, these registers cannot be accessed.
Rev. 1.0, 02/03, page 717 of 1294
Table 21.2 Register Configuration (1)
Register Name Host controller interface revision register Control register Command status register Interrupt status register Interrupt enable register Interrupt disable register Abbreviation HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R R R/W R/W R/W R/W R/W R/W R/W R/W P4 Address H'FE34 0000 H'FE34 0004 H'FE34 0008 Area 7 Address H'1E34 0000 H'1E34 0004 H'1E34 0008 Sync Size Clock 32 32 32 Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
H'FE34 000C H'1E34 000C 32 H'FE34 0010 H'FE34 0014 H'FE34 0018 H'1E34 0010 H'1E34 0014 H'1E34 0018 32 32 32
Host controller communication area HcHCCA pointer register Period current ED pointer register Control head ED pointer register HcPeriodCurrentED HcControlHeadED
H'FE34 001C H'1E34 001C 32 H'FE34 0020 H'FE34 0024 H'FE34 0028 H'1E34 0020 H'1E34 0024 H'1E34 0028 32 32 32
Control current ED pointer register HcControlCurrentED Bulk head ED pointer register Bulk current ED pointer register Done queue head pointer register Frame interval register Frame remaining register Frame number register Periodic start register Low speed threshold register Root hub descriptor A register Root hub descriptor B register Root hub status register Root hub port status 1 register HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 Shared memory start Shared memory end
H'FE34 002C H'1E34 002C 32 H'FE34 0030 H'FE34 0034 H'FE34 0038 H'1E34 0030 H'1E34 0034 H'1E34 0038 32 32 32
H'FE34 003C H'1E34 003C 32 H'FE34 0040 H'FE34 0044 H'FE34 0048 H'1E34 0040 H'1E34 0044 H'1E34 0048 32 32 32
H'FE34 004C H'1E34 004C 32 H'FE34 0050 H'FE34 0054 H'FE34 1000 H'1E34 0050 H'1E34 0054 H'1E34 1000 32 32 32
H'FE34 2FFF H'1E34 2FFF 32
Rev. 1.0, 02/03, page 718 of 1294
Table 21.2 Register Configuration (2)
Manual Reset by RESET Power-on Reset by RESET Register Name Abbrev. Pin/WDT/H-UDI H'0000 0010 Pin/WDT/ Multiple Exception H'0000 0010 Sleep by Sleep Instruction/ by Deep Sleep Hardware Retained * Standby by Software /Each Module Retained
Host controller interface revision HcRevision register Control register Command status register Interrupt status register Interrupt enable register Interrupt disable register Host controller communication area pointer register Period current ED pointer register HcPeriodCurrentED Control head ED pointer register HcControlHeadED Control current ED pointer register Bulk head ED pointer register Bulk current ED pointer register HcBulkHeadED HcBulkCurrentED HcControlCurrentED HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA
H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained
H'0000 0000 H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained
Retained Retained Retained
H'0000 0000 H'0000 0000 H'0000 0000 H'0000 2EDF H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0628 H'0200 1202 H'0000 0000 H'0000 0000 H'0000 0100 Undefined Undefined
H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Done queue head pointer register HcDoneHead Frame interval register Frame remaining register Frame number register Periodic start register Low speed threshold register Root hub descriptor A register Root hub descriptor B register Root hub status register Root hub port status 1 register HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 Shared memory start Shared memory end
H'0000 2EDF Retained H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0628 H'0200 1202 H'0000 0000 H'0000 0000 H'0000 0100 Undefined Undefined Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin.
Rev. 1.0, 02/03, page 719 of 1294
21.3.1
Host Controller Interface Revision Register (HcRevision)
HcRevision stores the version number of the host controller interface specifications.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 0 R 0 R 0 R 1 R 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 REV 0 R 0 R 0 R 0 R 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to these bits.
7 to 0
REV
H10
R
OpenHCI Revision H10: Indicates the OpenHCI specification version 1.0.
21.3.2
Control Register (HcControl)
HcControl defines the operation mode for HC. The bits of this register, except for HCFS and RWC, are modified only by HCD.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10
RWE
25 0 R 9
RWC
24 0 R 8
IR
23 0 R 7
22 0 R 6
21 0 R 5
BLE
20 0 R 4
CLE
19 0 R 3
IE
18 0 R 2
PLE
17 0 R 1
16 0 R 0
HCFS1 HCFS0
CBSR1 CBSR0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.0, 02/03, page 720 of 1294
Bits 31 to 11 10
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to these bits.
RWE
0
R/W
Remote Wakeup Enable This bit is used by HCD to enable/disable the remote wakeup function simultaneously with the detection of an upstream resume signal. 0: Remote wakeup function is not supported 1: Remote wakeup function is supported This function is not supported. Always write 0 to this bit.
9
RWC
0
R/W
Remote Wakeup Connected This bit indicates whether or not HC supports a remote wakeup signal. When the remote wakeup is supported and used in the system, HC must set this bit during POST in the system firmware. HC clears the bit simultaneously with the hardware reset, but not with the software reset. 0: Remote wakeup signal is not supported 1: Remote wakeup signal is supported This function is not supported. Always write 0 to this bit.
8
IR
0
R/W
Interrupt Routing This bit determines the routing of interrupts generated by the event registered in HcInterruptStatus. HCD clears this bit to 0 simultaneously with the hardware reset, but not with the software reset. HCD uses this bit as a tag to indicate the ownership of the host controller. 0: All interrupts are routed to normal bus interrupt mechanism 1: Setting prohibited
Rev. 1.0, 02/03, page 721 of 1294
Bits 7 6
Bit Name HCFS1 HCFS0
Initial Value 0 0
R/W R/W R/W
Description Host Controller Functional State HCD determines whether HC has started to route SOF after having read the SF bit of HcInterruptStatus. This bit can be changed by HC only in the USB suspend state. HC can change from the USB suspend state to the USB resume state after having detected the resume signal from the downstream port. In HC, USB suspend is entered after the software reset like USB reset is entered after the hardware reset. The former resets the root hub. 00: USB reset state 01: USB resume state 10: USB operation state 11: USB suspend state
5
BLE
0
R/W
Bulk List Enable This bit is set to enable the processing of the bulk list in the next frame. HC checks this bit when the processing of the list has been determined. When this bit is 0 (disabling), HCD can modify the list. When HcBulkCurrentED indicates ED to be deleted, HCD should increment the pointer by updating HcBulkCurrentED before re-enabling the list processing. 0: Bulk list processing is disabled in the next frame 1: Bulk list processing is enabled in the next frame
4
CLE
0
R/W
Control List Enable This bit is set to 1 to enable processing of the control list in the next frame. When cleared to 0 by HCD, the control list is not processed after the next SOF. HC must check this bit whenever the list is to be processed. When this bit is 0 (disabling), HCD can modify the list. When HcControlCurrentED indicates ED to be deleted, HCD should increment the pointer by updating HcControlCurrentED before re-enabling list processing. 0: Control list processing is disabled in the next frame 1: Control list processing is enabled in the next frame
Rev. 1.0, 02/03, page 722 of 1294
Bits 3
Bit Name IE
Initial Value 0
R/W R/W
Description Isochronous Enable This bit is used by HCD to enable/disable the processing of isochronous ED. While processing the periodic list, HC will check the status of this bit when it finds an isochronous ED (F =1). When this bit is 1 (enabling), HC continues to process ED. When this bit is 0 (disabling), HC stops the processing of the periodic list (currently including only isochronous ED) and starts to process the bulk/control list. Setting this bit is guaranteed to be valid in the next frame (not in the current frame). 0: Isochronous list processing is disabled in the next frame 1: Isochronous list processing is enabled in the next frame
2
PLE
0
R/W
Periodic List Enable This bit is set to 1 to enable processing of the periodic list. When HCD clears it to 0, no periodic list processing is carried out after next SOF. HC must check this bit before HC starts to process the list. 0: Periodic list processing is disabled in the next frame 1: Periodic list processing is enabled in the next frame
1 0
CBSR1 CBSR0
0 0
R/W R/W
Control Bulk Service Ratio This specifies the service ratio between Control and Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD must restore this value. 00: The ratio of Control ED to Bulk ED is 1:1 01: The ratio of Control ED to Bulk ED is 2:1 10: The ratio of Control ED to Bulk ED is 3:1 11: The ratio of Control ED to Bulk ED is 4:1
Rev. 1.0, 02/03, page 723 of 1294
21.3.3
Command Status Register (HcCommandStatus)
HcCommandStatus indicates the current status of HC. HC reads this register to receive a command issued by HCD. HCD sets each bit by writing 1 and HC clears it by writing 0.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 OCR 0 R/W 18 0 R 2 BLF 0 R/W 17 16
SOC1 SOC0 0 R 1 CLF 0 R/W 0 R 0 HCR 0 R/W
Bits 31 to 18 17 16
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to these bits.
SOC1 SOC0
0 0
R R
Scheduling Overrun Count These bits are incremented in each SchedulingOverrun error. These bits are initialized to B00 and wrap around at B'11. These bits are incremented when scheduling overrun is detected even though the SO bit in HcInterruptStatus is set. These bits are used by HCD to monitor any persistent scheduling problem. Reserved These bits are always read as 0. Always write 0 to these bits.
15 to 4
All 0
R
3
OCR
0
R/W
Ownership Change Request This bit is set to 1 by OS HCD to request a change of control of HC. When this bit is1, HC sets the OC bit in the HcInterruptStatus. After a change, this bit is cleared to 0 and remains 0 until the next request from OS HCD. 0: Do not request the change of the control of HC 1: Request the change of the control of HC
Rev. 1.0, 02/03, page 724 of 1294
Bits 2
Bit Name BLF
Initial Value 0
R/W R/W
Description Bulk List Filled This bit is used to indicate whether there are any TDs in the list. HCD sets this bit to 1 for the list when adding TD to ED. When starting to process the head of the list, HC checks BF. As long as BLF is 0, HC does not start to process the list. When BLF is 1, HC starts to process the list to set BF through 0. When HC finds TD in the list, HC sets BLF to 1. When TD is not in the list and HCD does not set BLF, HC completes processing the list. When list processing is stopped, BLF remains 0. 0: TD is not found in the Bulk list 1: TD is found in the Bulk list
1
CLF
0
R/W
Control List Filled This bit is used to indicate whether there are any TDs in the control list. HCD sets this bit when adding TD to ED in the control list. When HC starts to process the head of the control list, it checks CLF. As long as CLF is 0, HC does not start to process the control list. When CF is 1, HC starts to process the control list and clears CLF to 0. When HC finds TD in the list, HC sets CLF to 1. When TD is not found in the control list and HCD does not set CLF, HC completes the processing of the control list. When control list processing is stopped, CLF remains 0. 0: TD is not found in the Control list 1: TD is found in the Control list
Rev. 1.0, 02/03, page 725 of 1294
Bits 0
Bit Name HCR
Initial Value 0
R/W R/W
Description Host Controller Reset HCD sets this bit to 1 to start software reset of HC. The HC changes to the USB suspend state in which most operational registers are reset, regardless of which functional state the HC is in. However, access to the InterrupRouting field in HcControl or access without host bus is allowed. HC clears this bit to 0 upon completion of the reset operation. The reset operation must be completed within 10s. Setting this bit to 1 does not either reset the root hub or issue the subsequent reset signal to the downstream port. 0: Software reset of HC is cancelled 1: Software reset of HC is started
21.3.4
Interrupt Status Register (HcInterruptStatus)
HcInterruptStatus indicates the status of various events that cause hardware interrupts. To generate an interrupt, HC sets the corresponding bit in this register to 1 when HcInterruptEnable enables a hardware interrupt with HcInterruptEnable.MIE = 1. HCD can clear a bit to 0 by writing 1 to release the interrupt status. However, HCD cannot set any of these bits to 1.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 OC 0 R/W 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 UE 0 R/W 19 0 R 3 RD 0 R/W 18 0 R 2 SF 0 R/W 17 0 R 1 WDH 0 R/W 16 0 R 0 SO 0 R/W
RHSC FNO 0 R/W 0 R/W
Rev. 1.0, 02/03, page 726 of 1294
Bits 31
Bit Name
Initial Value 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to these bits.
30
OC
0
R/W
Ownership Change HC sets this bit to 1 when HCD sets the OCR bit in the HcCommandStatus register. This event generates a system management interrupt (SMI) at once when not masked. When there is no SMI pin, this bit is set to 0. 0: No change requested 1: There is an HC change request
29 to 7
All 0
R
Reserved These bits are always read as 0. Always write 0 to these bits.
6
RHSC
0
R/W
Root Hub Status Change HC sets this bit to 1 when the contents of either HcRhStatus or any HcRhPortStatus1 have changed. 0: HcRhStatus or HcRhPortStatus contents are not changed 1: HcRhStatus or HcRhPortStatus contents are changed
5
FNO
0
R/W
Frame Number Overflow HC sets this bit to 1 after MSB bit in HcFmNumber changes from 0 to 1 or from 1 to 0 and the HccaFrameNumber is updated. 0: No change 1: MSB in HcFmNumber register is changed and HccaFrameNumber is updated
4
UE
0
R/W
Unrecoverable Error HC sets this bit to 1 when detecting a system error irrelevant to USB. HCD clears this bit after HC is reset. 0: Detected no system error irrelevant to USB 1: Detected a system error irrelevant to USB
Rev. 1.0, 02/03, page 727 of 1294
Bits 3
Bit Name RD
Initial Value 0
R/W R/W
Description Resume Detected HC sets this bit to 1 when detecting the transmission of a resume signal by a USB device. This bit is not set when HCD sets USB resume state. 0: A USB device is not asserting a resume signal 1: A USB device is asserting a resume signal
2
SF
0
R/W
Start of Frame HC sets this bit to 1 when each frame is started and after the HccaFrameNumber is updated. HC simultaneously generates the SOF token. 0: Frame is not started or HccaFrameNumber is not updated 1: Frame is started and HccaFrameNumber is updated
1
WDH
0
R/W
Writeback Done Head HC sets this bit to 1 immediately after writing HcDoneHead to HccaDoneHead. HccaDoneHead is not updated until this bit is cleared. HCD should clear this bit only after the content of HccaDoneHead has been stored. 0: HccaDoneHead is retained 1: The value in HcDoneHead is written to HccaDonehead
0
SO
0
R/W
Scheduling Overrun HC sets this bit to 1 when the USB schedule has overrun in the current frame after HccaFrameNumber is updated. Scheduling overrun also increments the SOC bit in HcCommandStatus. 0: The USB schedule has not overrun in the current frame 1: The USB schedule has overrun in the current frame
21.3.5
Interrupt Enable Register (HcInterruptEnable)
Each enable bit in HcInterruptEnable corresponds to the related hardware interrupt bit in HcInterruptStatus. A hardware interrupt is generated when bits in HcInterruptStatus are set to1, the corresponding bits in HcInterruptEnable are set to 1, and HcInterruptEnable.MIE = 1. Writing 1 to a bit in this register sets the corresponding bit to 1, while writing 0 does not clear the bit to 0 but leaves it unchanged. Reading this register will return the current value of this register.
Rev. 1.0, 02/03, page 728 of 1294
Bit: Initial value: R/W: Bit: Initial value: R/W:
31 MIE 0 R/W 15 0 R
30 OC 0 R/W 14 0 R
29 0 R 13 0 R
28 0 R 12 0 R
27 0 R 11 0 R
26 0 R 10 0 R
25 0 R 9 0 R
24 0 R 8 0 R
23 0 R 7 0 R
22 0 R 6
21 0 R 5
20 0 R 4 UE 0 R/W
19 0 R 3 RD 0 R/W
18 0 R 2 SF 0 R/W
17 0 R 1 WDH 0 R/W
16 0 R 0 SO 0 R/W
RHSC FNO 0 R/W 0 R/W
Bits 31
Bit Name MIE
Initial Value 0
R/W R/W
Description Master Interrupt Enable Setting this bit to 1 will enable an interrupt generation by the event specified in another bit in this register. HCD uses this bit to enable the master interrupt. To use HCD for interrupt detection, use the USB bit of the INTC. 0: Operation is not affected 1: Interrupt generation is enabled
30
OC
0
R/W
Ownership Change 0: Operation is not affected 1: Interrupt generation to change HC control is enabled
29 to 7
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
6
RHSC
0
R/W
Root Hub Status Change 0: Operation is not affected 1: Interrupt generation due to Root Hub Status Change is enabled
5
FNO
0
R/W
Frame Number Overflow 0: Operation is not affected 1: Interrupt generation due to Frame Number Overflow is enabled
4
UE
0
R/W
Unrecoverable Error 0: Operation is not affected 1: Interrupt generation due to unrecoverable error is enabled
Rev. 1.0, 02/03, page 729 of 1294
Bits 3
Bit Name RD
Initial Value 0
R/W R/W
Description Resume Detected 0: Operation is not affected 1: Interrupt generation due to Resume Detected is enabled
2
SF
0
R/W
Start of Frame 0: Operation is not affected 1: Interrupt generation due to Start of Frame is enabled
1
WDH
0
R/W
Writeback Done Head 0: Operation is not affected 1: Interrupt generation for HcDoneHead Writeback is enabled
0
SO
0
R/W
Scheduling Overrun 0: Operation is not affected 1: Interrupt generation due to Scheduling Overrun is enabled
21.3.6
Interrupt Disable Register (HcInterruptDisable)
Each disable bit in the HcInterruptDisable corresponds to the related interrupt bit in HcInterruptStatus. Writing 1 to a bit in the HcInterruptDisable clears the corresponding bit in HcInterruptEnable to 0. Writing 0 to a bit leaves the corresponding bit in HcInterruptEnable unchanged. Reading this register will return the current value of HcInterruptEnable.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 MIE 0 R/W 15 0 R 30 OC 0 R/W 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 21 0 R 5 20 0 R 4 UE 0 R/W 19 0 R 3 RD 0 R/W 18 0 R 2 SF 0 R/W 17 0 R 1 WDH 0 R/W 16 0 R 0 SO 0 R/W
RHSC FNO 0 R/W 0 R/W
Rev. 1.0, 02/03, page 730 of 1294
Bits 31
Bit Name MIE
Initial Value 0
R/W R/W
Description Master Interrupt Enable 0: Operation is not affected 1: Interrupt generation for other events is disabled
30
OC
0
R/W
Ownership Change 0: Operation is not affected 1: Interrupt generation for HC control change is disabled
29 to 7
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
6
RHSC
0
R/W
Root Hub Status Change 0: Operation is not affected 1: Interrupt generation due to Root Hub Status Change is disabled
5
FNO
0
R/W
Frame Number Overflow 0: Operation is not affected 1: Interrupt generation due to Frame Number Overflow is disabled
4
UE
0
R/W
Unrecoverable Error 0: Operation is not affected 1: Interrupt generation due to unrecoverable error is disabled
3
RD
0
R/W
Resume Detected 0: Operation is not affected 1: Interrupt generation due to Resume Detected is disabled
2
SF
0
R/W
Start of Frame 0: Operation is not affected 1: Interrupt generation due to Start of Frame is disabled
1
WDH
0
R/W
Writeback Done Head 0: Operation is not affected 1: Interrupt generation due to HcDonehead Writeback is disabled
0
SO
0
R/W
Scheduling Overrun 0: Operation is not affected 1: Interrupt generation due to Scheduling Overrun is disabled
Rev. 1.0, 02/03, page 731 of 1294
21.3.7
Host Controller Communication Area Pointer Register (HcHCCA)
HcHCCA stores physical addresses of the host controller communication area (HCCA). HCD determines the alignment restrictions by writing 1 to all bits in HcHCCA and by reading the contents of HcHCCA. Alignment is evaluated by checking the number of 0s in the low-order bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must always return 0 when they are read. This area is used to retain the control structures and interrupt table that are accessed by HC and HCD.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCCA 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 0 R/W 0 R/W 0 R 0 R/W 6 0 R 0 R/W 5 0 R 0 R/W 4 0 R 0 R/W 3 0 R 0 R/W 2 0 R 0 R/W 1 0 R 0 R/W 0 0 R
HCCA 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bits 31 to 8 7 to 0
Bit Name HCCA
Initial Value All 0 All 0
R/W R/W R
Description Host Controller Communication Area Address These bits store the base address of HCCA. Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.8
Period Current ED Pointer Register (HcPeriodCurrentED)
HcPeriodCurrentED stores the address of the isochronous ED or interrupt ED to be processed in the current frame.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCED 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 PCED 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 R 2 0 R 0 R 1 0 R 0 R 0 0 R
Rev. 1.0, 02/03, page 732 of 1294
Bit 31 to 4 3 to 0
Bit Name PCED
Initial Value All 0
R/W R
Description Period Current ED Address These bits store the start address of the periodic list processed in the current frame.
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.9
Control Head ED Pointer Register (HcControlHeadED)
HcControlHeadED stores the address of the first ED to be processed in the control list.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHED 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 CHED 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R 0 R/W 2 0 R 0 R/W 1 0 R 0 R/W 0 0 R
Bit 31 to 4 3 to 0
Bit Name CHED
Initial Value All 0 All 0
R/W R/W R
Description Control Head ED Address These bits store the start address of the control list. Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.10 Control Current ED Pointer Register (HcControlCurrentED) HcControlCurrentED stores the address of the ED to be processed in the current frame in the control list.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCED 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 CCED 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R 0 R/W 2 0 R 0 R/W 1 0 R 0 R/W 0 0 R
Rev. 1.0, 02/03, page 733 of 1294
Bit 31 to 4
Bit Name CCED
Initial Value All 0
R/W R/W
Description Control Current ED Address These bits store the start address of the control list to be processed in the current frame.
3 to 0
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.11 Bulk Head ED Pointer Register (HcBulkHeadED) HcBulkHeadED stores the address of the first ED to be processed in the bulk list.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BHED 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 BHED 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R 0 R/W 2 0 R 0 R/W 1 0 R 0 R/W 0 0 R
Bit 31 to 4 3 to 0
Bit Name BHED
Initial Value All 0 All 0
R/W R/W R
Description Bulk Head ED Address These bits store the start address of the bulk list. Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.12 Bulk Current ED Pointer Register (HcBulkCurrentED) HcBulkCurrentED stores the address of the ED to be processed in the current frame in the bulk list.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCED 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 BCED 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R 0 R/W 2 0 R 0 R/W 1 0 R 0 R/W 0 0 R
Rev. 1.0, 02/03, page 734 of 1294
Bit 31 to 4
Bit Name BCED
Initial Value All 0
R/W R/W
Description Bulk Current ED Address These bits store the start address of the bulk list to be processed in the current frame.
3 to 0
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
21.3.13 Done Queue Head Pointer Register (HcDoneHead) HcDoneHead stores the address of the last processed TD in the done queue.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 DH 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 DH 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 R 2 0 R 0 R 1 0 R 0 R 0 0 R 23 22 21 20 19 18 17 16
Bit 31 to 4
Bit Name DH
Initial Value All 0
R/W R
Description Done Queue Pointer Address These bits store the address of the last processed TD.
3 to 0
All 0
R
Reserved These bits are always read as 0.
Rev. 1.0, 02/03, page 735 of 1294
21.3.14 Frame Interval Register (HcFmInterval) HcFmInterval consists of a 14-bit FI value that indicates the frame bit time interval (interval between two consecutive SOFs) and a 15-bit FSMPS value that indicates the maximum packet size that is transmitted and received at full speed by HC without causing scheduling overrun. HCD minutely adjusts the frame interval by updating the value in each SOF.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 FIT 0 R/W 15 0 R 0 R/W 14 0 R 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSMPS 0 R/W 8 0 R/W 7 FI 1 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Bit 31
Bit Name FIT
Initial Value 0
R/W R/W
Description Frame Interval Toggle This bit is toggled by HCD whenever it loads a new value into FI.
30 to 16
FSMPS
All 0
R/W
Largest Data Packet This bit specifies a value to be loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the maximum amount of data in bits transmittable/receivable by HC in a single transaction at any given time without causing scheduling overrun. The bit value is calculated by HCD.
15, 14
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
13 to 0
FI
H'2EDF
R/W
Frame Interval This bit specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11999. HCD should store the current value of this bit before resetting HC. Setting the HCR bit in HcCommandStatus will have the HC reset this bit to its nominal value. HCD may choose to restore the stored value upon the completion of the reset sequence.
Rev. 1.0, 02/03, page 736 of 1294
21.3.15 Frame Remaining Register (HcFmRemaining) HcFmRemaining contains a 14-bit down-counter that indicates bit times remaining until the current frame is complete. HcFmRemaining is a read-only register. Operation is not guaranteed when writing.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 FRT 0 R 15 0 R 30 0 R 14 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 29 0 R 13 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 FR 0 R 0 R 0 R 0 R 0 R 0 R 0 R 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31
Bit Name FRT
Initial Value 0
R/W R
Description Frame Remaining Toggle When FR reaches H0000, this bit stores the FIT value in HcFmInterval. This bit is used by HCD for the synchronization between the FI and FR bits.
30 to 14 13 to 0
FR
All 0 All 0
R R
Reserved These bits are always read as 0. Frame Bit Times Remaining This counter is decremented at each bit time. When it reaches zero, it is re-set to the FI value in HcFmInterval that is loaded at the next bit time boundary. When entering the USB operational state, HC re-loads the contents of the FI bit in HcFmInterval to this counter and uses the updated value from the next SOF.
21.3.16 Frame Number Register (HcFmNumber) HcFmNumber contains a 16-bit counter. This register is referenced for the timing between events occurring in HC and HCD. HCD uses 16-bit value specified in this register and generates a 32-bit frame number without requiring frequent access to the register. HcFmNumber is a read-only register. Operation is not guaranteed when writing.
Rev. 1.0, 02/03, page 737 of 1294
Bit: Initial value: R/W: Bit: Initial value: R/W:
31 0 R 15
30 0 R 14
29 0 R 13
28 0 R 12
27 0 R 11
26 0 R 10
25 0 R 9
24 0 R 8
23 0 R 7 FN
22 0 R 6
21 0 R 5
20 0 R 4
19 0 R 3
18 0 R 2
17 0 R 1
16 0 R 0
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 31 to 16 15 to 0
Bit Name FN
Initial Value All 0 All 0
R/W R R
Description Reserved These bits are always read as 0. Frame Number This is incremented when HcFmRemaining is reloaded. It will be rolled over to H0 after HFFFF. When HC enters the USB operational state, this will be automatically incremented. HC increments the FN at each frame boundary and sends a SOF. Then HC writes the FN contents to HCCA before reading the first ED in that Frame. After writing to HCCA, the HC sets HcInterruptStatus.SF = 1.
21.3.17 Periodic Start Register (HcPeriodicStart) HcPeriodicStart indicates the earliest time when HC should start to process the periodic list.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 29 0 R 13 28 0 R 12 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 PS 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Rev. 1.0, 02/03, page 738 of 1294
Bit 31 to 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to this bit.
13 to 0
PS
All 0
R/W
Periodic Start After a hardware reset, this bit is cleared. Then, HCD sets this bit to 1 during the HC initialization. The value is calculated roughly as 10% subtracted from the HcFmInterval value. When HcFmRemaining reaches the specified value, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress.
21.3.18 Low Speed Threshold Register (HcLSThreshold) HcLSThreshold stores an 11-bit LST value that is used by HC to determine whether or not to authorize the transfer of the LS packet of up to 8 bytes, before EOF. HC and HCD cannot change this value.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 0 R/W 1 R/W 1 R/W 0 R/W 27 0 R 11 26 0 R 10 25 0 R 9 24 0 R 8 23 0 R 7 LST 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
Bit 31 to 12
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. Always write 0 to this bit.
11 to 0
LST
H'628
R/W
LS Threshold This field contains a value which is compared to the FR bit prior to initiating a Low Speed transaction. The transaction is started only if the value of the FR bit is equivalent to or larger than that of this bit. HCD calculates the value of this bit taking transmission and setup overhead into consideration.
Rev. 1.0, 02/03, page 739 of 1294
21.3.19 Root Hub Descriptor A Register (HcRhDescriptorA) HcRhDescriptorA is the first register of two describing the characteristics of the root hub. The descriptor length (11), descriptor type (TBD), and hub controller current (0) bits in the hub Class Descriptor are emulated by HCD. All other bits are allocated in HcRhDescriptorA and HcRhDescriptorB.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 0 R/W 10 DT 0 R 1 R/W 9 NPS 1 R/W 0 R/W 8 PSM 0 R/W 0 R 0 R 0 R 0 R 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 NDP 0 R 0 R 1 R 0 R 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
POTPGT 0 R/W 15 0 R 0 R/W 14 0 R 0 R/W 13 0 R 0 R/W 12 0 R/W 11
NOCP OCPM 1 R/W 0 R/W
Bit 31 to 24
Bit Name POTPGT
Initial Value H'02
R/W R/W
Description Power On To Power Good Time This bit specifies the HCD wait time before accessing a powered-on port of the root hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT x 2 ms.
23 to 13
All 0
R
Reserved These bits are always read as 0. Always write 0 to this bit.
12
NOCP
1
R/W
No Overcurrent Protection This bit describes the overcurrent condition reporting method for root hub ports. When this bit is cleared to 0, the OCPM bit specifies either global or per-port reporting. 0: Overcurrent status info is collected 1: Overcurrent protection is not supported Note: There are restrictions on this bit. For details, see section 21.6, Restrictions on HcRhDescriptorA.
Rev. 1.0, 02/03, page 740 of 1294
Bit 11
Bit Name OCPM
Initial Value 0
R/W R/W
Description Overcurrent Protection Mode This bit specifies the overcurrent condition reporting method for root hub ports. At reset, this bit should reflect the same mode as in PSM. This bit is valid only when the NOCP bit is cleared to 0. 0: Overcurrent status info is collected for all ports 1: Overcurrent status info is collected for ports individually Note: There are restrictions on this bit. For details, see section 21.6, Restrictions on HcRhDescriptorA.
10
DT
1
R
Device Type This bit specifies that the root hub is not a compound device. Always write 0 to this bit. 0: Root hub is not a compound device 1: Setting prohibited
9
NPS
1
R/W
No Power Switching This bit selects whether ports are power switched or ports are always powered. It is implementation specific. When this bit is cleared to 0, the PSM bit specifies global or per-port switching. 0: Ports are power switched 1: Ports are always powered on when HC is powered on Note: Since the initial value is 1, this bit should be cleared to 0 in advance (0 is written by HCD) to enable power switching.
Rev. 1.0, 02/03, page 741 of 1294
Bit 8
Bit Name PSM
Initial Value 0
R/W R/W
Description Power Switching Mode This bit specifies the root hub port power switching control method. It is implementation specific. This bit is valid only when the NPS bit is cleared to 0. 0: All ports are powered at the same time. 1: Each port is powered individually. This mode allows port power to be controlled by either the global switch or per-port switching. When HcRhDescriptorB.PPCM = H'0002, the port responds only to port power commands (Set/ClearPortPower). When the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower).
7 to 0
NDP
H'02
R
Number of Downstream Ports These bits specify the number of downstream ports supported by the root hub. It is implementationspecific. The value of these bits is H'2. However, this LSI supports only 1 port for downstream.
21.3.20 Root Hub Descriptor B Register (HcRhDescriptorB) HcRhDescriptorB is the second register of two describing the characteristics of the root hub. Set the bits of this register on initial setup so as to cater for system implementation.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPCM 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 DR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0
Rev. 1.0, 02/03, page 742 of 1294
Bit 31 to 16
Bit Name PPCM
Initial Value All 0
R/W R/W
Description Port Power Control Mask Each bit indicates whether or not the corresponding port is affected by a global power control command when HcRhDescriptorA.PSM = 1. When a bit is set to 1, the corresponding port's power state is affected only by per-port power control (Set/ClearPortPower). When a bit is cleared to 0, the corresponding port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PSM = 0), settings in these bits are not valid. H0000: Port 1 is affected by global power control H0002: Port 1 is masked from global power control Other than above: Setting prohibited Bit 16: Reserved Bit 17: Ganged-power mask on Port 1 Bit 18: Ganged-power mask on Port 2 ... Bit 31: Ganged-power mask on Port 15 Note: Before setting these bits, clear HcRhDescriptorA.NPS = 0 and HcRhPortStatus.PPS = 0 to turn off the power of all ports.
15 to 0
DR
All 0
R/W
Device Removable Each bit is used only for a port of the root hub. When a bit is cleared to 0, the attached device is removable from the corresponding port. When a bit is set to 1, the attached device is not removable from the corresponding port. H0000: Device connected to port 1 can be removed H0002: Device connected to port 1 cannot be removed Other than above: Setting prohibited Bit 0: Reserved Bit 1: Device attached to Port 1 Bit 2: Device attached to Port 2 ... Bit 15: Device attached to Port 15
Rev. 1.0, 02/03, page 743 of 1294
21.3.21 Root Hub Status Register (HcRhStatus) HcRhStatus is divided into two parts. The high-order word in a longword represents the hub status change bits and the low-order word in a longword represents the hub status bits. Since this register functions differently in read than in write, functional descriptions will be made separately below. Note that bit titles in read are different from those in write so that bit titles can always suit the functions. For the bit name, the bit title for a read operation is used. Taking bit 0 as an example, the bit name is LPS and the bit title in read is Local Power Status while that in write is Clear Global Power. * Read
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 CRWE 0 R 15 DRWE 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 16 OCIC LPSC 0 R 1 OCI 0 R 0 R 0 LPS 0 R
Bit 31 30 to 18 17
Bit Name CRWE OCIC
Initial Value 0 All 0 0
R/W R R R
Description Reserved These bits are always read as 0. Reserved These bits are always read as 0. Overcurrent Indicator Change This bit is set to 1 by hardware when a change has occurred to the OCI bit of this register. 0: Operation is not affected 1: Overcurrent indicator has changed
16
LPSC
0
R
Local Power Status Change The root hub does not support the local power status function, thus, this bit is always read as 0.
15
DRWE
0
R
Device Remote Wakeup Enable When this bit is 1, the CSC bit is enabled as a resume event, causing a USB suspend to USB resume state transition and setting the RD interrupt. 0: Does not generate device remote wakeup event 1: Generates device remote wakeup event
Rev. 1.0, 02/03, page 744 of 1294
Bit 14 to 2 1
Bit Name OCI
Initial Value All 0 0
R/W R R
Description Reserved These bits are always read as 0. Overcurrent Indicator This bit reports overcurrent conditions when the global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented, this bit is always 0. 0: No port is in overcurrent state 1: A port is in overcurrent state
0
LPS
0
R
Local Power Status The root hub does not support the local power status function, thus, this bit is always read as 0.
* Write
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 CRWE 0 W 15 DRWE 0 W 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 16 OCIC LPSC 0 W 1 OCI 0 R 0 W 0 LPS 0 W
Bit 31
Bit Name CRWE
Initial Value 0
R/W W
Description Clear Remote Wakeup Enable Writing 1 to this bit clears the DRWE bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The DRWE bit is cleared to 0
30 to 18 17
OCIC
All 0 0
R W
Reserved Always write 0 to this bit. Overcurrent Indicator Change HCD clears this bit to 0 by writing 1. Writing 0 has no effect. 0: Operation is not affected 1: The OCIC bit is cleared to 0
Rev. 1.0, 02/03, page 745 of 1294
Bit 16
Bit Name LPSC
Initial Value 0
R/W W
Description Set Global Power In global power mode (PSM = 0), writing 1 to this bit will power all ports on (and clear the PPS bit to 0). In per-port power mode, it will set the PPS bit to 1 only on ports whose PPCM bit is not set. Writing 0 has no effect. 0: Operation is not affected 1: Power of all ports is turned on
15
DRWE
0
W
Set Remote Wakeup Enable Writing 1 to this bit sets the DRWE bit to 1. Writing 0 has no effect. 0: Operation is not affected 1: Device remote wakeup is enabled
14 to 2 1 0
OCI LPS
All 0 0 0
R R W
Reserved Always write 0 to this bit. Reserved Always write 0 to this bit. Clear Global Power In global power mode (PSM = 0), writing 1 to this bit will power all ports off (and clear the PPS bit to 0). In per-port power mode, it will clear the PPS bit to 0 only on ports whose PPCM bit is not set. Writing 0 has no effect. 0: Operation is not affected 1: Power of all ports is turned off
21.3.22 Root Hub Port Status 1 Register (HcRhPortStatus1) HcRhPortStatus1 is used for controlling and reporting the port event for each port. The upper word indicates the change of the port status and the lower word indicates the port status. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. Reserved bits should always be written 0. Since this register functions differently in read than in write, functional descriptions will be made separately below. Note that bit titles in read are different from those in write so that the bit titles can always suit the functions. For the bit name, the bit title for a read operation is used. Taking a
Rev. 1.0, 02/03, page 746 of 1294
bit 0 for example, the bit name is CCS and the bit title in read is Current Connect Status, while that in write is Clear Port Enable. * Read
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 24 0 R 8 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 19 18 17 16 PRSC OCIC PSSC PESC CSC 0 R 4 PRS 0 R 0 R 3 POCI 0 R 0 R 2 PSS 0 R 0 R 1 PES 0 R 0 R 0 CCS 0 R
LSDA PPS 0 R 1 R
Bit 31 to 21 20
Bit Name PRSC
Initial Value All 0 0
R/W R R
Description Reserved These bits are always read as 0. Port Reset Status Change This bit is set to 1 at the end of the 10-ms port reset signal. 0: Port reset is not complete 1: Port reset is complete
19
OCIC
0
R
Overcurrent Indicator Change This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when root hub changes the POCI bit. 0: POCI has not changed 1: POCI has changed
18
PSSC
0
R
Port Suspend Status Change This bit is set to 1 when the full resume sequence has been completed. This sequence includes the 20-ms resume pulse, LS EOP, and 3-ms resychronization delay. 0: Port resume is incomplete, or PRSC bit is set to 1 1: Port resume is complete
17
PESC
0
R
Port Enable Status Change This bit is set to 1 when a hardware event clears the PES bit to 0. Writing 1 by HCD does not set this bit to 1. 0: PES has not changed 1: PES has changed
Rev. 1.0, 02/03, page 747 of 1294
Bit 16
Bit Name CSC
Initial Value 0
R/W R
Description Connector Status Change This bit is set to 1 when a connect or disconnect event occurs. If CCS is cleared to 0 when a write to PPS, PES, or PPS occurs, this bit is set to 1 to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0: CCS has not changed 1: CCS has changed Note: When the DR bit is 1, this bit is set to 1 only after a root hub reset to inform the system that the device is attached.
15 to 10 9
LSDA
All 0 0
R R
Reserved These bits are always read as 0. Low-Speed Device Attached This bit indicates the speed of the device attached to this port. When this bit is 1, a low speed device is attached to this port. When this bit is 0, a full speed device is attached to this port. This bit is valid only when the CCS is set to 1. 0: Full-speed device is attached 1: Low-speed device is attached
Rev. 1.0, 02/03, page 748 of 1294
Bit 8
Bit Name PPS
Initial Value 1
R/W R
Description Port Power Status This bit reflects the port's power status, regardless of the type of power switching implemented. Since the initial value of the NPS bit in HcRhDescriptorA is 1, this bit is initially set to 1. The NPS bit should be cleared to 0 beforehand in order to enable power switching. This bit is cleared to 0 if an overcurrent condition is detected. HCD sets this bit to 1 by writing PPS or LPSC. HCD clears this bit to 0 by writing LSDA or OCI. Which power control switches are enabled is determined by PSM and PPCM. In global switching mode (PSM = 0), only Set/ClearGlobalPower command controls this bit. In per-port power switching (PSM = 1), when the PPCM bit for the port is set to 1, only Set/ClearPortPower commands are enabled. When port power is disabled, CCS, PES, PSS, and PRS should be reset. 0: Power of port is turned off 1: Power of port is turned on Note: This bit is always read as 1 when power switching is not supported.
7 to 5 4
PRS
All 0 0
R R
Reserved These bits are always read as 0. Port Reset Status When this bit is set by a write to this bit, port reset signal is asserted. When reset is completed, this bit is cleared when PRSC is set. This bit cannot be set if CCS is cleared. 0: Port is not in reset state 1: Port is in reset state
Rev. 1.0, 02/03, page 749 of 1294
Bit 3
Bit Name POCI
Initial Value 0
R/W R
Description Port Overcurrent Indicator This bit is only valid when the root hub is configured in such a way that overcurrent conditions are reported on a per-port basis. When per-port overcurrent reporting is not supported, this bit is cleared to 0. When this bit is 0, all power operations are normal for this port. When this bit is 1, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0: Port is not in overcurrent state 1: Port is in overcurrent state
2
PSS
0
R
Port Suspend Status This bit indicates the port is suspended or is in the resume sequence. It is set to 1 by a SetSuspendState write and cleared to 0 when PSSC is set to 1 at the end of the resume interval. This bit cannot be set to 1 when CCS is 0. This bit is also cleared to 0 when PRSC is set to 1 at the end of the port reset or when HC enters the USB resume state. When an upstream resume is in progress, it should propagate to HC. 0: Port is not in suspend state 1: Port is in suspend state
1
PES
0
R
Port Enable Status This bit indicates whether the port is enabled or disabled. The root hub may clear this bit to 0 when detecting an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble. This change also sets PESC to 1. HCD sets this bit to 1 by writing 1 to this bit and clears to 0 this bit by writing CSS. This bit cannot be set to 1 when CCS is 0. This bit is also set, if not already, on completion of a port reset when PRSC is set or port suspend when PSSC is set. 0: Port is disabled 1: Port is enabled
0
CCS
0
R
Current Connect Status This bit reflects the current state of the downstream port. 0: Device is not connected to port 1: Device is connected to port Note: This bit is always read 1 when the attached device is non-removable (DR = H0002).
Rev. 1.0, 02/03, page 750 of 1294
* Write
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 LSDA 0 W 24 0 R 8 PPS 1 W 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 19 18 17 16 PRSC OCIC PSSC PESC CSC 0 W 4 PRS 0 W 0 W 3 POCI 0 W 0 W 2 PSS 0 W 0 W 1 PES 0 W 0 W 0 CCS 0 W
Bit 31 to 21 20
Bit Name PRSC
Initial Value All 0 0
R/W R W
Description Reserved Always write 0 to this bit. Port Reset Status Change HCD writes 1 to this bit to clear this bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The PRSC bit is cleared to 0
19
OCIC
0
W
Overcurrent Indicator Change HCD writes 1 to this bit to clear this bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The OCIC bit is cleared to 0
18
PSSC
0
W
Port Suspend Status Change HCD writes 1 to this bit to clear this bit to 0. Writing 0 has no effect. Setting PRSC to 1 will also clear this bit to 0. 0: Operation is not affected 1: The PSSC bit is cleared to 0
Rev. 1.0, 02/03, page 751 of 1294
Bit 17
Bit Name PESC
Initial Value 0
R/W W
Description Port Enable Status Change HCD writes 1 to this bit to clear this bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The PESC bit is cleared to 0
16
CSC
0
W
Connect Status Change HCD writes 1 to this bit to clear this bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The CSC bit is cleared to 0
15 to 10 9
LSDA
All 0 0
R W
Reserved Always write 0 to this bit. Clear Port Power HCD writes 1 to this bit to clear the PPS bit to 0. Writing 0 has no effect. 0: Operation is not affected 1: The PPS bit is cleared to 0 and the power of the port is turned off
8
PPS
1
W
Set Port Power HCD writes 1 to this bit to set this bit to 1. Writing 0 has no effect. 0: Operation is not affected 1: The PPS bit is set to 1 and the power of the port is turned on
7 to 5 4
PRS
All 0 0
R W
Reserved Always write 0 to this bit. Set Port Clear HCD writes 1 to this bit to set the port reset signal. Writing 0 has no effect. Clearing CCS to 0 will not set this bit to 1 but will set CSC to 1 instead. This informs the driver that a disconnected port is reset. 0: Operation is not affected 1: The PRS bit is set to 1
Rev. 1.0, 02/03, page 752 of 1294
Bit 3
Bit Name POCI
Initial Value 0
R/W W
Description Clear Suspend Status HCD writes 1 to this bit to initiate a resume. Writing 0 has no effect. Setting both PSS and this bit to 1 starts a resume. 0: Operation is not affected 1: Resume is started
2
PSS
0
W
Set Port Suspend HCD sets this bit to 1 by writing 1. Writing 0 has no effect. Clearing CCS to 0 does not set PSS to 1 but sets CSC to 1 instead. It informs the driver that a disconnected port is suspended. 0: Operation is not affected 1: The PPS bit is set to 1 and the port is suspended
1
PES
0
W
Set Port Enable HCD sets this bit to this bit by writing 1. Writing 0 has no effect. Clearing CCS to 0 does not set PES to 1 but sets CSC to 1 instead. It informs the driver that a disconnected port is enabled. 0: Operation is not affected 1: The PES bit is set to 1 and the port is enabled
0
CCS
0
W
Clear Port Enable HCD writes 1 to this bit to clear the PES bit to 0. Writing 0 has no effect. CCS is not affected by any write. 0: Operation is not affected 1: The PES bit is cleared to 0 and the port is disabled
Rev. 1.0, 02/03, page 753 of 1294
21.4
Memory
The USB host has on-chip 8-kbyte SRAM as a shared memory which is defined in the OpenHCI specification. Write access to the shared memory is possible in bytes, words, or longwords. The data format is little endian. The MSB is bit 31 and the LSB is bit 0. The user can use the endian conversion in bytes or in words by rewriting an appropriate value in the CVRT bit in DMAUCR. Figure 21.2 shows a memory map of the shared memory. When area P4 is selected as the register area, the CPU sees the shared memory area to be mapped into HFE34 1000 to HFE34 2FFF, while the HC sees it to be mapped into H0000 0000 to H0000 1FFF. Therefore when the HC accesses the shared memory, the area from H0000 0000 to H0000 1FFF must be specified. The shared memory area is mapped into HFE34 1000 to HFE34 2FFF in area P4 or into H1E34 1000 to H1E34 2FFF in area 7. For details, see section 32, List of Registers.
H'FE34 2FFF
H'0000 1FFF
CPU
Shared memory
Host controller (HC)
H'FE34 1000
H'0000 0000 USB host
Figure 21.2 Memory Map of Shared Memory
Rev. 1.0, 02/03, page 754 of 1294
21.5
21.5.1
Data Storage Format for USB Host Controller
Storage Format of Transfer Data
The USB host controller assumes that data in shared memory is stored in the byte order where the first data is placed in the lower address while the last data in the higher address, regardless of the endian setting of the CPU. Figure 21.3 shows USB read operation.
Program DATA.L DATA.L DATA.L H'1122 3344 H'5566 7788 H'0000 0099 Shared memory +3 +2 11 22 +7 +6 55 66 +11 +10 00 00 +1 33 +5 77 +9 00 +0 44 +4 88 +8 99 USB host LW read H'1122 3344 LW read H'5566 7788 LW read H'0000 0099
Figure 21.3 USB Read Operation Data order in shared memory should correspond with the order of data read by the USB host controller. When reading data from external memory, the USB host controller reads data in longwords regardless of the endian setting. The USB host controller assumes that read data is in the byte order that places the first byte to the lower address and the last byte to the higher address. Namely, data in shared memory must be stacked from lower address to higher, regardless of whether big or little endian is selected. An example of failure is shown in figure 21.4.
The transfer address A is specified in the program (big endian mode). MOV.B #H'12. @R0 The transfer start address A and 1-byte transfer size for USB is specified.
Memory +3 12 +2 00 +1 00 +0 00 Data expected to be transferred LW read H'1200 0000 Actually transferred data
Figure 21.4 Example of Transfer Failure In this example, USB host controller does not receive #H'12, which is the expected transfer data. The USB host controller stacks data from low-order bits of the memory when writing so that the data is correctly read/written on both sides regardless of the endian setting. That is, the data is always aligned in little endian format.
Rev. 1.0, 02/03, page 755 of 1294
21.5.2
Storage Format of the Descriptor
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of the USB host controller must be placed such that each Dword is aligned on a longword boundary (addresses 4n to 4n + 3) of the memory. Each descriptor must be aligned on a memory address boundary prescribed by the OpenHCI specification Ver.1.0.
21.6
Restrictions on HcRhDescriptorA
When modifying initial settings of the NOCP or OCPM bits in HcRhDescriptorA after reset, keep the following in mind. 1. The initial values are NOCP=1 and OCPM=0, and the USB host controller does not detect overcurrent. To use the overcurrent detection, set NOCP = 0 and OCPM = 1 simultaneously. Modify these bits only once during USB host controller initialization. Do not modify them more than once. 2. Making the settings in step 1 above will not change the settings in the OCI and OCIC bits in HcRhStatus for overcurrent condition information. These bits should be ignored. 3. Making the settings in step 1 above will set HcInterruptStatus.RHSC = 1 even if a port is not in overcurrent condition. Therefore, perform interrupt handling processing shown in figure 21.5.
Start of RHSC interrupt handling
Interrupt source is set in HcRhStatus and HcRhPortStatus1? Yes
No
Perform handling for interrupt sources indicated by HcRhStatus and HcRhPortStatus1
Clear RHSC in HcInterruptStatus
End of RHSC interrupt handling
Figure 21.5 Example of RHSC interrupt handling
Rev. 1.0, 02/03, page 756 of 1294
Section 22 Hitachi Controller Area Network 2 (HCAN2)
The Hitachi Controller Area Network 2 (HCAN2) is a module that controls the Controller Area Network (CAN) provided for realtime communication in automobiles or industrial equipment systems. For details on the CAN specification, refer to the CAN Specification Version 2.0, Robert Bosch GmbH, 1991. The section places no constraints upon the implementation of the HCAN2 module in terms of process, packaging or power supply criteria. These issues are resolved appropriately in implementation specifications.
22.1
Features
* Supports CAN specification 2.0A/2.0B and ISO-11898: * 31 programmable transmit/receive Mailboxes and one receive-only Mailbox * Sleep mode for low power consumption and automatic recovery from sleep mode by detecting the CAN bus being active * Programmable receive filter masks (standard identifier and extended identifier) are supported by all Mailboxes * Programmable CAN data rate up to 1 Mbit/s * Transmit message queuing with internal priority sorting mechanism against a priority inversion problem of the real time application * Data buffer access without using handshake * Flexible CPU interface * Flexible interrupt structure * A 16-bit free running timer with flexible clock sources and pre-scaler, timer compare match register * Supports flexible time stamp function for both transmission and reception (the stamp timing is programmable)
22.2
22.2.1
Architecture
Block diagram
HCAN2 offers a flexible and sophisticated method for the organization and control of CAN frames, which is compliant to CAN2.0B Active and ISO-11898. The module is formed from 5 different functional entities. These are the Micro Processor Interface (MPCI), Mailbox, Mailbox
Rev. 1.0, 02/03, page 757 of 1294
Control, Timer and CAN Interface. The figure below shows the block diagram of the module. The bus interface timing is designed based on SH internal bus interface.
CAN bus CAN Rx CAN Interface CANREC Can core CANTEC CAN Tx CAN_NERR
CANBCR
Transmit buffer
Receive buffer Control signals Status signals
Data-in[15:0] Data-out[15:0] Address[10:0] Clock Reset Interrupt Wait
CPU interface
HCAN2 internal bus
CANTXPR CANTXCR CANRXPR
CANTXACK CANABACK CANRFPR CANUMSR
CANMCR CANGSR
CANIRR CANIMR
CANMBIMR
16 bit bus
Mailbox control These registers are doubled Mailbox0 Mailbox1 Mailbox2 Mailbox3 Mailbox4 Mailbox5 Mailbox6 Mailbox7 Mailbox8 Mailbox9 Mailbox10 Mailbox11 Mailbox12 Mailbox13 Mailbox14 Mailbox15 Mailbox16 Mailbox17 Mailbox18 Mailbox19 Mailbox20 Mailbox21 Mailbox22 Mailbox23 Mailbox24 Mailbox25 Mailbox26 Mailbox27 Mailbox28 Mailbox29 Mailbox30 Mailbox31
CANTCNTR CANTCR
CANTCMR
16-bit timer
Mailbox0-31 (RAM) Note: Since the HCAN2 is designed on the basis of a 16-bit bus system, longword (32-bit) accesses are prohibited. All registers can be accessed with words and mailboxes can be accessed with words or bytes. Legend: CANTCNTR CANTCR CANTCMR CANMCR CANGSR CANIRR CANIMR CANBCR CANREC : Timer counter register : Timer control register : Timer compare match register : Master control register : General status register : Interrupt request register : Interrupt mask register : Bit configuration register : Receive error counter CANTEC CANTXPR CANTXCR CANTXACK CANABACK CANRXPR CANRFPR CANMBIMR CANUMSR : Transmit error counter : Transmit pending request register : Transmit cancel register : Transmit acknowledge register : Abort acknowledge register : Receive data frame pending register : Remote frame request pending register : Mailbox interrupt mask register : Unread message status register
Figure 22.1 Block Diagram of HCAN2 Module
Rev. 1.0, 02/03, page 758 of 1294
22.2.2
Block Function
(1) Micro Processor Interface (MPI) The MPI allows communication between the CPU and the HCAN2 registers/mailboxes to control the timer unit, memory interface and data controller, etc. It also contains the wakeup control logic that detects the CAN bus activities and notifies the MPI and the other parts of HCAN2 so that the HCAN2 can automatically exit the Sleep mode. The MPI has four registers CANMCR, CANIRR, CANGSR and CANIMR. (2) Mailbox Mailboxes are essentially RAM configured as message buffers. There are 32 Mailboxes, and each mailbox stores the following information. * CAN message control (identifier, dlc, rtr, ide, etc) * CAN message data (for CAN data frames) * Time Stamp for message receive/transmit * Local Acceptance Filter Mask for mailboxes configured to receive * 3-bit width Mailbox Configuration, Disable Automatic Re-Transmission bit, AutoTransmission of response to remote frame request and New Message Control bit. (3) Mailbox Control The Mailbox control supports the following functions. For received message, it compares the IDs and generates appropriate RAM address and data to store messages from the CAN interface into the Mailbox, and set/clear the appropriate registers accordingly. To transmit message, it runs the internal arbitration to pick the correct priority message and loads the message from the Mailbox into the buffer of the CAN Interface, and set/clear appropriate registers accordingly. Arbitrate Mailbox accesses between the host CPU and the Mailbox Control. The Mailbox control has registers CANTXPR, CANTXCR, CANTXACK, CANABACK, CANRXPR, CANRFPR, and CANMBIMR. (4) Timer With the use of the Time Stamp field, the Timer module allows HCAN2 to record the time in which the messages are transmitted and received.
Rev. 1.0, 02/03, page 759 of 1294
The timer is a 16-bit free running counter that can be controlled by the host CPU. It provides one 16-bit Compare Match Register that holds a reference timer value. When the value of the free running 16-bit timer matches the reference value hold in the compare match register, an interrupt signal is generated. The clock period of this Timer offers a wide selection derived from the system clock. The timer has registers CANTCNTR, CANTCR, and CANTCMR. (5) CAN Interface The CAN interface supports the CAN Bus Data Link Controller specification described in CAN Specification Version 2.0, Robert Bosch GmbH, 1991. This block fulfils all the functions of the standard DLC as specified by the OSI 7 Layer Reference model. This functional entity also provides the registers and logic specific to a given CAN bus, which includes the Receive Error Counter, Transmit Error Counter, the Bit Configuration Registers and various useful test modes. This block also contains functional entities to hold the data received and the data to be transmitted for the CAN Data Link Controller.
22.3
Input/Output Pins
Table 22.1 summarizes the pins of the HCAN2. Table 22.1 Pin Configuration
Pin Name CAN0_RX CAN0_TX CAN0_NERR CAN1_RX CAN1_TX CAN1_NERR I/O Input Output Input Input Output Input Function CAN bus receive signal of channel 0 CAN bus transmit signal of channel 0 CAN bus error of channel 0 CAN bus receive signal of channel 1 CAN bus transmit signal of channel 1 CAN bus error of channel 1
22.4
22.4.1
Programming model - overview
Memory map
The diagram of the memory map is shown in Fig. 22.2.
Rev. 1.0, 02/03, page 760 of 1294
Bit15 H'000 H'002 H'004 H'006 H'008 H'00A H'00C H'020 H'022 H'028 H'02A H'030 H'032 H'038 H'03A Master control register (CANMCR) General status register (CANGSR) Bit configuration register 1 (CANBCR1) Bit configuration register 0 (CANBCR0) Interrupt request register (CANIRR)
Bit0 H'100 Mailbox-0 control (BaseID,ExtID,Rtr,Ide,DLC,ATX,DART,MBC) H'106 H'108 H'10A H'10C H'10E H'110 Mailbox-0 acceptance filter mask 0 Mailbox 0 time stamp 1 2 3 Mailbox-0 data (8 bytes) 4 5 6 7
Interrupt mask register (CANIMR) Receive error counter Transmit error (CANREC) counter (CANTEC) Transmit pending request register 1 (CANTXPR1) Transmit pending request register 0 (CANTXPR0) Transmit cancel register 1 (CANTXCR1) Transmit cancel register 0 (CANTXCR0) Transmit acknowledge register 1 (CANTXACK1) Transmit acknowledge register 0 (CANTXACK0) Abort acknowledge register 1 (CANABACK1) Abort acknowledge register 0 (CANABACK0)
H'120 H'140 H'160
Mailbox-1 control / time stamp/ data / LAFM Mailbox-2 control / time stamp/ data / LAFM Mailbox-3 control / time stamp/ data / LAFM
H'040 Receive data frame pending register 1 (CANRXPR1) H'042 Receive data frame pending register 0 (CANRXPR0) H'048 Remote frame request pending register 1 (CANRFPR1) H'04A Remote frame request pending register 0 (CANRFPR0) H'050 H'052 H'058 H'05A H'080 H'082 H'090 Mailbox interrupt mask register 1 (CANMBIMR1) Mailbox interrupt mask register 0 (CANMBIMR0) Unread message status register 1 (CANUMSR1) Unread message status register 0 (CANUMSR0) Timer counter register (CANTCNTR) Timer control register (CANTCR) Timer compare match register (CANTCMR) H'4A0 Mailbox-29 control / time stamp/ Data / LAFM H'4C0 Mailbox-30 control / time stamp/ Data / LAFM H'4E0 Mailbox-31 control / time stamp/ Data / LAFM H'4F3
H'2E0 Mailbox-15 control / time stamp/ data / LAFM H'2F3 H'300 Mailbox-16 control / time stamp/ data / LAFM
Figure 22.2 HCAN2 Memory Map 22.4.2 Mail box
Mailboxes function as message buffers to transmit/receive CAN frames. Each Mailbox is comprised of four identical storage fields: 1) Message Control, 2) Message Data, 3) Time Stamp and 4) Local Acceptance Filter Mask. Table 22.2 shows the address map for the control, data, timestamp and LAFM address for each mailbox.
Rev. 1.0, 02/03, page 761 of 1294
Notes: 1. The Message Control, Timestamp and LAFM fields can only be accessed with 16 bits, whereas the Message Data area can be accessed in units of 16 bits or 8 bits. Also, unused parts of Mailboxes must be initialized during the configuration to their inactive state as they are in effect configured of RAM. When the LAFM is not used to receive messages, it must be cleared. 2. Unused Mailboxes can be used as extra memory. However, it is important in such case to disable the related mailbox (setting MBC to B'111) in order to avoid that the mailbox joins the search for a matching identifier during the reception of messages, and even store a wrong message in the worst case.
Rev. 1.0, 02/03, page 762 of 1294
Table 22.2 Address map
Address Control Mailbox 0 (receive-only) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 6 Bytes 100 to 105 120 to 125 140 to 145 160 to 165 180 to 185 1A0 to 1A5 1C0 to 1C5 1E0 to IE5 200 to 205 220 to 225 240 to 245 260 to 265 280 to 285 2A0 to 2A5 2C0 to 2C5 2E0 to 2E5 300 to 305 320 to 325 340 to 345 360 to 365 380 to 385 3A0 to 3A5 3C0 to 3C5 3E0 to 3E5 400 to 405 420 to 425 440 to 445 460 to 465 480 to 485 4A0 to 4A5 4C0 to 4C5 4E0 to 4E5 Time Stamp 2 Bytes 106 to 107 126 to 127 146 to 147 166 to 167 186 to 187 1A6 to 1A7 1C6 to 1C7 1E6 to 1E7 206 to 207 226 to 227 246 to 247 266 to 267 286 to 287 2A6 to 2A7 2C6 to 2C7 2E6 to 2E7 306 to 307 326 to 327 346 to 347 366 to 367 386 to 387 3A6 to 3A7 3C6 to 3C7 3E6 to 3E7 406 to 407 426 to 427 446 to 447 466 to 467 486 to 487 4A6 to 4A7 4C6 to 4C7 4E6 to 4E7 Data 8 Bytes 108 to 10F 128 to 12F 148 to 14F 168 to 16F 188 to 18F 1A8 to 1AF 1C8 to 1CF 1E8 to 1EF 208 to 20F 228 to 22F 248 to 24F 268 to 26F 288 to 28F 2A8 to 2AF 2C8 to 2CF 2E8 to 2EF 308 to 30F 328 to 32F 348 to 34F 368 to 36F 388 to 38F 3A8 to 3AF 3C8 to 3CF 3E8 to 3EF 408 to 40F 428 to 42F 448 to 44F 468 to 46F 488 to 48F 4A8 to 4AF 4C8 to 4CF 4E8 to 4EF LAFM 4 Bytes 110 to 113 130 to 133 150 to 153 170 to 173 190 to 193 1B0 to 1B3 1D0 to 1D3 1F0 to 1F3 210 to 213 230 to 233 250 to 253 270 to 273 290 to 293 2B0 to 2B3 2D0 to 2D3 2F0 to 2F3 310 to 313 330 to 333 350 to353 370 to 373 390 to 393 3B0 to 3B3 3D0 to 3D3 3F0 to 3F3 410 to 413 430 to 433 450 to 453 470 to 473 490 to 493 4B0 to 4B3 4D0 to 4D3 4F0 to 4F3
Rev. 1.0, 02/03, page 763 of 1294
Mailbox 0 is a receive-only box but Mailboxes 1 to 31 can operate as both receive and transmit boxes, depending on the MBC bits in the Message Control. The following diagram shows the structure of a Mailbox in detail.
Address 15 H'100 + N*32 H'102 + N*32 H'104 + N*32 H'106 + N*32 H'108 + N*32 H'10A + N*32 H'10C + N*32 H'10E + N*32 H'110 + N*32 H'112 + N*32 NMC ATX DART 0 14 13 12 11 10 Data bus 9 8 7 Access Size 16 bits 16 bits CBE DLC[3:0] 8/16 bits 16 bits MSG_DATA_1 MSG_DATA_3 MSG_DATA_5 MSG_DATA_7 8/16 bits 8/16 bits Data MSG_DATA_4 MSG_DATA_6 8/16 bits 8/16 bits 16 bits LAFM Local acceptance filter mask 1 (LAFM1) 16 bits Notes: 1. All bits shadowed in gray are reserved and the write value should always be 0. The read value is not guaranteed. 2. ATX and DART are not supported by mailbox 0, and the MBC setting of mailbox 0 is restricted. Time stamp Control Field Name
6
5
4
3
2
STDID[10:0] EXTID[15:0] MBC[2:0] 0
RTR IDE
1 0 EXTID [17:16]
TimeStamp[15:0] MSG_DATA_0 (first Rx/Tx byte) MSG_DATA_2
Local acceptance filter mask 0 (LAFM0)
Figure 22.3 Mailbox N Structure
Rev. 1.0, 02/03, page 764 of 1294
(1) Message Control Field
Address H'100 + N*32 Bit 15 Bit Name Description Reserved The write value should always be 0. The read value is not guaranteed.
14 to STDID10 Standard ID 4 to STDID0 These bits set Identifiers (Standard Identifiers) of Data Frames and remote Frames. 3 RTR Remote Transmission Request Used to distinguish between Data Frames and Remote Frames. This bit is overwritten by the received CAN frames depending on Data Frame or Remote Frame. Important: Note that when the ATX bit is set with the setting MBC = B'001, the RTR bit will never be set. When a Remote Frame is received, the host CPU can be notified by CANRFPR set or IRR2 (Remote Frame Request Interrupt), however, as HCAN2 needs to transmit the current message as a Data Frame, the RTR bit remains 0. 0: Data Frame 1: Remote Frame H'100 + N*32 2 IDE Identifier Extension Used to distinguish between the standard format and extended format of CAN data frames and remote frames. 0: Standard format 1: Extended format 1 0 H'102 + N*32 H'104 + N*32 EXTID17 EXTID16 Identifier Extension These bits set Identifiers (Extended identifiers) for Data Frames and Remote Frames.
15 to EXTID15 0 to EXTID0 15 14
Reserved The write value should always be 0. The read value is not guaranteed.
Rev. 1.0, 02/03, page 765 of 1294
Address H'104 + N*32
Bit 13
Bit Name NMC
Description New Message Control When this bit is cleared to 0, the Mailbox of which CANRXPR/CANRFPR bit is already set does not store the new message but maintains the old one and sets the corresponding CANUMSR bit. When this bit is set to 1, the Mailbox of which CANRXPR/CANRFPR bit is already set overwrites with the new message and sets the corresponding CANUMSR bit. Automatic Transmission of Data Frame When this bit is set to 1 and a Remote Frame is received into the Mailbox, a Data Frame is transmitted from the same Mailbox using the current contents of the message data by setting the corresponding CANTXPR automatically. The scheduling of transmission is still governed by CAN identifier. In order to use this function, MBC[2:0] needs be programmed to B'001. Important : Note that when this function is used, the RTR bit will never be set despite receiving a Remote Frame. When a Remote Frame is received, the host CPU will be notified by the corresponding CANRFPR set, however, as the HCAN2 needs to transmit the current message as a Data Frame, the RTR bit remains 0. If a mailbox is configured to receive Remote Frames, then the RTR bit is overwritten by the received CAN Frames. Disable Automatic Re-Transmission When this bit is set, it disables the automatic re-transmission of a message in the event of an error on the CAN bus or an arbitration lost on the CAN bus. When this function is used, the corresponding CANTXCR bit is automatically set at the start of transmission. When this bit is cleared, the HCAN2 tries to transmit the message as many times as required until it is successfully transmitted or it is cancelled by CANTXCR. Mailbox Configuration These bits configure the nature of each Mailbox as shown in Table 22.3. When MBC is set to B'111, the Mailbox is inactive, i.e., it does not receive or transmit a message regardless of CANTXPR or other settings. The setting of MBC = 110 is prohibited. Reserved The write value should always be 0. The read value is not guaranteed.
12
ATX
11
DART
10 9 8
MBC2 MBC1 MBC0
7 6

Rev. 1.0, 02/03, page 766 of 1294
Address H'104 + N*32
Bit 5
Bit Name CBE
Description CAN Bus Error An external fault-tolerant CAN transceiver can be used together with the HCAN2 module. In such case the error output pin of the transceiver must be connected to the CAN_NERR pin. The value of CAN_NERR is stored into the CBE bit at the end of each Transmit/Receive (if the message is stored). This bit reports the inverted value of the CAN_NERR pin. Then, using a transceiver with error pin active low, CBE shows a potential physical error with the CAN bus when set to 1. If a transceiver with error pin active high is used the notation must be inverted. As the CAN_NERR value will be updated after transmission or reception in the correspondent Mailbox noninterrupt is dedicated for this function but instead the interrupt for successful transmission (IRR8) or reception (IRR2) should be considered. Reserved The write value should always be 0. The read value is not guaranteed. Data Length Code These bits encode the number of bytes from 0, 1, 2, ... 8 that will be transmitted in a Data Frame. 0000: Data length = 0 byte 0001: Data length = 1 byte 0010: Data length = 2 bytes 0011: Data length = 3 bytes 0100: Data length = 4 bytes 0101: Data length = 5 bytes 0110: Data length = 6 bytes 0111: Data length = 7 bytes 1xxx: Data length = 8 bytes
4
3 2 1 0
DLC3 DLC2 DLC1 DLC0
Rev. 1.0, 02/03, page 767 of 1294
Table 22.3 Settings of Mailbox Functions
Data Frame Transmit Yes Yes Remote Frame Transmit Yes Yes Data Frame Receive No No Remote Frame Receive No Yes * * * * 0 1 0 No No Yes Yes * * 0 1 1 No No Yes No * * 1 0 0 No Yes Yes Yes * * 1 0 1 No Yes Yes No * * 1 1 1 1 0 1 Setting prohibited Mailbox inactive
MBC2 0 0
MBC1 0 0
MBC0 0 1
Remarks Not allowed for Mailbox 0 Can be used with ATX Not allowed for Mailbox 0 LAFM can be used Allowed for Mailbox 0 LAFM can be used Allowed for Mailbox 0 LAFM can be used Not allowed for Mailbox 0 LAFM can be used Not allowed for Mailbox 0 LAFM can be used
(2) (Mailbox) Timestamp Field Storage for the Timestamp on message for transmit/receive. The Timestamp is a function useful for monitoring when a message is transmitted/received: it can be used to verify if the reception/transmission of messages are within an expected schedule. (3) Message Data Field Storage for the CAN message data that is transmitted or received. MSG_DATA_0 corresponds to the first data byte that is transmitted or received. The bit order on the bus is bit 7 through to bit 0. (4) Local Acceptance Filter Mask (LAFM) This area is used as the Local Acceptance Filter Mask (LAFM) for a receive mailboxes. * LAFM The LAFM is comprised of two 16-bit read/write areas as follows. It allows a Mailbox to accept more than one identifier for receive.
Rev. 1.0, 02/03, page 768 of 1294
H'110 + N*32 H'112 + N*32
0
STDID_LAFM[10:0] EXTID_LAFM[15:0]
0
0
EXTID_LAFM [17:16]
16 bits 16 bits
LAFM field
Figure 22.4 Acceptance Filter If a bit is set in the LAFM, the corresponding bit of the received CAN identifier is ignored when the HCAN2 searches a Mailbox with the matching CAN identifier. If the bit is cleared, the corresponding bit of the received CAN identifier must match the STD_ID/EXT_ID set in the mailbox, in which the CAN frame is to be stored. The structure of the LAFM is the same as the Message Control in a Mailbox. If this function is not required, it must be filled with 0. Notes: 1. HCAN2 starts to find a matching identifier from Mailbox 31 down to Mailbox 0. As soon as HCAN2 finds one, it stops the search and stores the message into the Mailbox. This means that a received message can only be stored in 1 Mailbox. 2. When a message is received and a matching Mailbox is found, the whole message is stored into the Mailbox. This means that, if the LAFM is used, the STD_ID, RTR, IDE, and EXT_ID may differ to the ones originally set as they are updated with the STD_ID, RTR, IDE, and EXT_ID of the received message.
Address H'110 + N*32 Bit 15 Bit Name Description Reserved The write value should always be 0. The read value is not guaranteed.
14 STDID_LAFM Filter Mask [10:0] bits for the CAN Base Identifier [10:0] to 4 10 to 0: Corresponding CAN base ID set in Mailbox 0 is enabled. STDID_LAFM 1: Corresponding CAN base ID set in Mailbox 0 is disabled. 0 3, 2 Reserved The write value should always be 0. The read value is not guaranteed. Filter Mask [17:16] bits for the CAN Extended Identifier [17:16] 0: Corresponding Extended CAN base ID is enabled. 1: Corresponding Extended CAN base ID is disabled.
1 0
EXTID_LAFM 17, EXTID_LAFM 16
H'112 + N*32
15 EXTID_LAFM Filter Mask [15:0] bits for the CAN Extended Identifier [15:0] to 0 15 to 0: Corresponding Extended CAN base ID is enabled. EXTID_LAFM 1: Corresponding Extended CAN base ID is disabled. 0
Rev. 1.0, 02/03, page 769 of 1294
22.5
HCAN2 Control Registers
The HCAN2 has the following registers. For more information on addresses of registers and register states in each processing, refer to section 32, List of Registers. Table 22.4 Register Configuration (1)
Sync Ch. Register Name 0 Master control register General status register Bit configuration register 1 Bit configuration register 0 Interrupt request register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0
Receive data frame pending register 1 Receive data frame pending register 0
Abbrev. CAN0MCR CAN0GSR CAN0BCR1 CAN0BCR0 CAN0IRR CAN0IMR
R/W R/W R R/W R/W R/W R/W
1
P4 Address H'FE38 0000 H'FE38 0002 H'FE38 0004 H'FE38 0006 H'FE38 0008 H'FE38 000A H'FE38 000C H'FE38 0020 H'FE38 0022 H'FE38 0028 H'FE38 002A H'FE38 0030 H'FE38 0032 H'FE38 0038 H'FE38 003A H'FE38 0040 H'FE38 0042 H'FE38 0048
Area 7 Address H'1E38 0000 H'1E38 0002 H'1E38 0004 H'1E38 0006 H'1E38 0008 H'1E38 000A H'1E38 000C H'1E38 0020 H'1E38 0022 H'1E38 0028 H'1E38 002A H'1E38 0030 H'1E38 0032 H'1E38 0038 H'1E38 003A H'1E38 0040 H'1E38 0042 H'1E38 0048
Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
CAN0TECREC R/W* CAN0TXPR1 CAN0TXPR0 CAN0TXCR1 CAN0TXCR0 R/W* R/W* R/W* R/W*
2
2
2
2
CAN0TXACK1 R/W CAN0TXACK0 R/W CAN0ABACK1 R/W CAN0ABACK0 R/W CAN0RXPR1 CAN0RXPR0 CAN0RFPR1 R/W R/W R/W
Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register
CAN0RFPR0
R/W
H'FE38 004A
H'1E38 004A
16
Pck
CAN0MBIMR1 R/W CAN0MBIMR0 R/W CAN0UMSR1 CAN0UMSR0 CAN0TCNTR R/W R/W R/W
H'FE38 0050 H'FE38 0052 H'FE38 0058 H'FE38 005A H'FE38 0080
H'1E38 0050 H'1E38 0052 H'1E38 0058 H'1E38 005A H'1E38 0080
16 16 16 16 16
Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 770 of 1294
Sync Ch. Register Name 0 Timer control register Timer compare match register Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 12 Mailbox 13 Mailbox 14 Mailbox 15 Mailbox 16 Mailbox 17 Mailbox 18 Mailbox 19 Mailbox 20 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Abbrev. CAN0TCR CAN0TCMR CAN0MB0 CAN0MB1 CAN0MB2 CAN0MB3 CAN0MB4 CAN0MB5 CAN0MB6 CAN0MB7 CAN0MB8 CAN0MB9 CAN0MB10 CAN0MB11 CAN0MB12 CAN0MB13 CAN0MB14 CAN0MB15 CAN0MB16 CAN0MB17 CAN0MB18 CAN0MB19 CAN0MB20 CAN0MB21 CAN0MB22 CAN0MB23 CAN0MB24 CAN0MB25 CAN0MB26 CAN0MB27 CAN0MB28 CAN0MB29 CAN0MB30 R/W R/W R/W P4 Address H'FE38 0082 H'FE38 0090 Area 7 Address H'1E38 0082 H'1E38 0090 H'1E38 0100 H'1E38 0120 H'1E38 0140 H'1E38 0160 H'1E38 0180 H'1E38 01A0 H'1E38 01C0 H'1E38 01E0 H'1E38 0200 H'1E38 0220 H'1E38 0240 H'1E38 0260 H'1E38 0280 H'1E38 02A0 H'1E38 02C0 H'1E38 02E0 H'1E38 0300 H'1E38 0320 H'1E38 0340 H'1E38 0360 H'1E38 0380 H'1E38 03A0 H'1E38 03C0 H'1E38 03E0 H'1E39 0400 H'1E38 0420 H'1E38 0440 H'1E38 0460 H'1E38 0480 H'1E38 04A0 H'1E38 04C0 Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
R/W*4*5 H'FE38 0100 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE38 0120 H'FE38 0140 H'FE38 0160 H'FE38 0180 H'FE38 01A0 H'FE38 01C0
45
45
45
45
45
R/W*4*5 H'FE38 01E0 R/W*4*5 H'FE38 0200 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE38 0220 H'FE38 0240 H'FE38 0260 H'FE38 0280 H'FE38 02A0 H'FE38 02C0
45
45
45
45
45
R/W*4*5 H'FE38 02E0 R/W*4*5 H'FE38 0300 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE38 0320 H'FE38 0340 H'FE38 0360 H'FE38 0380 H'FE38 03A0 H'FE38 03C0
45
45
45
45
45
R/W*4*5 H'FE38 03E0 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE38 0400 H'FE38 0420 H'FE38 0440 H'FE38 0460 H'FE38 0480 H'FE38 04A0 H'FE38 04C0
45
45
45
45
45
45
Rev. 1.0, 02/03, page 771 of 1294
Sync Ch. Register Name 0 1 Mailbox 31 Master control register General status register Bit configuration register 1 Bit configuration register 0 Interrupt request register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0
Receive data frame pending register 1 Receive data frame pending register 0
Abbrev. CAN0MB31 CAN1MCR CAN1GSR CAN1BCR1 CAN1BCR0 CAN1IRR CAN1IMR
R/W R/W* * R/W R R/W R/W R/W R/W
1 45
P4 Address H'FE38 04E0 H'FE39 0000 H'FE39 0002 H'FE39 0004 H'FE39 0006 H'FE39 0008 H'FE39 000A H'FE39 000C H'FE39 0020 H'FE39 0022 H'FE39 0028 H'FE39 002A H'FE39 0030 H'FE39 0032 H'FE39 0038 H'FE39 003A H'FE39 0040 H'FE39 0042 H'FE39 0048
Area 7 Address H'1E38 04E0 H'1E39 0000 H'1E39 0002 H'1E39 0004 H'1E39 0006 H'1E39 0008 H'1E39 000A H'1E39 000C H'1E39 0020 H'1E39 0022 H'1E39 0028 H'1E39 002A H'1E39 0030 H'1E39 0032 H'1E39 0038 H'1E39 003A H'1E39 0040 H'1E39 0042 H'1E39 0048
Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
CAN1TECREC R/W* CAN1TXPR1 CAN1TXPR0 CAN1TXCR1 CAN1TXCR0 R/W*
2
R/W*2 R/W* R/W*
2
2
CAN1TXACK1 R/W CAN1TXACK0 R/W CAN1ABACK1 R/W CAN1ABACK0 R/W CAN1RXPR1 CAN1RXPR0 CAN1RFPR1 R/W R/W R/W
Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register Timer control register Timer compare match register Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4
CAN1RFPR0
R/W
H'FE39 004A
H'1E39 004A
16
Pck
CAN1MBIMR1 R/W CAN1MBIMR0 R/W CAN1UMSR1 CAN1UMSR0 CAN1TCNTR CAN1TCR CAN1TCMR CAN1MB0 CAN1MB1 CAN1MB2 CAN1MB3 CAN1MB4 R/W R/W R/W R/W R/W R/W* * R/W* *
45
H'FE39 0050 H'FE39 0052 H'FE39 0058 H'FE39 005A H'FE39 0080 H'FE39 0082 H'FE39 0090 H'FE39 0100 H'FE39 0120
H'1E39 0050 H'1E39 0052 H'1E39 0058 H'1E39 005A H'1E39 0080 H'1E39 0082 H'1E39 0090 H'1E39 0100 H'1E39 0120 H'1E39 0140 H'1E39 0160 H'1E39 0180
16 16 16 16 16 16 16 16 16 16 16 16
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
45
R/W*4*5 H'FE39 0140 R/W* * R/W* *
45
H'FE39 0160 H'FE39 0180
45
Rev. 1.0, 02/03, page 772 of 1294
Sync Ch. Register Name 1 Mailbox 5 Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 12 Mailbox 13 Mailbox 14 Mailbox 15 Mailbox 16 Mailbox 17 Mailbox 18 Mailbox 19 Mailbox 20 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31 Abbrev. CAN1MB5 CAN1MB6 CAN1MB7 CAN1MB8 CAN1MB9 CAN1MB10 CAN1MB11 CAN1MB12 CAN1MB13 CAN1MB14 CAN1MB15 CAN1MB16 CAN1MB17 CAN1MB18 CAN1MB19 CAN1MB20 CAN1MB21 CAN1MB22 CAN1MB23 CAN1MB24 CAN1MB25 CAN1MB26 CAN1MB27 CAN1MB28 CAN1MB29 CAN1MB30 CAN1MB31 R/W R/W* *
45
P4 Address H'FE39 01A0
Area 7 Address H'1E39 01A0 H'1E39 01C0 H'1E39 01E0 H'1E39 0200 H'1E39 0220 H'1E39 0240 H'1E39 0260 H'1E39 0280 H'1E39 02A0 H'1E39 02C0 H'1E39 02E0 H'1E39 0300 H'1E39 0320 H'1E39 0340 H'1E39 0360 H'1E38 0380 H'1E38 03A0 H'1E38 03C0 H'1E38 03E0 H'1E39 0400 H'1E39 0420 H'1E39 0440 H'1E39 0460 H'1E39 0480 H'1E39 04A0 H'1E39 04C0 H'1E39 04E0
Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
R/W*4*5 H'FE39 01C0 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE39 01E0 H'FE39 0200 H'FE39 0220 H'FE39 0240 H'FE39 0260 H'FE39 0280 H'FE39 02A0
45
45
45
45
45
45
R/W*4*5 H'FE39 02C0 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'FE39 02E0 H'FE39 0300 H'FE39 0320 H'FE39 0340 H'FE39 0360 H'FE39 0380 H'1E39 03A0
45
45
45
45
45
45
R/W*4*5 H'1E39 03C0 R/W* * R/W* * R/W* * R/W* * R/W* * R/W* * R/W* *
45
H'1E39 03E0 H'FE39 0400 H'FE39 0420 H'FE39 0440 H'FE39 0460 H'FE39 0480 H'FE39 04A0
45
45
45
45
45
45
R/W*4*5 H'FE39 04C0 R/W* *
45
H'FE39 04E0
Rev. 1.0, 02/03, page 773 of 1294
Table 22.4 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Ch. Register Name 0 Master control register General status register Bit configuration register 1 Bit configuration register 0 Interrupt request register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0
Receive data frame pending register 1 Receive data frame pending register 0
Manual Reset by RESET Pin/WDT/ Multiple Exception H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep by Sleep Instruction/ by
Standby by Software/ Each
Abbrev. CAN0MCR CAN0GSR CAN0BCR1 CAN0BCR0 CAN0IRR CAN0IMR
H-UDI H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
CAN0TECREC H'0000 CAN0TXPR1 CAN0TXPR0 CAN0TXCR1 CAN0TXCR0 H'0000 H'0000 H'0000 H'0000
CAN0TXACK1 H'0000 CAN0TXACK0 H'0000 CAN0ABACK1 H'0000 CAN0ABACK0 H'0000 CAN0RXPR1 CAN0RXPR0 CAN0RFPR1 H'0000 H'0000 H'0000
Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register Timer control register Timer compare match register Mailbox 0 Mailbox 1
CAN0RFPR0
H'0000
H'0000
Retained
Retained
CAN0MBIMR1 H'FFFF CAN0MBIMR0 H'FFFF CAN0UMSR1 CAN0UMSR0 CAN0TCNTR CAN0TCR CAN0TCMR CAN0MB0 CAN0MB1 H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined
H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined
Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 774 of 1294
Power-on Reset by RESET Pin/WDT/ Ch. Register Name 0 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31 1 Master control register General status register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Abbrev. CAN0MB2 CAN0MB3 CAN0MB4 CAN0MB5 CAN0MB6 CAN0MB7 CAN0MB8 CAN0MB9 CAN0MB10 CAN0MB11 CAN0MB21 CAN0MB22 CAN0MB23 CAN0MB24 CAN0MB25 CAN0MB26 CAN0MB27 CAN0MB28 CAN0MB29 CAN0MB30 CAN0MB31 CAN1MCR CAN1GSR CAN1IMR H-UDI Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'0001 H'000C H'FFFF
Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined H'0001 H'000C H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep by Sleep Instruction/ by
Standby by Software/ Each
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
CAN1TECREC H'0000 CAN1TXPR1 CAN1TXPR0 CAN1TXCR1 CAN1TXCR0 H'0000 H'0000 H'0000 H'0000
CAN1TXACK1 H'0000
Rev. 1.0, 02/03, page 775 of 1294
Power-on Reset by RESET Pin/WDT/ Ch. Register Name 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0
Receive data frame pending register 1 Receive data frame pending register 0
Manual Reset by RESET Pin/WDT/ Multiple Exception H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Sleep by Sleep Instruction/ by
Standby by Software/ Each
Abbrev.
H-UDI
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained
CAN1TXACK0 H'0000 CAN1ABACK1 H'0000 CAN1ABACK0 H'0000 CAN1RXPR1 CAN1RXPR0 CAN1RFPR1 H'0000 H'0000 H'0000
Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register Timer control register Timer compare match register Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 12 Mailbox 13
CAN1RFPR0
H'0000
H'0000
Retained
Retained
CAN1MBIMR1 H'FFFF CAN1MBIMR0 H'FFFF CAN1UMSR1 CAN1UMSR0 CAN1TCNTR CAN1TCR CAN1TCMR CAN1MB0 CAN1MB1 CAN1MB2 CAN1MB3 CAN1MB4 CAN1MB5 CAN1MB6 CAN1MB7 CAN1MB8 CAN1MB9 CAN1MB10 CAN1MB11 CAN1MB12 CAN1MB13 H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 776 of 1294
Power-on Reset by RESET Pin/WDT/ Ch. Register Name 1 Mailbox 14 Mailbox 15 Mailbox 16 Mailbox 17 Mailbox 18 Mailbox 19 Mailbox 20 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31 Abbrev. CAN1MB14 CAN1MB15 CAN1MB16 CAN1MB17 CAN1MB18 CAN1MB19 CAN1MB20 CAN1MB21 CAN1MB22 CAN1MB23 CAN1MB24 CAN1MB25 CAN1MB26 CAN1MB27 CAN1MB28 CAN1MB29 CAN1MB30 CAN1MB31 H-UDI Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Manual Reset by RESET Pin/WDT/ Multiple Exception Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Sleep by Sleep Instruction/ by
Standby by Software/ Each
Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Notes: *
After exiting hardware standby mode, this LSI enters the Power-On Reset state by the RESET pin. *1. Can be written to when MCR15 = MCR = 1 (Test Mode). *2. Only allows writing a 1 to the Mailbox designated for transmission. *3. Cannot be modified. *4. The Message Control, Message Data, Timestamp and LAFM fields can only be accessed with 16 bits, whereas the Message Data area can be accessed with 16 bits or 8 bits. Also, unused parts of Mailboxes must be initialized during the configuration to their inactive state as they are configured of RAM. *5. Unused Mailboxes can be used as memory. However, it is important in such case to disable the related mailbox (setting MBC to B'111) in order to avoid that the mailbox joins the search for a matching identifier during the reception of messages, and even store a wrong message in the worst case.
Rev. 1.0, 02/03, page 777 of 1294
22.5.1
Master Control Register (CANMCR)
CANMCR is a 16-bit read/write register that controls HCAN2.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 0 R 5 MCR5 0 R/W 4 0 R 3 0 R 2 1 0 TST7 TST6 TST5 TST4 TST3 TST2 TST1 TST0 MCR7 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W MCR2 MCR1 MCR0 0 R/W 0 R/W 1 R/W
Bit 15
Bit Name TST7
Initial Value 0
R/W R/W
Description Test Mode Enables/disables the Test Modes settable by TST6 to TST0 bits. When this bit is set, the following TST6 to TST0 bits become effective. 0: HCAN2 is in Normal Mode. 1: HCAN2 is in Test Mode.
14
TST6
0
R/W
Write CAN Error Counters Enables the Transmit Error Counter (TEC) and Receive Error Counter (REC) registers to be writable. Only TEC can be directly written to. The same value written into TEC is automatically written into REC. The maximum value that can be written into TEC/REC is D'255 (H'FF). This means that the HCAN2 cannot be forced into the Bus Off state. Before writing into TEC/REC, the HCAN2 needs to be put into Halt Mode. When writing into TEC/REC, the TST7 bit needs be set to 1. 0: TEC and REC is not writable but read-only. 1: TEC and REC is writable with the same value at the same time. Force to Error Passive This bit can force HCAN2 to become Error Passive node, regardless of the Error Counters. 0: State of HCAN2 depends on the Error Counters. 1: HCAN2 behaves as an Error Passive node regardless of the Error Counters.
13
TST5
0
R/W
Rev. 1.0, 02/03, page 778 of 1294
Bit 12
Bit Name TST4
Initial Value 0
R/W R/W
Description Auto Acknowledge Mode Allows HCAN2 to generate its own Acknowledge bit in order to enable Self Test. In order to achieve the Self Test mode, the message transmitted needs to be read back, and there are two settings for this. One is to set [Enable Internal Loop = 1 & Disable Tx Output = 1 & Disable Rx Input = 1], so that the Tx value can be internally provided to the Rx. The other way is to set [Enable Internal Loop = 0 & Disable Tx Output = 0 & Disable Rx Input = 0] and connect the Tx and Rx onto the CAN bus so that the transmitted data can be received via the CAN bus. 0: HCAN2 does not generate its own Acknowledge bit. 1: HCAN2 generates its own Acknowledge bit.
11
TST3
0
R/W
Disable Error Counters Enables/disables the Error Counters (TEC/REC) to be functional. When this bit is disabled (set to 1), the Error Counters (TEC/REC) remain unchanged and hold their current value. When this bit is enabled (cleared to 0), the Error Counters (TEC/REC) function according to the CAN specification. 0: Error Counters (TEC/REC) function according to the CAN specification. 1: Error Counters (TEC/REC) remain unchanged and holds the current value. Disable Rx InputControls the Rx to be supplied into the CAN Interface block. When this bit is enabled (cleared to 0), the Rx pin value is supplied into the CAN Interface block. When this bit is disabled (set to 1), the Rx value for the CAN block always remains recessive or the Tx value internally connected if Enable Internal Loop = 1. 0: External Rx pin value is supplied for the CAN Interface block. 1: Internal Loop Enable = 0: Rx value always remains recessive for the CAN Interface block. Internal Loop Enable = 1: Tx value is internally supplied for the CAN Interface block.
10
TST2
0
R/W
Rev. 1.0, 02/03, page 779 of 1294
Bit 9
Bit Name TST1
Initial Value 0
R/W R/W
Description Disable Tx Output Controls the Tx pin to output transmit data or recessive bits. When this bit is enabled (cleared to 0), the internal transmit output value appears on the Tx pin. When this bit is disabled (set to 1), the Tx Output pin always remains recessive or Tx value is internally looped back the internal Rx if Enable Internal Loop = 1. 0: External Tx pin value is supplied for the CAN Interface block. 1: Internal Loop Enable = 0: Tx is always recessive on the Tx pin. Internal Loop Enable = 1: Tx is internally looped back the internal Rx. Enable Internal Loop Enables/ disables the internal Tx looped back to the internal Rx. For details, refer to 22.6
8
TST0
0
R/W
Operation.
0: Rx is fed from the Rx pin. 1: Rx is fed from the internal Tx signal. 7 MCR7 0 R/W Auto- Wake Mode Enables/disables the Auto wake mode. If this bit is set, HCAN2 automatically cancels the Sleep Mode (MCR5) by detecting CAN bus activity (dominant bit). If MCR7 is cleared HCAN2 does not automatically cancel the Sleep Mode. 0: HCAN2 does not automatically cancel Sleep Mode. 1: HCAN2 automatically cancels Sleep Mode when the CAN bus active is detected. Reserved The write value should always be 0. The read value is not guaranteed.
6
0
R
Rev. 1.0, 02/03, page 780 of 1294
Bit 5
Bit Name MCR5
Initial Value 0
R/W R/W
Description Sleep Mode Enables/disables Sleep mode transition. If this bit is set, the Sleep Mode is enabled. The HCAN2 waits for the completion of the current bus activity before shutting down. Until this mode is terminated HCAN2 will ignore all CAN bus activities. The two Error Counters (TEC and REC) will remain the same values during Sleep mode. Sleep mode will be exited in two ways: * * By writing a 0 to this bit. If MCR7 is enabled after detecting the dominant bit on the CAN bus.
When leaving this mode, the HCAN2 will synchronize to the CAN bus (by checking for 11 recessive bits) before re-initializing. This means that, when the second method above is used, the HCAN2 will miss the first message to receive, however, CAN transceivers have the same feature, and the software needs to be designed in this manner. Important: This mode is same as setting the module to the Halt mode and stopping the clock. This means that, the interrupt is generated from IRR0 when entering the Sleep mode. During the Sleep mode, only the MPI block is accessible, i.e., CANMCR/CANGSR/CANIRR/CANIMR are accessible. However, for example, IRR1 cannot be cleared as it is an OR'ed signal of CANRXPR that cannot be cleared during the Sleep mode, therefore, it is recommended to set the Halt mode first and then transit to the Sleep mode. 0: HCAN2 sleep mode is released. 1: Transition to HCAN2 sleep mode is enabled.
Rev. 1.0, 02/03, page 781 of 1294
Bit 4,3
Bit Name
Initial Value All 0
R/W R
Description Reserved The write value should always be 0. The read value is not guaranteed.
2
MCR2
0
R/W
Message Transmission Priority Selects the order of transmission for pending transmit data. When this bit is set, pending transmit data are sent in order of the bit position in CANTXPR. The order of transmission starts from Mailbox 31 as the highest priority, and then down to Mailbox 1 (if those mailboxes are configured for transmission). If this bit is cleared, all transmit messages are queued with respect to their priority (by running internal arbitration). The highest priority message has the Arbitration Field with the lowest digital value and is transmitted first. The internal arbitration includes the RTR bit and the IDE bit. 0: Transmission order is determined by the message identifier priority. 1: Transmission order is determined by the Mailbox number priority (Mailbox 31 Mailbox 1).
1
MCR1
0
R/W
Halt Request When this bit is set, the CAN controller completes its current operation and then to be cut off the CAN bus. HCAN2 remains in this Halt Mode until this bit is cleared. During the Halt Mode, the CAN Interface does not join the CAN bus activity or does not store messages nor transmit messages. All the registers and Mailbox contents retain. HCAN2 will complete the current operation if it is a transmitter or a receiver, and then enter the Halt Mode. If the CAN bus is in idle or intermission state, HCAN2 will enter the Halt Mode immediately. Entering the Halt Mode is notified by IRR0 and GSR4. In the Halt Mode, HCAN2 configuration can be modified as it does not join the bus activity. This bit has be cleared by writing a 0 to re-join the CAN bus. After this bit is cleared, the CAN Interface waits until it detects 11 recessive bits, and then joins the CAN bus. 0: Normal operating mode 1: Halt Mode transition request.
Rev. 1.0, 02/03, page 782 of 1294
Bit 0
Bit Name MCR0
Initial Value 1
R/W R/W
Description Reset Request Controls resetting of the HCAN2 module. After detecting a Reset request, the HCAN2 controller enters its reset routine, re-initializing the internal logic, and then setting GSR3 and IRR0 to notify the Reset Mode. During the re-initialization, all the registers are cleared. This bit has to be cleared by writing a 0 to join the CAN bus. After this bit is cleared, the HCAN2 module needs to be re-configured, waits until it detects 11 recessive bits, and then joins the CAN bus. After a Power-On Reset, this bit and GSR3 are always set. This means that a Reset request has been made. 0: CAN Interface normal operating mode (MCR0 = 0 and GSR3 = 0) Setting condition: When 0 is written after the HCAN2 Reset. 1: CAN Interface Reset Mode request.
Rev. 1.0, 02/03, page 783 of 1294
22.5.2
General Status Register (CANGSR)
CANGSR is a 16-bit read-only register that indicates the status of the HCAN2.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 4 3 2 1 0
GSR5 GSR4 GSR3 GSR2 GSR1 GSR0 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W
Bit 15 to 6
Bit Name --
Initial Value All 0
R/W --
Description Reserved The write value should always be 0. The read value is not guaranteed. Error Passive Status Indicates that the CAN Interface is Error Passive or not. This bit will be set as soon as the HCAN2 enters the Error Passive state and is cleared when the module returns to the Error Active state (This means that GSR5 will stay high during the Error Passive and Bus Off). Consequently, to find out the accurate state, both GSR5 and GSR0 must be considered. 0: HCAN2 is not Error Passive. Setting condition: HCAN2 is in Error Active state. 1: HCAN is Error Passive (if GSR.0 = 0) Setting condition: TEC 128 or REC 128
5
GSR5
0
R
4
GSR4
0
R
Halt/Sleep Status Indicates whether the CAN Interface is in the Halt/Sleep state or not. 0: HCAN2 is not in the Halt state or Sleep state. 1: HCAN2 is in the Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1). Setting condition: when MCR1 is set and the CAN bus is in intermission or idle state.
3
GSR3
1
R
Reset Status Indicates whether the CAN interface is in the Reset state (Configuration mode) or not. 0: Normal operating state Setting condition: After the HCAN2 internal Reset 1: Reset state (Configuration mode)
Rev. 1.0, 02/03, page 784 of 1294
Bit 2
Bit Name GSR2
Initial Value 1
R/W R
Description Message Transmission Complete Flag Flag that indicates to the host CPU if HCAN2 is processing transmission requests or a transmission is completed. This bit is an OR'ed signal of all the CANTXPR bits. Please note the difference to the meaning of IRR8 (Slot Empty) that is an OR'ed signal of all the CANTXACK/CANABACK bits. 0: Transmission in progress 1: There is no message requested for transmission.
1
GSR1
0
R
Transmit/Receive Warning Flag Flag that indicates an error warning. 0: Clearing condition: TEC < 96 or REC < 96 or TEC 256 1: Setting condition: 96 < TEC < 256 or 96 < REC < 256
0
GSR0
0
R
Bus Off Flag Flag that indicates that the HCAN2 is in the Bus Off state. 0: Clearing condition: Recovery from the Bus Off State 1: Setting condition: TEC 256 (Bus Off state)
Rev. 1.0, 02/03, page 785 of 1294
22.5.3
Bit Configuration Registers 1 and 0 (CANBCR1, CANBCR0)
The CANBCR registers are 16-bit read/write registers that is used to set CAN bit timing parameters and the baud rate pre-scaler for the CAN interface. For the following description, the timequanta is defined as follows:
Timequanta = BRP fclk
Where: BRP (Baud Rate Predivider) is a value stored in CANBCR0 and fclk is the peripheral clock frequency. * CANBCR1
Bit: 15 14 13 12 11 0 R 10 9 8 7 0 R 6 0 R 5 4 3 0 R 2 0 R 1
EG
0
BSP
TSEG1 TSEG1 TSEG1 TSEG1 _3 _2 _1 _0
TSEG2 TSEG2 TSEG2 _2 _1 _0
SJW1 SJW0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 14 13 12
Bit Name TSEG1_3 TSEG1_2 TSEG1_1 TSEG1_0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Time Segment 1 These bits are used to set the segment for absorbing output buffer, CAN bus, and input buffer delay. A value from 4 to 16 can be set. 0000: Setting prohibited 0001: Setting prohibited 0010: Setting prohibited 0011: PRSEG + PHSEG1 = 4 time quanta 0100: PRSEG + PHSEG1 = 5 time quanta : 1111: PRSEG + PHSEG1 = 16 time quanta Reserved The write value should always be 0. The read value is not guaranteed.
11
--
0
--
Rev. 1.0, 02/03, page 786 of 1294
Bit 10 9 8
Bit Name TSEG2_2 TSEG2_1 TSEG2_0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Time Segment 2 These bits are used to set the segment for correcting a 1-bit time error. A value from 2 to 8 time quanta can be set as shown below. 000: Setting prohibited 001: PHSEG2 = 2 time quanta (Conditionally prohibited. See table 22.2.) 010: PHSEG2 = 3 time quanta 011: PHSEG2 = 4 time quanta 100: PHSEG2 = 5 time quanta 101: PHSEG2 = 6 time quanta 110: PHSEG2 = 7 time quanta 111: PHSEG2 = 8 time quanta
7, 6
--
All 0
--
Reserved The write value should always be 0. The read value is not guaranteed. ReSynchronization Jump Width These bits set the synchronization jump width. 00: 01: 10: 11: Synchronization jump width = 1 time quantum Synchronization jump width = 2 time quanta Synchronization jump width = 3 time quanta Synchronization jump width = 4 time quanta
5 4
SJW1 SJW0
0 0
R/W R/W
3, 2
--
All 0
--
Reserved The write value should always be 0. The read value is not guaranteed. Edge Select Selects at which edge is to be used for resynchronization. In order to comply to the standard CAN, this bit should be cleared to 0. 0: Re-synchronization is performed at falling edge of Rx. 1: Re-synchronization is performed at both rising and falling edge of Rx. Bit Sample Point Sets the point at which data is sampled. Threetime sampling is only available when the BRP is programmed to be less than 4. 0: Bit sampling at one point (end of Time Segment 1) 1: Bit sampling at three points (end of Time Segment 1, and 1 time quantum before and after)
1
EG
0
R/W
0
BSP
0
R/W
Rev. 1.0, 02/03, page 787 of 1294
* CANBCR0
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 6 5 4 3 2 1 0 BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 15 to 8
Bit Name --
Initial Value All 0
R/W --
Description Reserved The write value should always be 0. The read value is not guaranteed. Baud Rate Pre-scale These bits are used to set the clock used for the Time Quantum. 00000000: 00000001: 00000010: : 11111111: 1 x System clock 2 x System clock 3 x System clock (BRP+1) x System clock 256 x System clock
7 to 0
BRP7 to BRP0
All 0
R/W
* Bit Timing Settings
1-bit time (8 to 25 quanta)
SYNC_SEG
PRSEG TSEG1
PHSEG1
PHSEG2 TSEG2 2-8 Quantum
1
4-16
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal bit edge transitions occur in this segment.) PRSEG: Segment for compensating for physical delay between networks PHSEG1: Buffer segment for phase drift (positive) (This segment is extended when synchronization (resynchronization) is established.) PHSEG2: Buffer segment for phase drift (negative) (This segment is shortened when synchronization (resynchronization) is established.) The HCAN2 Bit Rate calculation is:
Bit rate = fclk BRP x (TSEG1 + TSEG2 + 1)
where BRP, TSEG1 and TSEG2 are derived values from the descriptions of the tables above, but not the actual programmed values. The "+ 1" is for the SYNC_SEG and fixed to 1 time quantum. fCLK = Pck (peripheral clock (Pck/2 or Pck/3))
Rev. 1.0, 02/03, page 788 of 1294
BCR Setting Constraints TSEG1 > TSEG2 SJW (SJW = 1 to 4) TSEG + TSEG2 + 1 = 8 to 25 time quanta These constraints allow the setting range shown in the table below for TSET1 and TSEG2 in the Bit Configuration Register. Table 22.5 shows the settings of TSEG1 and TSEG2 in CANBCR1. That allow the abovedescribed settings. Table 22.5 TSEG1 and TSEG2 Settings
TSEG2 (Bits 10 to 8 in CANBCR1) 001 2 TSEG1 (Bits 15 to 12 in CANBCR1) 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 5 6 7 8 9 10 11 12 13 14 15 16 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 010 3 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 011 4 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 100 5 No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 101 6 No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 110 7 No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes 111 8 No No No No No Yes Yes Yes Yes Yes Yes Yes Yes
Examples: 1. To have a Bit rate of 1Mbps with a frequency of fclk = 40MHz, it is possible to set: BRP = 4, TSEG1 = 6, TSEG2 = 3. Then the configuration to write is CANBCR1 = 5200 and CANBCR0 = 0003. 2. To have a Bit rate of 500kpbs with a frequency of 35MHz, it is possible to set: BPR = 5, TSEG1 = 8, TSEG2 = 5. Then the configuration to write is CANBCR1 = 7400 and CANBCR0 = 0004.
Rev. 1.0, 02/03, page 789 of 1294
22.5.4
Interrupt Request Register (CANIRR)
CANIRR is a 16-bit read/write-clearable register containing status flags for the various interrupt sources.
Bit: Initial value: R/W: 15 0 R 14 13 12 11 0 R 10 0 R 9 IRR9 0 R/W 8 7 6 IRR6 0 R/W 5 IRR5 0 R/W 4 IRR4 0 R/W 3 IRR3 0 R/W 2 IRR2 0 R 1 IRR1 0 R 0 IRR0 1 R/W
IRR14 IRR13 IRR12 0 R/W 0 R/W 0 R/W
IRR8 IRR7 0 R/W 0 R/W
Bit 15
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always 0. Writing a 0 to this bit has no effect. The read value is not guaranteed. Timer Compare Match Interrupt Indicates that a Compare-Match condition occurred to CANTCMR. When the value set in CANTCMR matches the Timer value (CANTCMR =CANTCNTR) this bit is set. Please note that this bit is not set if the CANTCMR value is H'0000. 0: Timer Compare Match has not occurred for CANTCMR. Clearing condition: Write a 1 to this bit. 1: Timer Compare Match has occurred for CANTCMR. Setting condition: CANTCMR matches to the Timer value (CANCMR = CANTCNTR). Timer Overrun Interrupt Indicates that the Timer has overrun and is reset to 0. Please note that this bit is set even when the CANTCMR is enabled to clear-set the Timer value and its value is set to H'FFFF. 0: Timer has not overrun. Clearing condition: Write a 1 to this bit. 1: Timer has overrun. Setting condition: When the timer (CANTCNTR) changes from H'FFFF to H'0000.
14
IRR14
0
R/W
13
IRR13
0
R/W
Rev. 1.0, 02/03, page 790 of 1294
Bit 12
Bit Name IRR12
Initial Value 0
R/W R/W
Description Wake-up on Bus Activity Indicates that a CAN bus activity is present. When the HCAN is in sleep mode and a recessive to dominant bit transition takes place on the CAN bus, this bit is set. The operation of this interrupt is configured in the Master Control Register. (MCR7 - Auto-wake Mode). This interrupt is cleared by writing a 1 to this bit position. Writing a 0 has no effect. 0: Bus idle state Clearing condition: Write a 1 to this bit. 1: CAN bus activity is detected in HCAN2 sleep mode. Setting condition: Bit transition, from recessive to dominant, is detected in sleep mode.
11
0
R
Reserved This bit is always 0. Writing a 1 to this bit has no effect. This bit is always read as 0. Reserved This bit is always. Writing a 1 to this bit has no effect. This bit is always read as 0. Message Overrun/Overwrite Interrupt Flag Indicates that a message has been received but the existing message in the matching Mailbox has not been read due to the corresponding CANRXPR or CANRFPR set to 1. The received message is either abandoned (overrun) or overwritten depeding on the value of the NMC (New Message Control) bit. This bit is cleared by writing a 1 to the correspondent bit position in CANUMSR (Unread Message Status Register). Writing a 0 has no effect. 0: No message overrun/overwrite Clearing condition: Clean all bits in CANUMSR. 1: Receive message overrun and its storage has been rejected or message overwrite. Setting condition: Message is received while the corresponding CANRXPR or CANRFPR =1 and CANMBIMR = 0.
10
0
R
9
IRR9
0
R/W
Rev. 1.0, 02/03, page 791 of 1294
Bit 8
Bit Name IRR8
Initial Value 0
R/W R/W
Description Mailbox Empty Interrupt Flag Indicates that message transmission or transmission cancellation has been successfully ended, and the Mailbox is now ready to accept a new message data for the next transmission. This bit is set when at least one CANTXPR bit is cleared. This bit is set by an OR'ed signal of the CANTXACK and CANABACK bits, therefore, this bit is automatically cleared when all the CANTXACK and CANABACK bits are cleared. Writing a 0 has no effect. Note that this bit does not indicate that all CANTXPR bits are reset, whereas GSR2 does. 0: Messages set for transmission or transmission cancellation is not in progress. Clearing condition: All the CANTXACK and CANABACK bits are cleared. 1: Message has been transmitted or aborted, and a new message can be stored. Setting condition: One of the CANTXPR bits is cleared by completion of transmission or completion of transmission abort (i.e. in case of CANMBIMR = 0, the CANTXACK or CANABACK bit is set).
7
IRR7
0
R/W
Overload Frame Indicates that the HCAN2 has transmitted an overload frame. It remains latched until reset by writing a 1 to this bit position. Writing a 0 has no effect. 0: Clearing condition: Write a 1 to this bit. 1: Setting condition: Overload frame is transmitted.
Rev. 1.0, 02/03, page 792 of 1294
Bit 6
Bit Name IRR6
Initial Value 0
R/W R/W
Description Bus Off Interrupt Flag This bit is set when the HCAN2 enters the Bus-off state or when the HCAN2 leaves Bus-off state and returns to Error-Active. This is because that the existing condition is that 11 recessive bits x 128 have been received at the node of TEC 256 or at the end of Bus-off. This bit remains latched even though the HCAN2 node leaves the Bus-off condition, and needs to be explicitly cleared by software. The software is expected to read the GSR0 to judge whether HCAN2 has become Busoff or error active, GSR0 should be read. This bit is cleared by writing a 1. Writing a 0 has no effect. 0: Clearing condition: Write a 1 to this bit. 1: Bus off state caused by a transmit error or error active state returned from Bus-off. Setting condition: TEC 256 or the end of busoff after receiving 128 x 11 bits
5
IRR5
0
R/W
Error Passive Interrupt Flag Indicates the Error Passive state caused by the transmit/receive error counter. This bit is cleared by writing a 1, while writing a 0 has no effect. If this bit is cleared, the node may still be error passive. 0: Clearing condition: Write a 1 to this bit. 1: Error passive state is caused by a transmit/receive error. Setting condition: TEC 128 or REC 128
4
IRR4
0
R/W
Receive Overload Warning Interrupt Flag This bit becomes set and latches if the receive error counter (REC) reaches a value greater than 96. This bit is cleared by writing a 1. Writing a 0 has no effect. When the interrupt is cleared, the REC still holds its value greater than 96. 0: Clearing condition: Write a 1 to this bit. 1: Error warning state is caused by a receive error. Setting condition: REC 96
Rev. 1.0, 02/03, page 793 of 1294
Bit 3
Bit Name IRR3
Initial Value 0
R/W R/W
Description Transmit Overload Warning Interrupt Flag This bit becomes set and latches if the transmit error counter (TEC) reaches a value greater than 96. This bit is cleared by writing a 1. Writing a 0 has no effect. When the interrupt is cleared, the TEC still holds a value greater than 96. 0: Clearing condition: Write a 1 to this bit. 1: Error warning state is caused by a transmit error. Setting condition: TEC 96
2
IRR2
0
R
Remote Frame Request Interrupt Flag Indicates that a Remote Frame has been received in a Mailbox. This bit is set if at least one receive mailbox contains a Remote Frame transmission request. This bit is cleared by ensuring all bits in the Remote Request Pending Register (CANRFPR) are cleared. Writing to this bit has no effect. 0: Clearing condition: Clearing all bits in CANRFPR. 1: At least one remote request is pending Setting conditions: When remote frame is received and the corresponding CANMBIMR = 0. Data Frame Received Interrupt Flag Indicates that there is a pending Data Frame received. If this bit is set at least on receive mailbox contains a pending message. This bit is cleared when all bits in the Receive Message Pending Register (CANRXPR) are cleared, i.e. there is no pending message in any receiving mailbox. It is a logical OR from each configured receive mailbox. Writing to this bit has no effect. 0: Clearing condition: Clearing all bits in CANRXPR. 1: Data Frame is received and stored in Mailbox Setting conditions: When data is received and the corresponding CANMBIMR = 0.
1
IRR1
0
R
Rev. 1.0, 02/03, page 794 of 1294
Bit 0
Bit Name IRR0
Initial Value 1
R/W R/W
Description Reset/Halt/Sleep Interrupt Flag Indicates that the CAN Interface has been reset or halted and the HCAN2 is now in Configuration mode or HCAN2 is asleep. An interrupt signal will be generated through this bit to notify the change of the HCAN2's state to the host processor if a MCR0 (Software reset) or MCR1 (Halt) or MCR5 (Sleep) request is made. The GSR may be read after this bit is set to figure out which state HCAN2 is in. Important: When a Sleep mode request needs to be made, the Halt mode should be used beforehand. Refer to the MCR5 description. 0: Clearing condition: Write a 1 to this bit. 1: Transition to Software reset mode, Halt mode, or Sleep mode. Setting condition: When reset/halt processing completed after Software reset (MCR0) or Halt mode (MCR1) or Sleep mode (MCR5) is requested.
22.5.5
Interrupt Mask Register (CANIMR)
CANIMR is a 16-bit register that prevents all interrupts corresponding interrupts in the CANIRR from generating on output signal on the IRQ. An interrupt request is masked if the corresponding bit position is set to 1. This register can be read or written at any time. The CANIMR directly controls the generation of IRQ, but does not prevent the setting of the corresponding bit in the CANIRR.
Bit: Initial value: R/W: 15 1 R 14 13 12 11 1 R 10 1 R 9 8 7 6 5 4 3 2 1 0
IMR14 IMR13 IMR12 1 R/W 1 R/W 1 R/W
IMR9 IMR8 IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 IMR0 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Rev. 1.0, 02/03, page 795 of 1294
Bit 15, 11, 10
Bit Name
Initial Value All 1
R/W R
Description Reserved This bit is always. Writing a 1 to this bit has no effect. This bit is always read as 0. Masks interrupt sources corresponding to IRR14 to IRR12, IRR9 to IRR0. When the bit is set, the interrupt is masked, however, the CANIRR bit setting is retained. 0: Corresponding CANIRR bit is not masked (IRQ is generated for interrupt conditions). 1: Corresponding interrupt of CANIRR bit is masked.
IMR14 to 14 to 12, 9 to IMR12, IMR9 to 0 IMR0
All 1
R/W
22.5.6
Transmit Error Counter and Receive Error Counter (CANTECREC)
CANTECREC is 16 bit read/(write) register and consists of the transmit error counter (TEC) and receive error counter (REC) that function as a counter indicating the number of transmit/receive message errors on the CAN interface. The counter value is stipulated in CAN Specification Version 2.0, Robert Bosch GmbH, 1991 and Implementation Guide for the CAN Protocol, CAN Specification 2.0 Addendum, CAN In Automation, Erlangen, Germany. In the normal mode, this register is read-only and can only be modified by the CAN interface. This register can be cleared by a Reset request (MCR0) or Bus off.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 0 0 0 R/W* R/W* R/W* 0 0 0 0 R/W* R/W* R/W* R/W* 0 0 0 0 R/W* R/W* R/W* R/W* 0 0 0 0 R/W* R/W* R/W* R/W* 0 R/W*
Bit 15 to 8 7 to 0
Bit Name TEC7 to TEC0 REC7 to REC0
Initial Value All 0 All 0
R/W R/W* R/W*
Description Transmit error counter Receive error counter
Note: * It is possible to write the value only in test mode with MCR15 = MCR14 = 1.
Rev. 1.0, 02/03, page 796 of 1294
22.5.7
Transmit Pending Request Registers 1 and 0 (CANTXPR1, CANTXPR0)
The CANTXPR registers are two 16-bit read/conditionally-write registers that contain any transmit pending flags for the CAN module. CANTXPR1 controls Mailboxes 31 to 16, and CANTXPR0 controls Mailboxes 15 to 1. The host CPU may set the CANTXPR bits to affect any message being considered for transmission by writing a 1 to the corresponding bit location. Writing a 0 has no effect. CANTXPR cannot be cleared by writing a 0, but it must be cleared by setting the corresponding CANTXCR bits. CANTXPR may be read by the host CPU to determine which, if any, transmissions are pending. There is a transmit pending bit for all Mailboxes except for the Mailbox 0. Writing a 1 to a bit location when the mailbox is configured to receive will have no effect, and will be automatically cleared when an internal arbitration for transmission runs. The HCAN2 will clear a transmit pending flag after successful transmission of its corresponding or when a transmission abort is normally requested from TXCR. The CANTXPR flag is not cleared if the message is not transmitted due to the CAN node losing the arbitration process or due to errors on the CAN bus, and HCAN2 automatically tries to transmit it again until its DART (Disable Automatic Re-Transmission) bit is set in the Message-Control of the corresponding Mailbox. In such case (DART is set), the transmission is cleared and notified through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit in the Abort Acknowledgement Register (CANABACK). If the status of CANTXPR changes, the HCAN2 shall ensure that in the identifier priority scheme (MCR2 = 0), the highest priority message is always presented for transmission in an intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus. Please refer to 22.6 Operation in details. When the HCAN2 changes state of nay CANTXPR bit position to 0, an empty slot interrupt (IRR8) may be generated. This indicates that either successful or an aborted mailbox transmission has been made. If a message transmission is successful it is signaled in the CANTXACK, and if a message transmission abortion is successful it is signaled in the CANABACK. By checking these registers, the contents of the Message-Data of the corresponding Mailbox may be modified to prepare for the next transmission. * CANTXPR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 TXPR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 797 of 1294
Bit 15 to 0
Bit Name TXPR1[15:0]
Initial Value All 0
R/W R/W*
Description Indicates that the corresponding Mailbox is requested to transmit a CAN Frame. Bit15 to 0 correspond to Mailboxes 31 to 16, respectively. When multiple bits are set, the order of the transmissions is governed by the MCR2 (CAN ID or Mailbox number. 0: Transmit message idle state in corresponding mailbox. Clearing condition: Completion of message transmission or message transmission abortion (automatically cleared) 1: Transmission request made fo corresponding mailbox
Note: * A write of 1 only is allowed to the Mailbox designated for transmission.
* CANTXPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R
TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 TXPR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 1
Bit Name TXPR0[15:1]
Initial Value All 0
R/W R/W*
Description Indicating that the corresponding Mailbox is requested to transmit a CAN Frame. Bits15 to 1 correspond to Mailboxes 15 to 1, respectively. When multiple bits are set, the order of the transmission is governed by the MCR2 (CANID or Mailbox number). 0: Transmit message idle state in corresponding mailbox. Clearing condition: Completion of message transmission or message transmission abortion (automatically cleared) 1: Transmission request for the corresponding Mailbox Reserved This bit is always 0 as this Mailbox is receiveonly. Writing a 0 to this bit has no effect. The read value is not guaranteed.
0
0
R
Note: * A write of 1 only is allowed for the Mailbox designated for transmission.
Rev. 1.0, 02/03, page 798 of 1294
22.5.8
Transmit Cancel Registers 1 and 0 (CANTXCR1, CANTXCR0)
The CANTXCR are two 16-bit read/conditionally-write registers. The CANTXCR1 controls Mailbox 31 to Mailbox 16, and the CANTXCR0 controls Mailbox 15 to Mailbox 1. These registers are used by the microprocessor to request the pending transmission requests in the CANTXPR to be cancelled. To clear the corresponding bit in CANTXPR, the host CPU must write a 1 to the corresponding CANTXCR bit. Writing a 0 has no effect. When an abort has succeeded, the CAN controller clears the corresponding CANTXPR and CANTXCR bits, and sets the corresponding CANABACK bit. However, once a Mailbox has started transmission, the transmission cannot be canceled by this bit. In such case, if the transmission is finishes in success, the CAN controller clears the corresponding CANTXPR and CANTXCR bits, and sets the corresponding CANTXACK bit, however, if the transmission fails due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding CANTXPR and CANTXCR bits, and sets the corresponding CANABACK bit. If an attempt is made by the host CPU to clear Mailbox transmission that is not transmit-pending, it shall have no effect, and will be automatically cleared when an internal arbitration for transmission runs. * CANTXCR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 TXCR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name TXCR1[15:0]
Initial Value All 0
R/W R/W*
Description Requests the corresponding Mailbox that is in the queue for transmission, to cancel its transmission. Bits 15 to 0 correspond to Mailboxes 31 to 16 (and TXPR1[15:0]) respectively. 0: Transmit message cancellation idle state in corresponding mailbox. Clearing condition: Completion of transmit message cancellation (automatically cleared) 1: Transmission cancellation request made for the corresponding Mailbox.
Note: * A write of 1 only is allowed for the Mailbox designated for transmission when it is in the wait state.
Rev. 1.0, 02/03, page 799 of 1294
* CANTXCR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R
TXCR0 TXCR0 TXPR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 TXCR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 1
Bit Name TXCR0[15:1]
Initial Value All 0
R/W R/W*
Description Requests the corresponding Mailbox that is in the queue for transmission, to cancel its transmission. Bits 15 to 1 correspond to Mailboxes 15 to 1 (and TXPR1[15:1]) respectively. 0: Transmit message cancellation idle state in corresponding mailbox. Clearing condition: Completion of transmit message cancellation (automatically cleared) 1: Transmission cancellation request made for the corresponding Mailbox.
0
0
R
Reserved This bit is always 0 as this Mailbox is receiveonly. Writing a 1 to this bit has no effect. This bit is always read as 0.
Note: * A write of 1 only is allowed for the Mailbox designated for transmission when it is in the wait state.
Rev. 1.0, 02/03, page 800 of 1294
22.5.9
Transmit Acknowledge Registers 0 and 1 (CANTXACK1, CANTXACK0)
The CANTXACK are two16-bit read/conditionally-write registers that are used to signal to the CPU that a Mailbox transmission has been successfully made. When transmission has succeeded, the HCAN2 sets the corresponding bit in CANTXACK. The host CPU can clear the CANTXACK bit by writing a 1 to the corresponding bit location. Writing a 0 has no effect. * CANTXACK1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 TXACK1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W*
0 0 R/W* R/W*
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name TXACK1[15:0]
Initial Value All 0
R/W R/W*
Description Notifies that requested transmission of the corresponding Mailbox has been finished successfully. Bits 15 to 0 correspond to Mailboxes 31 to 16 respectively. 0: Clearing condition: Write a 1 to this bit. 1: The corresponding Mailbox has successfully transmitted message (Data or Remote Frame). Setting condition: Completion of message transmission for the corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
Rev. 1.0, 02/03, page 801 of 1294
* CANTXACK0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R
TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 TXACK0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1
Initial value: 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W*
0 0 R/W* R/W*
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
0 0 0 R/W* R/W* R/W*
Bit 15 to 1
Bit Name TXACK0[15:1]
Initial Value All 0
R/W R/W*
Description Notifies that requested transmission of the corresponding Mailbox has been finished successfully. Bits 15 to 1 correspond to Mailboxes 15 to 1 respectively. 0: Clearing condition: Write a 1 to this bit. 1: The corresponding Mailbox has successfully transmitted messages (Data or Remote Frame). Setting condition: Completion of message transmission for the corresponding Mailbox
0
0
R
Reserved This bit is always 0 as this Mailbox is receiveonly. Writing a 1 to this bit has no effect. This bit is always read as 0.
Note: * Only a write of 1 only is allowed to clear the bit.
22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0) The CANABACK registers are two 16-bit read/conditionally-write registers that are used to signal to the CPU that a mailbox transmission has been aborted as per its each request. When an abort has succeeded, the HCAN2 sets the corresponding bit in CANABACK. The host CPU may clear the Abort Acknowledge bit by writing a 1 to the corresponding bit. Writing a 0 has no effect. A CANABACK bits position is set by the HCAN2 to acknowledge that a CANTXPR bit has been cleared by the corresponding CANTXCR bit. * CANABACK1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 ABACK1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W*
0 0 R/W* R/W*
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 802 of 1294
Bit 15 to 0
Bit Name ABACK1[15:0]
Initial Value All 0
R/W R/W*
Description Notifies that requested transmission cancellation requested of the corresponding Mailbox has been performed successfully. Bits 15 to 0 correspond to Mailboxes 31 to 16 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox has cancelled transmission of message (Data or Remote Frame). Setting condition: Completion of transmission cancellation for the corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
* CANABACK0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R
ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 ABACK0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1
Initial value: 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W*
0 0 R/W* R/W*
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
0 0 0 R/W* R/W* R/W*
Bit 15 to 1
Bit Name ABACK0[15:1]
Initial Value All 0
R/W R/W*
Description Notifies that requested transmission cancellation requested of the corresponding Mailbox has been performed successfully. Bits 15 to 1 correspond to Mailboxes 15 to 1 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox has cancelled transmission of message (Data or Remote Frame). Setting condition: Completion of transmission cancellation for the corresponding Mailbox
0
0
R
Reserved This bit is always 0 as this is receive-only. Writing a 1 to this bit has no effect. This bit is always read as 0.
Note: * Only a write of 1 is allowed to clear the bit.
Rev. 1.0, 02/03, page 803 of 1294
22.5.11 Receive Data Frame Pending Registers 1 and 0 (CANRXPR1, CANRXPR0) The CANRXPR are two 16-bit read/conditionally-write registers that contain the receive Data Frame pending flags associated with the configured Receive Mailboxes. When a CAN Data Frame is successfully stored in a receive Mailbox, the corresponding bit is set in CANRXPR. The bit may be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. However, the bit may only be set if the Mailbox is configured by its MBC (Mailbox Configuration) to receive Data Frame. When a CANRXPR bit is set, it also set IRR1 (Data Frame Received Interrupt Flag) if its CANMBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR1 is not set. Please note that those bits are only set by receiving Data Frame and not by receiving Remote Frame. * CANRXPR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 RXPR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name RXPR1[15:0]
Initial Value All 0
R/W R/W*
Description Configurable receive Mailbox locations corresponding to Mailbox position from 31 to 16 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox received a CAN Data Frame. Setting condition: Completion of Data Frame receive on corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
* CANRXPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 RXPR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 804 of 1294
Bit 15 to 0
Bit Name RXPR0[15:0]
Initial Value All 0
R/W R/W*
Description Configurable receive Mailbox locations corresponding to Mailbox position from 15 to 0 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox received a CAN Data Frame. Setting condition: Completion of Data Frame receive on corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
22.5.12 Remote Frame Request Pending Registers 1 and 0 (CANRFPR1, CANRFPR0) The CANRFPR are two 16-bit read/conditionally-write registers that contains the received Remote Frame pending flags associated with the configured Receive Mailboxes. When a CAN Remote Frame is successfully stored in a receive Mailbox, the corresponding bit is set in CANRFPR. The bit may be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. There is a bit position for all mailboxes. However, the bit may only be set if the Mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a CANRFPR bit is set, IRR2 (Remote Frame Request Interrupt Flag) is also set CANMBIMR (Mailbox Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Note that these bits are only set by receiving Remote Frames and not by receiving Data Frames. * CANRFPR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 RFPR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name RFPR1[15:0]
Initial Value All 0
R/W R/W*
Description Remote request pending flags for Mailboxes 31 to 16 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox received Remote Frame. Setting condition: Completion of remote frame reception in the corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
Rev. 1.0, 02/03, page 805 of 1294
* CANRFPR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 RFPR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name RFPR0[15:0]
Initial Value All 0
R/W R/W*
Description Remote request pending flags for Mailboxes 15 to 0 respectively. 0: Clearing condition: Write a 1 to this bit. 1: Corresponding Mailbox received Remote Frame Setting condition: Completion of remote frame reception in the corresponding Mailbox
Note: * Only a write of 1 is allowed to clear the bit.
22.5.13 Mailbox Interrupt Mask Registers 1 and 0 (CANMBIMR1, CANMBIMR0) The CANMBIMR are two 16-bit read/write registers. The CANMBIMR only prevents the setting of IRR related to the Mailbox activities (IRR1: Data Frame Received Interrupt, IRR2: Remote Frame Request Interrupt, IRR8: Mailbox Empty Interrupt, and IRR9: Message Overrun Interrupt). If a Mailbox is configured as receive, a mask at the corresponding bit position prevents the generation of receive interrupts (IRR1 and IRR2 and IRR9) but does not prevents the settings of the corresponding bit in CANRXPR or CANRFPR or CANUMSR. Similarly, when a mailbox has been configured for transmission, a mask prevents the generation of in Interrupt signal and setting of an Mailbox Empty Interrupt due to successful transmission or transmission abortion (IRR8), however, it does not prevent the HCAN2 from clearing the corresponding CANTXPR/CANTXCR bit and setting the CANTXACK bit for abortion of transmission. A mask is set by writing a 1 to the corresponding bit for the Mailbox activity to be masked. At reset, all Mailbox interrupts are masked. * CANMBIMR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 MBIMR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Rev. 1.0, 02/03, page 806 of 1294
Bit 15 to 0
Bit Name MBIMR1[15:0]
Initial Value All 1
R/W R/W
Description Enable or disable interrupt requests from individual Mailboxes 31 to 16 respectively. 0: Interrupt requests from IRR1/IRR2/IRR8/ IRR9 enabled. 1: Interrupt requests from IRR1/IRR2/IRR8/ IRR9 disabled.
* CANMBIMR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 MBIMR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15 to 0
Bit Name MBIMR0[15:0]
Initial Value All 1
R/W R/W
Description Enable or disable interrupt requests from individual Mailboxes 15 to 0 respectively. 0: Interrupt requests from IRR1/IRR2/IRR8/ IRR9 enabled. 1: Interrupt requests from IRR1/IRR2/IRR8/ IRR9 disabled.
22.5.14 Unread Message Status Registers 1 and 0 (CANUMSR1, CANUMSR0) The CANUMSR are two 16-bit read/write registers and record any receive mailboxes that have been emptied prior to a new message received. If the host CPU has not cleared the corresponding bit in CANRXPR or CANRFPR when a new message for that mailbox is received, the corresponding CANUMSR bit is set to 1. This bit may be cleared by writing a 1 to the corresponding bit location in the CANUMSR. Writing a 0 has no effect. If a mailbox is configured as a transmit box, the corresponding CANUMSR bit will not be set. * CANUMSR1
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 UMSR1 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.0, 02/03, page 807 of 1294
Bit 15 to 0
Bit Name UMSR1[15:0]
Initial Value All 0
R/W R/W
Description Indicate that an unread received message has been overwritten for Mailboxes 31 to 16. 0: Clearing condition: Write a 1 to this bit. 1: Unread received message is overwritten by a new message or overrun condition. Setting condition: A new message is received before CANRXPR or CANRFPR is cleared.
* CANUMSR0
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 UMSR0 _15 _14 _13 _12 _11 _10 _9 _8 _7 _6 _5 _4 _3 _2 _1 _0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 to 0
Bit Name UMSR0[15:0]
Initial Value All 0
R/W R/W
Description Indicate that an unread received message has been overwritten for Mailboxes 15 to 0. 0: Clearing condition: Write a 1 to this bit. 1: Unread received message is overwritten by a new message or overrun condition. Setting condition: A new message is received before CANRXPR or CANRFPR is cleared.
22.5.15 Timer Counter Register (CANTCNTR) CANTCNTR is a 16-bit read/write register that allows the CPU to monitor and modify the value of the Free Running Timer Counter. When the Timer rolls over or meets CANTCMR and TCR11 is set to 1, CANTCNTR is set to 0 and starts running again.
* CANTCNTR
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR TCNTR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 R/W: R/W* R/W* R/W* R/W*
0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
0 0 0 0 R/W* R/W* R/W* R/W*
Rev. 1.0, 02/03, page 808 of 1294
Bit 15 to 0
Bit Name TCNTR[15:0]
Initial Value All 0
R/W R/W*
Description Indicates the value of 16 bit Free Running Timer
Note: * The register can be cleared by the Compare Match condition.
22.5.16 Timer Control Register (CANTCR) CANTCR is a 16-bit read/write register and provides functions to control the operation of the Timer.
Bit: Initial value: R/W: 15
TCR15
14 0 R
13
12
11
10 0 R
9 0 R
8 0 R
7 0 R
6 0 R
5
4
3
2
1
0
TCR13 TCR12 TCR11
TPSC5 TPSC4 TPSC3 TPSC2 TPSC1 TPSC0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name TCR15
Initial Value 0
R/W R/W
Description Enable Timer When this bit is set, the timer is running. When this bit is cleared the timer completes the current cycle (notified by Timer overrun or a compare match on CANTCMR) and is cleared to 0. 0: Timer stops running and is cleared at the end of the current cycle. 1: Timer is running.
14
--
0
--
Reserved The write value should always be 0. The read value is not guaranteed. TimeStamp Control for Reception Specifies if the Timestamp in the message control of each Mailbox is recorded at the StartOfFrame (SOF) or EndOfFrame (EOF). 0: Timestamp is recorded at the SOF of every message received. 1: Timestamp is recorded at the EOF of every message received.
13
TCR13
0
R/W
Rev. 1.0, 02/03, page 809 of 1294
Bit 12
Bit Name TCR12
Initial Value 0
R/W R/W
Description TimeStamp Control for Transmission Specifies if the Timestamp of each transmit Mailbox is recorded at the point that the corresponding CANTXPR bit is set or the corresponding CANTXACK is set when a transmission request is made. 0: Timestamp is recorded at the point that the CANTXPR bit is set for message transmission. 1: Timestamp is recorded at the point that the CANTXACK bit is set for message transmission.
11
TCR11
0
R/W
Timer Clear-Set- Control by CANTCMR Specifies if the Timer is to be cleared and set to 0 when CANTCMR matches to CANTCNTR. Please note that the CANTCMR is also capable to generate an interrupt signal to the host CPU via IRR15. 0: Timer is not cleared by CANTCMR. 1: Timer is cleared by CANTCMR.
10-6
--
All 0
--
Reserved The write value should always be 0. The read value cannot be guaranteed. HCAN2 Timer Prescaler This control fields allows the timer source clock (2 x Peripheral clock) to be divided before it is used for the timer. The following relationship exists between the source clock period and timer period: 000000: 1 x Source clock 000001: 2 x Source clock 000010: 4 x Source clock 000011: 6 x Source clock 000100: 8 x Source clock : 111111: 126 x Source clock
5 4 3 2 1 0
TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
0 0 0 0 0 0
R/W R/W -- -- -- --
22.5.17 Timer Compare Match Registers (CANTCMR) The CANTCMR is a 16-bit read/write register capable of generating interrupt signals and clearing/ setting the timer value. If a compare match occurs, an interrupt flag is set to Bit14 in CANIRR and this bit cannot be prevented from being set in CANIRR except when the CANTCMR value is H'0000. Bit14 of
Rev. 1.0, 02/03, page 810 of 1294
CANIMR can prevent the generation of the interrupt signal. When Bit11 of CANTCR is set to 1, a compare match with CANTCMR will clear the timer to 0 (Timer Clear/ Set function).
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR TCMR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 15 to 0
Bit Name TCMR[15:0]
Initial Value 0
R/W R/W*
Description Indicates the value of Free Running Timer.
Note: * This register is cleared by the Compare Match condition.
Rev. 1.0, 02/03, page 811 of 1294
22.6
22.6.1
Operation
Test Mode Settings
The HCAN2 has various test modes. The register TST[7:0] (MCR[15:8]) is used to select the HCAN2 test mode. The default (initialized) settings allow HCAN2 to operate in Normal mode. The following table is examples for test modes.
Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: TST7 TST6 TST5 TST4 TST3 TST2 TST1 0 1 1 1 1 1 0 0 0 0 1 -- 0 0 0 0 0 1 0 0 1 1 -- -- 0 1 -- -- -- -- 0 0 0 1 -- -- 0 1 0 1 -- -- Bit 8: TST0 0 0 0 1 -- -- Description Normal mode (initial value) Listen-Only Mode (Receive-Only Mode) Self Test Mode 1 (External) Self Test Mode 2 (Internal) Error Passive Mode 1 Error Passive Mode 2
* Normal Mode: HCAN2 operates in the normal mode. * Listen-Only Mode: ISO-11898 requires this mode for baud rate detection etc. The Error Counters are disabled so that TEC/REC does not increase the value, and the Tx Output is disabled so that HCAN2 does not generate error frames. * Self Test Mode 1: HCAN2 generates its own Acknowledge bit. The Rx/Tx pin must be connected to the CAN bus. * Self Test Mode 2: HCAN2 generates its own Acknowledge bit. The Rx/Tx pin does not need to be connected to the CAN bus or any external devices, as the internal Tx is looped back to the internal Rx. * Error Passive Mode 1: HCAN2 can be forced to become Error Passive node by writing a value (greater than 127) into the Error Counter (MCR1 must be 1 when writing to the Error Counter). The value written into TEC is written into REC, so only the same value can be set to these registers. Also, HCAN2 needs to be put into Halt Mode when writing into TEC/REC. * Error Passive Mode 2: HCAN2 can be forced to become an Error Passive node by setting the TST5.
Rev. 1.0, 02/03, page 812 of 1294
22.6.2
HCAN2 Settings
* Reset Sequence Following sequence is an example to configure the HCAN2 after Hardware/Software Reset. After reset, all the registers are initialized, therefore, the HCAN2 needs to be configured before joining the CAN bus activity. Read the notes carefully.
Reset sequence Configuration mode Power on/software reset*1 Clear MCR0 GSR3 = 0? Yes No
This takes 23 clocks
Clear all Mailboxes*2 (MSG control,data, time stamp,LAFM)
Set CANBCR[1, 0]*3
Clear IRR0
Clear required CANIMR
HCAN2 is in normal mode Set CANTXPR to start transmission or stay idle for reception
Normal mode Set LAFM Detect 11 recessive bits and join the CAN bus activity
Set CANTCR and CANTCMR
Mailbox settings (STD-ID, EXT-ID, DLC, RTR, IDE, MBC, MBIMR, DART, ATX, NMC, LAFM)
Receive*3
Transmit*3
Timer start*4
Notes: *1 Software reset could be performed at any time by setting MCR0=1. *2 Mailboxes are comprised of RAMs. Therefore, initialize all the mailboxes first even if some of them are not used. *3 If CANTXPR is not set, HCAN2 will receive the next incoming message. If CANTXPR is set, HCAN2 will start transmission of the message and will be arbitrated by the CAN bus. If it loses the arbitration, it will become a receiver. *4 Timer can be started at any time after CANTCR is set.
Figure 22.5 Reset Sequence
Rev. 1.0, 02/03, page 813 of 1294
22.6.3
Message Transmission Sequence
(1) Event Trigger Transmission * Message Transmission Request The following is an example to transmit a CAN frame onto the bus. Note that IRR8 is set when one of the CANTXACK or CANABACK bits is set, meaning one of the Mailbox has completed its transmission or transmission abortion and is now ready to be updated for the next transmission, whereas the GSR3 means that there is currently no transmission request made (CANTXPR = H'0000).
HCAN2 is in normal mode (MBC=H'000 or H'001, TTT=0) Mailbox[ ] is ready to be updated for next transmission
Update message data of Mailbox
Clear CANTXACK [ Yes
]
Write a 1 to CANTXPR at any desired time
CANTXACK [
] set?
No
Yes Internal arbitration in the highest priority? Yes Transmission start No IRR8 set? No
CAN bus arbitration
End of frame
CAN bus
Figure 22.6 Transmission Request
Rev. 1.0, 02/03, page 814 of 1294
* Internal Arbitration for Transmission The following diagram explains how HCAN2 manages to schedule transmission-requested messages in the correct order based on the CAN identifier. `Internal arbitration' picks up the highest priority message among messages transmitted-request messages.
Frame 1 CAN bus Bus idle SOF Message EOF Interm SOF Frame 2 Message Frame 3 EOF Interm SOF Tx arbitration Rx matching for Frame 4
HCAN2 scheduler Scheduler start point TXPR/TXCR/
Tx arbitration for Frame 1
Tx arbitration for Frame 2
Rx matching
Tx arbitration for Frame 3
Error/arbitration -lost set point
1-1
2-1
2-2
3-1
3-2
3-4
3-3
1-1
:If CANTXPR bit is set during the CAN bus idle state, the internal arbitration starts operation and transmission is started. :If one of the five factors described above is generated in this period (during frame 2 Tx arbitration), the internal arbitration is started and the next transmitted frame (frame 2) is scheduled. :The internal arbitration is disabled in this period (during Rx matching). It is scheduled at the SOF of the next frame (frame 2). If the message requested to be transmitted is in the highest priority, transmission is provided in frame 3. :Same as 2-1 , 2-2 .
2-1 , 2-2
3-1 , 3-2
3-3 , 3-4
Interm SOF EOF Message
: Intermission field : Start of frame : End of frame : Arbitration + Control + Data + CRC + ACK
Figure 22.7 Internal Arbitration for Transmission The HCAN2 Scheduler, which runs internal arbitration, has two states, Tx Arbitration State and Rx Matching State. HCAN2 Scheduler is in the Rx Matching State if the CAN bus is in the EOF or Intermission cycle, or otherwise is in the Tx Arbitration State. When a transmission (or transmission abortion) request is made in the Tx Arbitration State, the internal arbitration starts immediately. When a transmission (or transmission abortion) request is made in the Rx Matching State, the internal arbitration waits until the Rx Matching State (i.e. Intermission field) is finished, and then starts running as soon as the HCAN2 scheduler state becomes the `Tx arbitration state'. There are 5 factors that can run internal arbitration, which are: * CANTXPR is set.
Rev. 1.0, 02/03, page 815 of 1294
* CANTXCR is set (not that, if CANTXCR is set for the message currently under transmission, HCAN2 does not stop the transmission but completes. If the message loses the bus arbitration or causes an error on the bus, the HCAN2 will cancel the transmission request.) * Error occurs on the CAN bus. * Message under transmission loses the arbitration on the CAN bus. * Mailbox with the setting of MBC = B'001 receives a Remote Frame. Whenever these factors happen, the internal arbitration starts running to ensure that the highest priority message is always transmitted first. The followings are examples set in the diagram. 1-1 : When a TXPR bit(s) is set while the CAN bus is idle, the internal arbitration starts running immediately and the transmission is started. During this period (Tx Arb for Frame-2), whenever or however many times any of the 4 factors occurs, the internal arbitration starts running and scheduled for the next frame (Frame-2) to be transmitted. During this period (Rx Matching), any internal arbitration is not allowed to run, but scheduled later at the SOF of the next frame (Frame-2). If the transmit-requested message has the highest priority, the transmission will be set for the Frame-3. This is the same case as 2-1,2-2.
2-1, 2-2
:
3-1, 3-2
:
3-3, 3-4
:
Rev. 1.0, 02/03, page 816 of 1294
22.6.4
Message Reception Sequence
The diagram below shows the message receive sequence.
CAN bus End of arbitration Field HCAN2 Idle End of frame
Valid CAN-ID received N=N-1 Loop (N=31(15) ; N > 0 ; N=N-1) Compare ID with Mailbox[N] + LAFM[N] (if MBC is set to receive) No ID matched? No N=0? Yes
Valid CAN frame received
Read IRR1=0
Read RXPR[N]=0
Check MBC/ LAFM/CAN-ID Correct
Incorrect Write a 1 to RXPR[N]
Yes Store mailbox-number[N] and go back to the idle state
RXPR[N] (RFPR[N]) already set? Yes
Read Mailbox[N] No
Read RXPR[N]=1 Overwrite MSG overwrite or overrun? (NMC)
Yes IRR1 set to 1? No
Overrun * Store message by overwriting * Set CANUMSR * Set IRR9 (if MBIMR[N]=0) * Generate interrupt signal (if IMR9=0) interrupt signal * Reject message * Set CANUMSR * Set IRR9 (if MBIMR[N]=0) * Generate interrupt signal (if IMR9=0) interrupt signal * Store message * Set RXPR[N] (RFPR[N]) * Set IRR1 (IRR2) (if MBIMR[N]=0) * Generate interrupt signal (if IMR1(IMR2)=0) interrupt signal
Read IRR
CPU received interrupt
Note: * Please confirm CANUMSR[N] = 0 when NMC[N] = 1
Figure 22.8 Message Receive Sequence
Rev. 1.0, 02/03, page 817 of 1294
When the HCAN2 recognizes the end of Arbitration field while receiving a message, it starts comparing the received identifier to the identifiers set in Mailboxes, starting from Mailbox 31 down to Mailbox 0. It first checks the MBC if it is configured as a receive box, and reads LAFM, and reads the CAN-ID of Mailbox 31 (if configured as receive) to finally compares them to the received ID. If it does not match, the same check takes place at Mailbox 30 (if configured as a receive). Once HCAN2 finds a matching identifier, it stores the number of Mailbox [N] into an internal buffer, stops the search, and gets back to idle state, waiting for an EndOfFrame (EOF) to come. When an EOF is notified by the CAN interface logic, HCAN2 this time only reads the MBC, LAFM and CAN-ID of Mailbox [N] to confirm the matching condition again (i.e., there has been no modification to the configuration of Mailbox [N]). This re-confirmation guarantees the data consistency even when a Mailbox is re-configured during receiving message. If it still matches, then the message is written or abandoned, depending on the NMC bit. If it is written into the corresponding Mailbox, including the CAN-ID, i.e., there is a possibility that the CAN-ID is overwritten by a different CAN-ID of the received message due to the LAFM used. This also implies that, if the identifier of the received message matches the ID + LAFM of 2 or more Mailboxes, the higher numbered Mailbox will always store the relevant messages and the lower numbered Mailbox will never receive messages. Therefore, the settings of the identifiers and LAFMs need to be carefully selected. 22.6.5 Reconfiguration of Mailbox
When re-configuration of Mailboxes is required, the following procedures should be taken. (1) Change ID of transmit box or Change transmit box to receive box Confirm that the corresponding CANTXPR is not set. The identifier and corresponding MBC field can be changed at any time. When both of them need to be changed, please change the identifier first and then the corresponding MBC field. (2) Change ID of receive box or Change receive box to transmit box * Method-1: Using Halt Mode The advantage of this method is that HCAN2 will not lose a message if the message is currently on the CAN bus and the HCAN2 is a receiver. HCAN2 will be in Halt Mode after completing of the reception. The disadvantage is that it might take long if HCAN2 is receiving a message (as the transmission to the halt state is delayed until the end of the reception), and also HCAN2 will not be able to receive/transmit messages during Halt mode.
Rev. 1.0, 02/03, page 818 of 1294
* Method-2: Without Using Halt Mode The advantage of this method is that the re-configuration is done instantly, and the software overhead can be substantially reduced because of no interruption. CANRXPR (CANRFPR) needs to be read before and after the re-configuration is to check if a message is received or not during this period. Please note that CANMBIMR does not prevent the CANRXPR (CANRFPR) bit or the IRR1 from being set but simply prevents the interrupt signal from being generated. If a message is received, it is unknown that the received message is for the previous ID or for the new ID. Therefore, if a message is received a message during this period, it is better to abandon this message, and this is the disadvantage of this method.
Rev. 1.0, 02/03, page 819 of 1294
Method 1 (Halt Mode)
Method 2 (on-the-fly)
HCAN2 is in Normal Mode
HCAN2 is in Normal Mode
Set MCR1 (Halt Mode) End the current session Is HCAN2 transmitter, receiver, or Bus Off? Yes
Set corresponding CANMBIMR bit
Clear CANRXPR Read corrensponding CANRXPR(CANRFPR) bit as 0? Yes Change ID or MBC of mailbox
No
No Generate interrupt (IRR0
Read IRR0 and GSR4 as 1
Read IRR0 and GSR4 as 1
HCAN2 is in Halt Mode
Read Corrensponding RXPR bit 1
0
Change ID or MBC field of mailbox
Clear corresponding RXPR Abandon the received MSG
Clear MCR1
Clear corresponding CANMBIMR bit
HCAN2 is in Normal Mode
HCAN2 is in normal mode and ready for action
Note: The shadowed boxes need to be done by software (host processor)
Figure 22.9 Changing ID of Receive Box or Changing Receive Box to Transmit Box
Rev. 1.0, 02/03, page 820 of 1294
22.6.6
Standby Mode
This HCAN2 supports clock gating to reduce power consumption. The module standby mode can be controlled by CLKSTP00 (bit 12 for channel 0 and bit 13 for channel 1) in the Low Power Consumption Module. To set one of HCAN2 channels to standby mode, the following procedure is required: 1. Set HCAN2 to Halt Mode (MCR1 = 1). 2. Wait for the Halt Mode Interrupt (IRR0). 3. Clear all pending interrupt requests. 4. Disable the requested channel by setting the corresponding bit to 1 in CLKSTP00 register in the Power Control (channel 0 for CSTP12, channel 1 for CSTP13). To wake-up from the Standby mode, the following procedure is required: 1. Enable the requested channel by setting the corresponding bit to 1 in CLKSTPCLR00 register in the Power Control (channel 0 for bit 12, channel 1 for bit 13). 2. Modify HCAN2 configurations, if necessary 3. Release HCAN2 Halt Mode by clearing MCR1. 4. After 11 recessive bits are detected on the CAN bus, the HCAN2 is able to join the communication.
Rev. 1.0, 02/03, page 821 of 1294
Rev. 1.0, 02/03, page 822 of 1294
Section 23 Hitachi Serial Protocol Interface (HSPI)
This LSI incorporates one channel of the Hitachi Serial Protocol Interface (HSPI).
23.1
Features
The HSPI has the following features. * Operating mode: Master mode or Slave mode. * The transmit and receive sections within the module are double buffered to allow duplex communication. * A flexible peripheral clock division strategy allows a wide range of bit rates to be supported. * The programmable clock control logic allows setting for two different transmit protocols and accommodates transmit and receive functions on either edge of the serial bit clock. * Error detection logic is provided for warning of the receive buffer overflow. * The HSPI has a facility to generate the chip select signal to slave modules when configured as a master mode either automatically as part of the data transfer process, or under the manual control of the host processor. * The HSPI supports DMA transfer of both receive and transmit data independently via two DMA channels if implemented in the system.
Rev. 1.0, 02/03, page 823 of 1294
Figure 23.1 is a block diagram of the HSPI.
Bus interface
Register SPCR SPSR SPSCR SPTBR SPRBR System control HSPI_CS
HSPI_RX
LSB
Shift register
MSB
HSPI_TX
Pck
Clock division Serial bit clock generator HSPI_CLK
Polarity selection
Figure 23.1 Block Diagram of HSPI
23.2
Input/Output Pins
The input/output pins of the HSPI is shown in table 23.1. Table 23.1 Pin Configuration
Name Serial bit clock pin Transmit data pin Receive data pin Chip select pin Abbreviation HSPI_CLK HSPI_TX HSPI_RX HSPI_CS I/O Input/Output Output Input Input/Output Function Clock input/output Transmit data output Receive data input Chip select
Rev. 1.0, 02/03, page 824 of 1294
23.3
Register Descriptions
The HSPI has the following registers. For details on addresses of these registers and register status in each processing state, refer to section 32, List of Registers. Table 23.2 Register Configuration (1)
Register Name Control register Status register System control register Transmit buffer register Receive buffer register Abbrev. SPCR SPSR SPSCR SPTBR SPRBR R/W R/W R*
2
P4 Address H'FE18 0000 H'FE18 0004 H'FE18 0008 H'FE18 000C H'FE18 0010
Area 7 Address H'1E18 0000 H'1E18 0004 H'1E18 0008 H'1E18 000C H'1E18 0010
Size 32 32 32 32 32
Sync Clock Pck Pck Pck Pck Pck
R/W R/W R
Table 23.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Register Name Abbrev. H-UDI Manual Reset by RESET Pin/WDT/ Multiple Exception Sleep by Sleep Instruction/ by Software/ Deep Sleep by Hardware Each Module Standby
Control register Status register System control register Transmit buffer register Receive buffer register
SPCR SPSR SPSCR SPTBR SPRBR
H'0000 0000*1 H'0000 0000*1 Retained H'0000 0120*1 H'0000 0120*1 Retained H'0000 0040* H'0000 0040* Retained H'0000 0000* H'0000 0000* Retained H'0000 0000* H'0000 0000* Retained
1 1 1 1 1 1
*
Retained Retained Retained Retained Retained
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. 1. Reserved bits are read as undefined values. 2. To clear the flag, only 0s are written to bits 4 and 3.
Rev. 1.0, 02/03, page 825 of 1294
23.3.1
Control Register (SPCR)
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and specifies the clock polarity and frequency.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 23 R 7
FBS
22 R 6
CLKP
21 R 5
IDIV
20 R 4
19 R 3
18 R 2
17 R 1
16 R 0
CLKC4 CLKC3 CLKC2 CLKC1 CLKC0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 8
Bit Name
Initial Value All
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. First Bit Start Controls the timing relationship between each bit of transferred data and the serial bit clock. 0: The first bit transmitted from the HSPI module is set up such that it can be sampled by the receiving device on the first edge of HSPI_CLK after the HSPI_CS pin goes low. Similarly the first received bit is sampled on the first edge of HSPI_CLK after the HSPI_CS pin goes low. 1: The first bit transmitted from the HSPI module is set up such that it can be sampled by the receiving device on the second edge of HSPI_CLK after the HSPI_CS pin goes low. Similarly the first received bit is sampled on the second edge of HSPI_CLK after the HSPI_CS pin goes low.
7
FBS
0
R/W
6
CLKP
0
R/W
Serial Clock Polarity 0: HSPI_CLK signal is not inverted and so is low when inactive. 1: HSPI_CLK signal is inverted and so is high when inactive.
Rev. 1.0, 02/03, page 826 of 1294
Bit 5
Bit Name IDIV
Initial Value 0
R/W R/W
Description Initial Clock Division Ratio 0: The peripheral clock is divided by a factor of 4 initially to create an intermediate frequency, which is further divided to create the serial bit clock when master mode. 1: The peripheral clock is divided by a factor of 32 initially to create an intermediate frequency, which is further divided to create the serial bit clock when master mode.
4 to 0
CLKC 4 to 0
All 0
R/W
Clock Division Count These bits determine the number of intermediate frequency cycles long both the high and low periods of the serial bit clock. 00000: 1 intermediate frequency cycle. Serial bit clock frequency = Intermediate frequency / 2. 00001: 2 Intermediate frequency cycles. Serial bit clock frequency = Intermediate frequency / 4. 00010: 3 intermediate frequency cycles. Serial bit clock frequency = Intermediate frequency / 6. : 11111: 32 intermediate frequency cycles. Serial bit clock frequency = Intermediate frequency / 64.
The serial bit clock frequency can be computed using the following formula:
Serial bit clock frequency = Pck (Initial clock division x (Clock division count + 1) x 2
When the HSPI is configured as a slave, the IDIV and CLKC bits are ignored and the HSPI synchronizes to the externally supplied serial bit clock. The maximum value of the external serial bit clock that the module can operate with is peripheral clock frequency / 8. If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI will undergo the HSPI software reset.
Rev. 1.0, 02/03, page 827 of 1294
23.3.2
Status Register (SPSR)
SPSR is a 32-bit readable/writable register. The status flag in SPSR can confirm whether the system correctly operates or not. If the ROIE bit in SPSCR is set to 1, an interrupt request is generated due to the occurrence of the receive buffer overrun error or the warning of the receive buffer overrun error. When the TFIE bit in SPSCR is set to 1, an interrupt request is generated by the transmit complete status flag. If the appropriate enable bit in SPSCR is set to 1, an interrupt request is generated due to the receive FIFO halfway, receive FIFO full, transmit FIFO empty, or transmit FIFO halfway flag. If the RNIE bit in SPSCR is set to 1, an interrupt request is generated when the receive FIFO is not empty.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 25 R 9 24 R 8 23 R 7 22 R 6 21 R 5 20 R 4 19 R 3 18 R 2 17 R 1 16 R 0
TXFU TXHA TXEM RXFU RXHA RXEM RXOO RXOW RXFL TXFN TXFL 0 R 0 R 1 R 0 R 0 R 1 R 0 0 R/W* R/W* 0 R 0 R 0 R
Bit
Bit Name
Initial Value All
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. Transmit FIFO Full Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the transmit FIFO is full of bytes for transmission and cannot accept any more. It is cleared to 0 when data is transmitted from the transmit FIFO. Transmit FIFO Halfway Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the transmit FIFO reaches the halfway point, that is, it has 4 bytes of data and 4 spaces for more data. It is cleared to 0 when more data is written to the transmit FIFO. It remains set to 1 until cleared to 0 regardless of the subsequent FIFO levels. If TXHA = 1 and THIE = 1 then the interrupt is generated.
31 to 11
10
TXFU
0
R
9
TXHA
0
R
Rev. 1.0, 02/03, page 828 of 1294
Bit 8
Bit Name TXEM
Initial Value 1
R/W R
Description Transmit FIFO Empty Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the transmit FIFO is empty of data to transmit. It is cleared to 0 when more data is written to the transmit FIFO. If TXEM = 1 and TEIE = 1 then the interrupt is generated. Receive FIFO Full Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the receive FIFO is full of received bytes and cannot accept any more. It is cleared to 0 when data is read out of the receive FIFO. If RXFU = 1 and RFIE = 1 then the interrupt is generated. Receive FIFO Halfway Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the receive FIFO reaches the halfway point, that is, it has 4 bytes of data and 4 spaces for more data. It is cleared to 0 when more data is read from the receive FIFO. It remain set to 1 until cleared to 0 regardless of the subsequent FIFO levels. If RXHA = 1 and RHIE = 1 then the interrupt is generated. Receive FIFO Empty Flag This status flag is enabled only to operation in FIFO mode. The flag is set to 1 when the receive FIFO is empty of received data. It is cleared to 0 when more data is received into to the receive FIFO. If RXEM = 0 and RNIE = 1 then the interrupt is generated. Receive Buffer Overrun Occurred Flag This status flag is set to 1 when new data has been received but the previous received data has not been read from SPRBR. The previously received data will not be overwritten by the newly received data. The RXOO flag remain set to 1 until writing a 0 to its bit position. If RXOO = 1 and ROIE = 1 then the interrupt is generated.
7
RXFU
0
R
6
RXHA
0
R
5
RXEM
1
R
4
RXOO
0
R/W*
Rev. 1.0, 02/03, page 829 of 1294
Bit 3
Bit Name RXOW
Initial Value 0
R/W R/W*
Description Receive Buffer Overrun Warning Flag This status flag is set to 1 when a new serial data transfer starts and the previous received data has not been read from SPRBR. The RXOW remain set to 1 until writing a 0 to its bit position. If RXOW= 1 and ROIE = 1 then the interrupt is generated.
2
RXFL
0
R
Receive Buffer Full Status Flag This status flag indicates that new data is available in the SPRBR and has not yet been read. It is set to 1 at the completion of a serial bus transfer at the point the shift register contents are loaded into the SPRBR. This bit is cleared to 0 by reading SPRBR. If RXFL = 1 and RXDE = 1 then the DMA transfer request enabled. Transmit Complete Status Flag This status flag indicates that the last transmission has completed. It is set to 1 when SPTBR is able to write more data from the peripheral bus. This bit is cleared to 0 by writing more data SPTBR. If TXFN = 1 and TFIE = 1 then the interrupt is generated. Transmit Buffer Full Status Flag This status flag indicates SPTBR has transmitted data. It is set to 1 when SPTBR is written with data from the peripheral bus. This bit is cleared to 0 when SPTBR is able to accept more data from the peripheral bus. If TXFL = 0 (i.e. the SPTBR is empty) and TXDE = 1 then the DMA transfer request enabled.
1
TXFN
0
R
0
TXFL
0
R
Note:* These bits are readable/writable bits. When writing 0, these bits are initialized, while writing 1 is ignored.
Rev. 1.0, 02/03, page 830 of 1294
23.3.3
System Control Register (SPSCR)
SPSCR is a 32-bit readable/writable register that enables or disables interrupts or FIFO mode, selects either LSB first or MSB first in transmitting/receiving date, and master or slave mode. If any of the FFEN, LMSB, CSA or MASL bit values are changed, then the module will undergo the HSPI software reset.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 TEIE 0 R/W 28 R 12 27 R 11 26 R 10 25 R 9 24 R 8 23 R 7 22 R 6 21 R 5 CSA 0 R/W 20 R 4 TFIE 0 R/W 19 R 3 18 R 2 17 R 1 16 R 0
THIE RNIE RHIE RFIE FFEN LMSB CSV 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W
ROIE RXDE TXDE MASL 0 R/W 0 R/W 0 R/W 0 R/W
Bit
Bit Name
Initial Value All
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. Transmit FIFO Empty Interrupt Enable 0:Transmit FIFO empty interrupt disabled 1:Transmit FIFO empty interrupt enabled
31 to 14
13
TEIE
0
R/W
12
THIE
0
R/W
Transmit FIFO Halfway Interrupt Enable 0:Transmit FIFO halfway interrupt disabled 1:Transmit FIFO halfway interrupt enabled
11
RNIE
0
R/W
Receive FIFO Not Empty Interrupt Enable 0: Receive FIFO not empty interrupt disabled 1: Receive FIFO not empty interrupt enabled
10
RHIE
0
R/W
Receive FIFO Halfway Interrupt Enable 0: Receive FIFO halfway interrupt disabled 1: Receive FIFO halfway interrupt enabled
9
RFIE
0
R/W
Receive FIFO Full Interrupt Enable 0: Receive FIFO full interrupt disabled 1: Receive FIFO full interrupt enabled
Rev. 1.0, 02/03, page 831 of 1294
Bit 8
Bit Name FFEN
Initial Value 0
R/W R/W
Description FIFO Mode Enable Enables or disables the FIFO mode. When FIFO mode is enabled two 8-entry deep FIFOs are made available, one for transmit data and one for receive data. These FIFOs are read and written via SPTBR and SPRBR. When FIFO mode is disabled the SPTBR and SPRBR are used directly so new data must be written to SPTBR and read from SPRBR for each and every transfer. FIFO mode must be disabled if DMA requests are also going to be used to service SPTBR and SPRBR. 0: FIFO mode disabled 1: FIFO mode enabled
7
LMSB
0
R/W
LSB/MSB First Control 0: Data is transmitted and received most significant bit (MSB) first. 1: Data is transmitted and received least significant bit (LSB) first.
6
CSV
1
R/W
Chip Select Value Controls the value output from the chip select when the HSPI is a master and the chip select generation has been selected. 0: Chip select output is low. 1: Chip select output is high.
5
CSA
0
R/W
Automatic/Manual Chip Select 0: Chip select output is automatically generated during data transfer. 1: Chip select output is manually controlled, with its value being determined by the CSV bit.
4
TFIE
0
R/W
Transmit Complete Interrupt Enable 0: Transmit complete interrupt disabled 1: Transmit complete interrupt enabled
3
ROIE
0
R/W
Receive Overrun Occurred / Warning Interrupt Enable 0: Receive overrun occurred / warning interrupt disabled 1: Receive overrun occurred / warning interrupt enabled
Rev. 1.0, 02/03, page 832 of 1294
Bit 2
Bit Name RXDE
Initial Value 0
R/W R/W
Description Receive DMA Enable 0: Receive DMA transfer request disabled 1: Receive DMA transfer request enabled
1
TXDE
0
R/W
Transmit DMA Enable 0: Transmit DMA transfer request disabled 1: Transmit DMA transfer request enabled
0
MASL
0
R/W
Master/Slave Select Bit 0: HSPI module configured as a slave 1: HSPI module configured as a master
Rev. 1.0, 02/03, page 833 of 1294
23.3.4
Transmit Buffer Register (SPTBR)
SPTBR is a 32-bit readable/writable register that stores data to be transmitted.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 0 R/W 0 R/W 0 R/W 0 R/W 23 R 7 22 R 6 21 R 5 20 R 4 TD 0 R/W 0 R/W 0 R/W 0 R/W 19 R 3 18 R 2 17 R 1 16 R 0
Bit 31 to 8
Bit Name
Initial Value All
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. Transmit Data Data written to this register is transferred to the shift register for transmission. When reading these bits, always read as data stored in the transmit buffer.
7 to 0
TD
All 0
R/W
Rev. 1.0, 02/03, page 834 of 1294
23.3.5
Receive Buffer Register (SPRBR)
SPRBR is a 32-bit read-only register that stores the number of received data.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R 15 R 30 R 14 R 29 R 13 R 28 R 12 R 27 R 11 R 26 R 10 R 25 R 9 R 24 R 8 R 0 R 0 R 0 R 0 R 23 R 7 22 R 6 21 R 5 20 R 4 RD 0 R 0 R 0 R 0 R 19 R 3 18 R 2 17 R 1 16 R 0
Bit 31 to 8
Bit Name
Initial Value All
R/W R
Description Reserved These bits are always read as an undefined value. The write value should always be 0. Receive Data Data from the shift register, which is stored as each byte, is received, if the previously received data has been read.
7 to 0
RD
All 0
R
Rev. 1.0, 02/03, page 835 of 1294
23.4
23.4.1
Operation
Operation Overview without DMA (FIFO Mode Disabled)
Figure 23.2 shows the flow of a transmit/receive operation procedure.
Start Reset the system
Select master or slave mode by setting the MASL bit in SPSCR Select required interrupts by setting TFIE and ROIE bits in SPSCR
Check if TXBUFF is empty by reading the TXFL bit in SPSR Yes Write data to SPTBR
No
HSPI_TX data to/from slave
Yes
Another transmit required? No End
Figure 23.2 Operational Flowchart Depending on the settings of SPCR, the master transmits data to the slave on either the falling or rising edge of HSPI_CLK and samples data from the slave on the opposite edge. The data transfer between the master and slave completes when the transmit complete status flag (TXFN) in SPSR is set to 1. This flag should be used to identify when an HSPI transfer event (byte transmitted and byte received) has occurred, even in the case where the HSPI module is being used to receive data only (null data being transmitted). By default data is transmitted MSB first, but LSB first is also possible depending on how the LMSB bit in SPSCR is set. During the transmit function the slave responds by sending data to the master synchronized with the HSPI_CLK from the master transmitted. Data from the slave is sampled and transferred to the shift register in the module and on completion of the transmit function, is transferred to SPRBR.
Rev. 1.0, 02/03, page 836 of 1294
The HSPI_CS pin is used to select the HSPI module when the HSPI is configured as a slave, and prepare it to receive data from an external master. When the FBS bit in SPCR is 0, the HSPI_CS pin must be driven high between successive bytes. When the FBS = 1, the HSPI_CS pin can stay low for several byte transmissions. In this case, if the system is configured such that the FBS is always 1, then the HSPI_CS line can be fixed at ground (if the HSPI will only be used as a slave). 23.4.2 Operation Overview with DMA
The operation of the HHSPI when DMA is used to perform transmit and receive data transfers is simpler than when DMA is not used. The HSPI must be configured as in the case for transfers without DMA. FIFO mode must be disabled. The DMA controller (DMAC) should then be configured to transfer the required amount of data. DMA requests can then be enabled in the HSPI module and the transfers will then take place without further processor intervention. When the DMAC indicates that all transfers have ended then the DMA request signals in the HSPI module should be disabled to remove any remaining DMA requests. This is necessary as the HSPI module will always request data to transmit. 23.4.3 Operation with FIFO Mode Enabled
In order to reduce the interrupt overhead on the processor in the case for operation without DMA mode, FIFO mode has been provided. When FIFO mode is enabled, up to 8 bytes can be written in advance for transmission and up to 8 bytes can be received before the receive FIFO needs to be read. To transfer the specified amount of data between the HSPI module and an external device, follow the following procedure: 1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity etc.) and enable FIFO mode. 2. Write bytes into the transmit FIFO via SPTBR. If more than 8 bytes are to be transmitted then enable the transmit FIFO halfway interrupt to keep track of the FIFO level as data is transmitted. 3. Respond to the transmit FIFO halfway interrupt when it occurs by writing more data to the transmit FIFO and reading data from the receive FIFO via SPRBR. 4. When all of the transmit data has been written into the transmit FIFO, disable the transmit FIFO halfway interrupt and read the contents of the receive FIFO until it is empty. Enable the receive FIFO not empty interrupt to keep track of when the final bytes of the transfer are received. 5. Respond to the receive FIFO not empty interrupt until all the expected data has been received. 6. Disable the module until it is required again.
Rev. 1.0, 02/03, page 837 of 1294
In some applications, an undefined amount of data will received from an external HSPI device. If this is the case, follow the following procedure: 1. Set up the module for the required HSPI transfer characteristics (master/slave, clock polarity etc.) and enable FIFO mode. 2. Fill the transmit FIFO with the data to transmit. Enable the receive FIFO not empty interrupt. 3. Respond to the receive FIFO not empty interrupt and read data from the receive FIFO until it is empty. Write more data to the transmit FIFO if required. 4. Disable the module when the transfer is to stop. 23.4.4 Timing Diagrams
The following diagrams explain the timing relationship of all shift and sample processes in the HSPI. Figure 23.3 shows the conditions when FBS = 0, while figure 23.4 shows the conditions when FBS = 1. It can be seen that if CLKP in SPCR is 0 then transmit data is shifted on the falling edge of HSPI_CLK and receive data is sampled on the rising edge. The opposite is true when CLKP = 1.
Data transfer cycle
1
2
3
4
5
6
7
8
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1)
HSPI_TX
MSB
6
5
4
3
2
1
LSB
HSPI_RX HSPI_CS
MSB
6
5
4
3
2
1
LSB
*
Figure 23.3 Timing Conditions when FBS = 0
Rev. 1.0, 02/03, page 838 of 1294
Data transfer cycle
1
2
3
4
5
6
7
8
HSPI_CLK (CLKP = 0)
HSPI_CLK (CLKP = 1) HSPI_TX MSB HSPI_RX * MSB HSPI_CS 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB
Figure 23.4 Timing Conditions when FBS = 1 23.4.5 HSPI Software Reset
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI software reset is generated. The receive and transmit FIFO pointers can be initialized by the HSPI software reset. The data transmission after the HSPI software reset should protect transmitting and receiving protocol of HSPI, and please perform it from the first. A guarantee of operation is not offered other than it. While the master device is not transferring data and the HSPI is in slave mode, respecify the CS bit to make the HSPI_CS pin the low level after the HSPI software reset. 23.4.6 Clock Polarity and Transmit Control
SPCR also allows the user to define the shift timing for transmit data and polarity. The FBS bit in SPCR allows selection between two different transfer formats. The MSB or LSB is valid on the falling edge of HSPI_CS. The CLKP bit in SPCR allows for control of the polarity select block which controls which edges of HSPI_CLK shift and sample data in the master and slave. 23.4.7 Transmit and Receive Routines
The master and slave can be considered linked together as a circular shift register synchronized with HSPI_CLK. The transmit byte from the master is replaced with the receive byte from the slave in eight HSPI_CLK cycles. Both the transmit and receive functions are double buffered to allow for continuous reads and writes. When FIFO mode is enabled eight entry FIFOs are available for both transmit and receive data.
Rev. 1.0, 02/03, page 839 of 1294
23.5
Power Saving and Clocking Strategy
The HSPI operates synchronized with the bus clock. Module standby mode can be enabled or disabled by controlling the CSTP22 bit in the clock stop register (CLKSTP00) in the CPG module. To power down the module, follow the following procedure. 1. Ensure all data transfers have taken place. That is, the transmit buffer (or FIFOs) should be empty and the receive buffer (or FIFOs) should have been read until they are empty. 2. Disable all DMA requests and interrupt requests. Disable FIFO mode. 3. Set the CSTP22 bit in clock stop clear register (CLKSTP00) to 1. To wake up the HSPI, the CSTP22 bit in the clock stop register (CLKSTPCLR00) should be set to 1.
Rev. 1.0, 02/03, page 840 of 1294
Section 24 Pin Function Controller (PFC)
24.1 Features
The PFC has the following features. * Individual control of pull-up of each port pin used by a peripheral module * Individual control of high-impedance (Hi-Z) state of pins used by the SCIF in software standby mode * Applicable modules are selectable by the MFI mode/LCD mode This LSI has ten general ports (A to H, J, and K), which provide 69 input/output pins and one output pin in total. The GPIO (general port for input/output) has the following features. * Each port pin is multiplexed pin, for which the port control register can set the pin function and pull-up MOS control individually. * Each port has a data register that stores data for the pins. * GPIO interrupts are supported. For details of multiplexed pins, refer to table 24.1, Multiplexed Pins Controlled by Port Control Registers. For pin multiplexing in this LSI, refer to table 1.2 and 1.3. By default, each pin of the ports is pulled up. When peripheral modules are used, it is necessary to turn off the pull-up of the pins to be used. Table 24.1 Multiplexed Pins Controlled by Port Control Registers
Pin Name
CAN0_NERR/AUDCK*1 CAN0_RX/AUDATA[2]* CAN0_TX/AUDATA[0]*
1
Port
A A A
1
GPIO
PTA7 input/output PTA6 input/output PTA5 input/output PTA4 input/output PTA3 input/output PTA2 input/output PTB7 input/output PTB6 input/output PTB5 input/output
MFI Mode (MD7=0)
LCD Mode (MD7 = 1)
Register Setting
AUD AUD AUD AUD AUD AUD BS2
HCAN2[0]/AUD HCAN2[0]/AUD HCAN2[0]/AUD HCAN2[1]/AUD HCAN2[1]/AUD HCAN2[1]/AUD SSI[0]/HAC[0] SSI[0]/HAC[0] SSI[0]/HAC[0]
1
CAN1_NERR/AUDSYNC* CAN1_RX/AUDATA[3]*
1
A A A
1 2
CAN1_TX/AUDATA[1]*1
SSI0_SCK/HAC_SD_IN0/BS2* * B SSI0_WS/HAC_SYNC0*
1
B
1
SSI0_SDATA/HAC_SD_OUT0* B
Rev. 1.0, 02/03, page 841 of 1294
Pin Name
CMT_CTR0/TCLK CMT_CTR1 CMT_CTR2 CMT_CTR3 MFI-D0/LCD_DATA0 MFI-D1/LCD_DATA1 MFI-D2/LCD_DATA2/IRQ6* MFI-D3/LCD_DATA3/IRQ7*
2
Port
B B B B C C C C
2
GPIO
PTB4 input/output PTB3 input/output PTB2 input/output PTB1 input/output PTC7 input/output PTC6 input/output PTC5 input/output PTC4 input/output PTC3 input/output PTC2 input/output PTC1 input/output PTC0 input/output PTD7 input/output PTD6 input/output PTD5 input/output PTD4 input/output PTD3 input/output PTD2 input/output PTD1 input/output PTD0 input/output PTE7 input/output PTE6 input/output PTE5 input/output PTE4 input/output PTE3 input/output PTE2 input/output PTE1 input/output PTE0 input/output PTF3 input/output PTF2 input/output PTF1 input/output
MFI Mode (MD7=0)
LCD Mode (MD7 = 1)
CMT CMT CMT CMT
Register Setting
MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI IRQ IRQ
LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC HSPI/MMCIF/SIM HSPI/MMCIF/SIM HSPI/MMCIF/SIM IRQ IRQ DMAC DMAC DMAC DMAC
2
MFI-D4/LCD_DATA4/DREQ2* MFI-D5/LCD_DATA5/DRAK2/ DACK2*2
C C C C D D
MFI-D6/LCD_DATA6/DREQ3*2 MFI-D7/LCD_DATA7/DRAK3/ DACK3*2 MFI-D8/LCD_DATA8*1 MFI-D9/LCD_DATA9*1 MFI-D10/LCD_DATA10* MFI-D11/LCD_DATA11* MFI-D12/LCD_DATA12* MFI-D13/LCD_DATA13* MFI-D14/LCD_DATA14* MFI-D15/LCD_DATA15* MFI-INT/LCD_CLK*
3 1
D D D D D D E E E
1
1
1
1
1
MFI-CS/LCD_DON*3 MFI-E/LCD_CL1*
3
MFI-MD/LCD_CL2*
3
E
3
MFI-RS/LCD_M_DISP* MFI-RW/LCD_FLM* VCPWC/IRQ4 * VEPWC/IRQ5 *
4 3
E E E E
1
4
HSPI_TX/SIM_D/MCDAT* HSPI_RX*1
F F F
HSPI_CLK/SIM_CLK/MCCLK*1
Rev. 1.0, 02/03, page 842 of 1294
Pin Name
HSPI_CS/SIM_RST/MCCMD*1 SCIF0_CLK SCIF0_RXD SCIF0_TXD SCIF1-CLK SCIF1_CTS SCIF1_RTS SCIF1_RXD SCIF1_TXD SCIF2-CLK SCIF2_CTS*3 SCIF2_RTS* SCIF2_RXD SCIF2_TXD UCLK USB_PENC* USB_OVC HAC_BIT_CLK0 HAC_RES SSI1_WS/HAC_SYNC1*
1 3 3
Port
F G G G G G G G G H H H H H H H H J J J J
1
GPIO
PTF0 input/output PTG7 input/output PTG6 input/output PTG5 input/output PTG4 input/output PTG3 input/output PTG2 input/output PTG1 input/output PTG0 input/output PTH7 input/output PTH6 input/output PTH5 input/output PTH4 input/output PTH3 input/output PTH2 input/output PTH1 input/output PTH0 input/output PTJ7 input/output PTJ6 input/output PTJ5 input/output PTJ4 input/output PTJ3 input/output PTJ2 input/output PTJ1 output PTK7 input/output PTK6 input/output PTK5 input/output PTK4 input/output PTK3 input/output PTK2 input/output
MFI Mode (MD7=0)
LCD Mode (MD7 = 1)
Register Setting
HSPI/MMCIF/SIM SCIF[0] SCIF[0] SCIF[0] SCIF[1] SCIF[1] SCIF[1] SCIF[1] SCIF[1] SCIF[2] SCIF[2] SCIF[2] SCIF[2] SCIF[2] USB USB USB HAC[0]/SSI[0] HAC[1][0] HAC[1]/SSI[1] HAC[1]/SSI[1] HAC[1]/SSI[1] HAC[1]/SSI[1] DCK Reserved/AUD Reserved/AUD Reserved/AUD Reserved/AUD Reserved/AUD ADC/AUD AUD AUD AUD AUD AUD AUD
SSI1_SCK/HAC_SD_IN1
SSI1_SDATA/HAC_SD_OUT1* J HAC_BIT_CLK1 DCK Reserved/AUDATA[3] * * Reserved/AUDATA[2] *1 Reserved/AUDATA[1] *1 Reserved/AUDCK *
1 1 3
J J K K K K
1
Reserved/AUDSYNC *
K K
ADTRG/AUDATA[0]*
1
Notes: *1. A module that uses this pin is selected by IPSELR in PFC. *2. A module that uses this pin is selected by MODSELR in PFC. *3. GPIO interrupts are supported.
Rev. 1.0, 02/03, page 843 of 1294
24.2
Register Descriptions
The PFC has the following set of registers. For details of the addresses of these registers and the states in each operating mode, see section 32, List of Registers. Table 24.2 Register Configuration (1)
Register Name Input pin pull-up control register DMA pin control register SCIF Hi-Z control register Peripheral module select register Port A pull-up control register Port B pull-up control register Port C pull-up control register Port D pull-up control register Port E pull-up control register Port F pull-up control register Port G pull-up control register Port H pull-up control register Port J pull-up control register Port K pull-up control register Mode pin pull-up control register Mode select register Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port J control register Port K control register Port A data register Abbrev. INPUPA DMAPCR SCIHZR IPSELR PAPUPR PBPUPR PCPUPR PDPUPR PEPUPR PFPUPR PGPUPR PHPUPR PJPUPR PKPUPR MDPUPR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address H'FE40 0028 H'FE40 002C H'FE40 0030 H'FE40 0034 H'FE40 0080 H'FE40 0084 H'FE40 0088 H'FE40 008C H'FE40 0090 H'FE40 0094 H'FE40 0098 H'FE40 009C H'FE40 00A0 H'FE40 00A4 H'FE40 00A8 H'FE40 00AC H'FE40 0000 H'FE40 0004 H'FE40 0008 H'FE40 000C H'FE40 0010 H'FE40 0014 H'FE40 0018 H'FE40 001C H'FE40 0020 H'FE40 0024 H'FE40 0040 Area 7 Address Size H'1E40 0028 H'1E40 002C H'1E40 0030 H'1E40 0034 H'1E40 0080 H'1E40 0084 H'1E40 0088 H'1E40 008C H'1E40 0090 H'1E40 0094 H'1E40 0098 H'1E40 009C H'1E40 00A0 H'1E40 00A4 H'1E40 00A8 H'1E40 00AC H'1E40 0000 H'1E40 0004 H'1E40 0008 H'1E40 000C H'1E40 0010 H'1E40 0014 H'1E40 0018 H'1E40 001C H'1E40 0020 H'1E40 0024 H'1E40 0040 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 8 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
MODSELR R/W PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PADR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 844 of 1294
Register Name Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register Port K data register GPIO interrupt control register
Abbrev. PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR GPIOIC
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P4 Address H'FE40 0044 H'FE40 0048 H'FE40 004C H'FE40 0050 H'FE40 0054 H'FE40 0058 H'FE40 005C H'FE40 0060 H'FE40 0064 H'FE80 0048
Area 7 Address Size H'1E40 0044 H'1E40 0048 H'1E40 004C H'1E40 0050 H'1E40 0054 H'1E40 0058 H'1E40 005C H'1E40 0060 H'1E40 0064 H'1E80 0048 8 8 8 8 8 8 8 8 8 16
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Bck
Table 24.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'FF00 Manual Reset by RESET Pin/WDT/ Multiple Exception Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Register Name Input pin pull-up control register DMA pin control register SCIF Hi-Z control register Peripheral module select register Port A pull-up control register Port B pull-up control register Port C pull-up control register Port D pull-up control register Port E pull-up control register Port F pull-up control register Port G pull-up control register Port H pull-up control register Port J pull-up control register Port K pull-up control register Mode pin pull-up control register Mode select register
Abbrev. INPUPA
DMAPCR H'A550 SCIHZR IPSELR PAPUPR PBPUPR PCPUPR PDPUPR PEPUPR PFPUPR PGPUPR PHPUPR PJPUPR PKPUPR H'0000 H'0003 H'FC H'FE H'FF H'FF H'FF H'0F H'FF H'FF H'FC H'FC
MDPUPR H'38 MODSELR H'00
Rev. 1.0, 02/03, page 845 of 1294
Register Name Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port J control register Port K control register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register Port K data register GPIO interrupt control register
Abbrev. PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR GPIOIC
Power-on Reset by RESET Pin/WDT/ H-UDI H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'003C H'0000 H'0000 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0000
Standby Manual Reset by by RESET Sleep Software/ by Sleep Pin/WDT/ Each Multiple Instruction/ by Deep Sleep Hardware Module Exception Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
Rev. 1.0, 02/03, page 846 of 1294
24.2.1
Port A Control Register (PACR)
PACR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PA7 MD1 0 R/W 14 PA7 MD0 0 R/W 13 PA6 MD1 0 R/W 12 PA6 MD0 0 R/W 11 PA5 MD1 0 R/W 10 PA5 MD0 0 R/W 9 PA4 MD1 0 R/W 8 PA4 MD0 0 R/W 7 PA3 MD1 0 R/W 6 PA3 MD0 0 R/W 5 PA2 MD1 0 R/W 4 PA2 MD0 0 R/W 3 0 R 2 0 R 1 0 R 0 0 R
Initial value: R/W:
Bit 15 14
Bit Name PA7MD1 PA7MD0
Initial value 0 0
R/W R/W R/W
Description PTA7 Mode 00: Peripheral module (HCAN2[0]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTA6 Mode 00: Peripheral module (HCAN2[0]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTA5 Mode 00: Peripheral module (HCAN2[0]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTA4 Mode 00: Peripheral module (HCAN2[1]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTA3 Mode 00: Peripheral module (HCAN2[1]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTA2 Mode 00: Peripheral module (HCAN2[1]/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PA6MD1 PA6MD0
0 0
R/W R/W
11 10
PA5MD1 PA5MD0
0 0
R/W R/W
9 8
PA4MD1 PA4MD0
0 0
R/W R/W
7 6
PA3MD1 PA3MD0
0 0
R/W R/W
5 4
PA2MD1 PA2MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 847 of 1294
Bit 3 to 0
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
24.2.2
Port B Control Register (PBCR)
PBCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PB7 MD1 0 R/W 14 PB7 MD0 0 R/W 13 PB6 MD1 0 R/W 12 PB6 MD0 0 R/W 11 PB5 MD1 0 R/W 10 PB5 MD0 0 R/W 9 PB4 MD1 0 R/W 8 PB4 MD0 0 R/W 7 PB3 MD1 0 R/W 6 PB3 MD0 0 R/W 5 PB2 MD1 0 R/W 4 PB2 MD0 0 R/W 3 PB1 MD1 0 R/W 2 PB1 MD0 0 R/W 1 0 R 0 0 R
Initial value: R/W:
Bit 15 14
Bit Name PB7MD1 PB7MD0
Initial value 0 0
R/W R/W R/W
Description PTB7 Mode 00: Peripheral module (SSI[0]/HAC[0]/BS2) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTB6 Mode 00: Peripheral module (SSI[0]/HAC[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTB5 Mode 00: Peripheral module (SSI[0]/HAC[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTB4 Mode 00: Peripheral module (CMT) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTB3 Mode 00: Peripheral module (CMT) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PB6MD1 PB6MD0
0 0
R/W R/W
11 10
PB5MD1 PB5MD0
0 0
R/W R/W
9 8
PB4MD1 PB4MD0
0 0
R/W R/W
7 6
PB3MD1 PB3MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 848 of 1294
Bit 5 4
Bit Name PB2MD1 PB2MD0
Initial value 0 0
R/W R/W R/W
Description PTB2 Mode 00: Peripheral module (CMT) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTB1 Mode 00: Peripheral module (CMT) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) Reserved These bits are always read as 0. The write value should always be 0.
3 2
PB1MD1 PB1MD0
0 0
R/W R/W
1, 0
All 0
R
24.2.3
Port C Control Register (PCCR)
PCCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PC7 MD1 1 R/W 14 PC7 MD0 1 R/W 13 PC6 MD1 1 R/W 12 PC6 MD0 1 R/W 11 PC5 MD1 1 R/W 10 PC5 MD0 1 R/W 9 PC4 MD1 1 R/W 8 PC4 MD0 1 R/W 7 PC3 MD1 1 R/W 6 PC3 MD0 1 R/W 5 PC2 MD1 1 R/W 4 PC2 MD0 1 R/W 3 PC1 MD1 1 R/W 2 PC1 MD0 1 R/W 1 PC0 MD1 1 R/W 0 PC0 MD0 1 R/W
Initial value: R/W:
Bit 15 14
Bit Name PC7MD1 PC7MD0
Initial value 1 1
R/W R/W R/W
Description PTC7 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC6 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC5 Mode 00: Peripheral module (MFI/LCDC/IRQ) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PC6MD1 PC6MD0
1 1
R/W R/W
11 10
PC5MD1 PC5MD0
1 1
R/W R/W
Rev. 1.0, 02/03, page 849 of 1294
Bit 9 8
Bit Name PC4MD1 PC4MD0
Initial value 1 1
R/W R/W R/W
Description PTC4 Mode 00: Peripheral module (MFI/LCDC/IRQ) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC3 Mode 00: Peripheral module (MFI/LCDC/DMAC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC2 Mode 00: Peripheral module (MFI/LCDC/DMAC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC1 Mode 00: Peripheral module (MFI/LCDC/DMAC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTC0 Mode 00: Peripheral module (MFI/LCDC/DMAC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
7 6
PC3MD1 PC3MD0
1 1
R/W R/W
5 4
PC2MD1 PC2MD0
1 1
R/W R/W
3 2
PC1MD1 PC1MD0
1 1
R/W R/W
1 0
PC0MD1 PC0MD0
1 1
R/W R/W
24.2.4
Port D Control Register (PDCR)
PDCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PD7 MD1 1 R/W 14 PD7 MD0 1 R/W 13 PD6 MD1 1 R/W 12 PD6 MD0 1 R/W 11 PD5 MD1 1 R/W 10 PD5 MD0 1 R/W 9 PD4 MD1 1 R/W 8 PD4 MD0 1 R/W 7 PD3 MD1 1 R/W 6 PD3 MD0 1 R/W 5 PD2 MD1 1 R/W 4 PD2 MD0 1 R/W 3 PD1 MD1 1 R/W 2 PD1 MD0 1 R/W 1 PD0 MD1 1 R/W 0 PD0 MD0 1 R/W
Initial value: R/W:
Rev. 1.0, 02/03, page 850 of 1294
Bit 15 14
Bit Name PD7MD1 PD7MD0
Initial value 1 1
R/W R/W R/W
Description PTD7 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD6 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD5 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD4 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD3 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD2 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD1 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTD0 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PD6MD1 PD6MD0
1 1
R/W R/W
11 10
PD5MD1 PD5MD0
1 1
R/W R/W
9 8
PD4MD1 PD4MD0
1 1
R/W R/W
7 6
PD3MD1 PD3MD0
1 1
R/W R/W
5 4
PD2MD1 PD2MD0
1 1
R/W R/W
3 2
PD1MD1 PD1MD0
1 1
R/W R/W
1 0
PD0MD1 PD0MD0
1 1
R/W R/W
Rev. 1.0, 02/03, page 851 of 1294
24.2.5
Port E Control Register (PECR)
PECR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PE7 MD1 0 R/W 14 PE7 MD0 0 R/W 13 PE6 MD1 0 R/W 12 PE6 MD0 0 R/W 11 PE5 MD1 0 R/W 10 PE5 MD0 0 R/W 9 PE4 MD1 0 R/W 8 PE4 MD0 0 R/W 7 PE3 MD1 0 R/W 6 PE3 MD0 0 R/W 5 PE2 MD1 0 R/W 4 PE2 MD0 0 R/W 3 PE1 MD1 0 R/W 2 PE1 MD0 0 R/W 1 PE0 MD1 0 R/W 0 PE0 MD0 0 R/W
Initial value: R/W:
Bit 15 14
Bit Name PE7MD1 PE7MD0
Initial value 0 0
R/W R/W R/W
Description PTE7 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE6 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE5 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE4 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE3 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE2 Mode 00: Peripheral module (MFI/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PE6MD1 PE6MD0
0 0
R/W R/W
11 10
PE5MD1 PE5MD0
0 0
R/W R/W
9 8
PE4MD1 PE4MD0
0 0
R/W R/W
7 6
PE3MD1 PE3MD0
0 0
R/W R/W
5 4
PE2MD1 PE2MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 852 of 1294
Bit 3 2
Bit Name PE1MD1 PE1MD0
Initial value 0 0
R/W R/W R/W
Description PTE1 Mode 00: Peripheral module (IRQ/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTE0 Mode 00: Peripheral module (IRQ/LCDC) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
1 0
PE0MD1 PE0MD0
0 0
R/W R/W
24.2.6
Port F Control Register (PFCR)
PFCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 PF3 MD1 0 R/W 6 PF3 MD0 0 R/W 5 PF2 MD1 0 R/W 4 PF2 MD0 0 R/W 3 PF1 MD1 0 R/W 2 PF1 MD0 0 R/W 1 PF0 MD1 0 R/W 0 PF0 MD0 0 R/W
Bit 15 to 8
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 6
PF3MD1 PF3MD0
0 0
R/W R/W
PTF3 Mode 00: Peripheral module (HSPI/MMCIF/SIM) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTF2 Mode 00: Peripheral module (HSPI/MMCIF/SIM) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTF1 Mode 00: Peripheral module (HSPI/MMCIF/SIM) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
5 4
PF2MD1 PF2MD0
0 0
R/W R/W
3 2
PF1MD1 PF1MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 853 of 1294
Bit 1 0
Bit Name PF0MD1 PF0MD0
Initial value 0 0
R/W R/W R/W
Description PTF0 Mode 00: Peripheral module (HSPI/MMCIF/SIM) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
24.2.7
Port G Control Register (PGCR)
PGCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PG7 MD1 0 R/W 14 PG7 MD0 0 R/W 13 PG6 MD1 0 R/W 12 PG6 MD0 0 R/W 11 PG5 MD1 0 R/W 10 PG5 MD0 0 R/W 9 PG4 MD1 0 R/W 8 PG4 MD0 0 R/W 7 PG3 MD1 0 R/W 6 PG3 MD0 0 R/W 5 PG2 MD1 0 R/W 4 PG2 MD0 0 R/W 3 PG1 MD1 0 R/W 2 PG1 MD0 0 R/W 1 PG0 MD1 0 R/W 0 PG0 MD0 0 R/W
Initial value: R/W:
Bit 15 14
Bit Name PG7MD1 PG7MD0
Initial value 0 0
R/W R/W R/W
Description PTG7 Mode 00: Peripheral module (SCIF[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG6 Mode 00: Peripheral module (SCIF[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG5 Mode 00: Peripheral module (SCIF[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG4 Mode 00: Peripheral module (SCIF[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PG6MD1 PG6MD0
0 0
R/W R/W
11 10
PG5MD1 PG5MD0
0 0
R/W R/W
9 8
PG4MD1 PG4MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 854 of 1294
Bit 7 6
Bit Name PG3MD1 PG3MD0
Initial value 0 0
R/W R/W R/W
Description PTG3 Mode 00: Peripheral module (SCIF[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG2 Mode 00: Peripheral module (SCIF[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG1 Mode 00: Peripheral module (SCIF[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTG0 Mode 00: Peripheral module (SCIF[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
5 4
PG2MD1 PG2MD0
0 0
R/W R/W
3 2
PG1MD1 PG1MD0
0 0
R/W R/W
1 0
PG0MD1 PG0MD0
0 0
R/W R/W
24.2.8
Port H Control Register (PHCR)
PHCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PH7 MD1 0 R/W 14 PH7 MD0 0 R/W 13 PH6 MD1 0 R/W 12 PH6 MD0 0 R/W 11 PH5 MD1 0 R/W 10 PH5 MD0 0 R/W 9 PH4 MD1 0 R/W 8 PH4 MD0 0 R/W 7 PH3 MD1 0 R/W 6 PH3 MD0 0 R/W 5 PH2 MD1 1 R/W 4 PH2 MD0 1 R/W 3 PH1 MD1 1 R/W 2 PH1 MD0 1 R/W 1 PH0 MD1 0 R/W 0 PH0 MD0 0 R/W
Initial value: R/W:
Bit 15 14
Bit Name PH7MD1 PH7MD0
Initial value 0 0
R/W R/W R/W
Description PTH7 Mode 00: Peripheral module (SCIF[2]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
Rev. 1.0, 02/03, page 855 of 1294
Bit 13 12
Bit Name PH6MD1 PH6MD0
Initial value 0 0
R/W R/W R/W
Description PTH6 Mode 00: Peripheral module (SCIF[2]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH5 Mode 00: Peripheral module (SCIF[2]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH4 Mode 00: Peripheral module (SCIF[2]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH3 Mode 00: Peripheral module (SCIF[2]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH2 Mode 00: Peripheral module (USB) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH1 Mode 00: Peripheral module (USB) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTH0 Mode 00: Peripheral module (USB) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
11 10
PH5MD1 PH5MD0
0 0
R/W R/W
9 8
PH4MD1 PH4MD0
0 0
R/W R/W
7 6
PH3MD1 PH3MD0
0 0
R/W R/W
5 4
PH2MD1 PH2MD0
1 1
R/W R/W
3 2
PH1MD1 PH1MD0
1 1
R/W R/W
1 0
PH0MD1 PH0MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 856 of 1294
24.2.9
Port J Control Register (PJCR)
PJCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PJ7 MD1 0 R/W 14 PJ7 MD0 0 R/W 13 PJ6 MD1 0 R/W 12 PJ6 MD0 0 R/W 11 PJ5 MD1 0 R/W 10 PJ5 MD0 0 R/W 9 PJ4 MD1 0 R/W 8 PJ4 MD0 0 R/W 7 PJ3 MD1 0 R/W 6 PJ3 MD0 0 R/W 5 PJ2 MD1 0 R/W 4 PJ2 MD0 0 R/W 3 PJ1 MD1 0 R/W 2 PJ1 MD0 0 R/W 1 0 R 0 0 R
Initial value: R/W:
Bit 15 14
Bit Name PJ7MD1 PJ7MD0
Initial value 0 0
R/W R/W R/W
Description PTJ7 Mode 00: Peripheral module (HAC[0]/SSI[0]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTJ6 Mode 00: Peripheral module (HAC[0][1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTJ5 Mode 00: Peripheral module (SSI[1]/HAC[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTJ4 Mode* 00: Peripheral module (SSI[1]/HAC[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTJ3 Mode* 00: Peripheral module (SSI[1]/HAC[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTJ2 Mode 00: Peripheral module (HAC[1]/SSI[1]) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PJ6MD1 PJ6MD0
0 0
R/W R/W
11 10
PJ5MD1 PJ5MD0
0 0
R/W R/W
9 8
PJ4MD1 PJ4MD0
0 0
R/W R/W
7 6
PJ3MD1 PJ3MD0
0 0
R/W R/W
5 4
PJ2MD1 PJ2MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 857 of 1294
Bit 3 2
Bit Name PJ1MD1 PJ1MD0
Initial value 0 0
R/W R/W R/W
Description PTJ1 Mode 00: Peripheral module (DCK) 01: Port output Other than above: Setting prohibited Reserved These bits are always read as 0, and the write value should always be 0.
1, 0
All 0
R
Note: *The following settings are prohibited: the combination of port3 set to output and port 4 to input or port3 to input and port4 to output.
24.2.10 Port K Control Register (PKCR) PKCR is a 16-bit readable/writable register that selects the pin function and input pull-up MOS control.
Bit: 15 PK7 MD1 0 R/W 14 PK7 MD0 0 R/W 13 PK6 MD1 0 R/W 12 PK6 MD0 0 R/W 11 PK5 MD1 0 R/W 10 PK5 MD0 0 R/W 9 PK4 MD1 0 R/W 8 PK4 MD0 0 R/W 7 PK3 MD1 0 R/W 6 PK3 MD0 0 R/W 5 PK2 MD1 0 R/W 4 PK2 MD0 0 R/W 3 0 R 2 0 R 1 0 R 0 0 R
Initial value: R/W:
Bit 15 14
Bit Name PK7MD1 PK7MD0
Initial value 0 0
R/W R/W R/W
Description PTK7 Mode 00: Peripheral module (Reserved/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTK6 Mode 00: Peripheral module (Reserved/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTK5 Mode 00: Peripheral module (Reserved/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On)
13 12
PK6MD1 PK6MD0
0 0
R/W R/W
11 10
PK5MD1 PK5MD0
0 0
R/W R/W
Rev. 1.0, 02/03, page 858 of 1294
Bit 9 8
Bit Name PK4MD1 PK4MD0
Initial value 0 0
R/W R/W R/W
Description PTK4 Mode 00: Peripheral module (Reserved/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTK3 Mode 00: Peripheral module (Reserved/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) PTK2 Mode 00: Peripheral module (ADC/AUD) 01: Port output 10: Port input (pull-up MOS: Off) 11: Port input (pull-up MOS: On) Reserved These bits are always read as 0, and the write value should always be 0.
7 6
PK3MD1 PK3MD0
0 0
R/W R/W
5 4
PK2MD1 PK2MD0
0 0
R/W R/W
3 to 0
All 0
R
24.2.11 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores port A data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 R 0 0 R
PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1, 0
Bit Name PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT
Initial value 0 0 0 0 0 0 All 0
R/W R/W R/W R/W R/W R/W R/W R
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out. Reserved These bits are always read as 0, and the write value should always be 0.
Rev. 1.0, 02/03, page 859 of 1294
24.2.12 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores port B data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 0 R
PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
Reserved This bit is always read as 0, and the write value should always be 0.
Rev. 1.0, 02/03, page 860 of 1294
24.2.13 Port C Data Register (PCDR) PCDR is an 8-bit readable/writable register that stores port C data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
24.2.14 Port D Data Register (PDDR) PDDR is an 8-bit readable/writable register that stores port D data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
Rev. 1.0, 02/03, page 861 of 1294
24.2.15 Port E Data Register (PEDR) PEDR is an 8-bit readable/writable register that stores port E data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
24.2.16 Port F Data Register (PFDR) PFDR is an 8-bit readable/writable register that stores port F data.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 2 1 0
PF3DT PF2DT PF1DT PF0DT
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 to 4
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
3 2 1 0
PF3DT PF2DT PF1DT PF0DT
0 0 0 0
R/W R/W R/W R/W
These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
Rev. 1.0, 02/03, page 862 of 1294
24.2.17 Port G Data Register (PGDR) PGDR is an 8-bit readable/writable register that stores port G data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
24.2.18 Port H Data Register (PHDR) PHDR is an 8-bit readable/writable register that stores port H data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT
Initial value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
Rev. 1.0, 02/03, page 863 of 1294
24.2.19 Port J Data Register (PJDR) PJDR is an 8-bit readable/writable register that stores port J data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 0 R
PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2 1
Bit Name PJ7DT PJ6DT PJ5DT PJ4DT PJ3DT PJ2DT PJ1DT
Initial value 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the value of this corresponding register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out. However, Bit 1 is exclusively used as an output port. Note: When port3 and port4 function as general input ports, the state of port3 is read from the PJ4DT bit and the state of port4 is read from the PJ3DT bit. Reserved This bit is always read as 0, and the write value should always be 0.
0
0
R
24.2.20 Port K Data Register (PKDR) PKDR is an 8-bit readable/writable register that stores port K data.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 R 0 0 R
PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7 6 5 4 3 2
Bit Name PK7DT PK6DT PK5DT PK4DT PK3DT PK2DT
Initial value 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
Description These bits store output data of a pin which is used as a general output port. When the pin functions as a general output port, if the port is read, the corresponding value of this register will be read out. When the pin functions as a general input port, if the port is read, the status of the corresponding pin will be read out.
Rev. 1.0, 02/03, page 864 of 1294
Bit 1, 0
Bit Name
Initial value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
24.2.21 GPIO Interrupt Control Register (GPIOIC) GPIOIC is a 16-bit readable/writable register that controls interrupt inputs. When an IRQ or IRL interrupt is used to cancel software standby mode, the standby cancellation IRL enable bit (STBIRLEN), described in section 10.5.2 Bus Control Register 2 (BCR2), should be set to 1.
15 14 13 12 11 10 9 PTIR PTIR PTIR PTIR PTIR PTIR PTIR EN15 EN14 EN13 EN12 EN11 EN10 EN9 Initial value: 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W Bit: 8 STB RT8 0 R/W 7 STB RT7 0 R/W 6 STB RT6 0 R/W 5 4 STB STB IRQ5 IRQ4 0 0 R/W R/W 3 STB IRL3 0 R/W 2 STB IRL2 0 R/W 1 STB IRL1 0 R/W 0 STB IRL0 0 R/W
Bit 15 14 13 12 11 10 9 8 7 6
Bit Name PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 STBRT8 STBRT7 STBRT6
Initial value 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Port Interrupt Enable The setting whether to use the port as a GPIO interrupt can be set for each bit. 0: Uses the port as a normal I/O port 1: Uses the port as a GPIO interrupt
Standby Cancellation Setting Bit In standby mode, if an interrupt to return from standby mode is detected while the corresponding STBRT bit is set to 1, the standby mode is cancelled. 0: Disables canceling standby mode by detection of an interrupt 1: Enables canceling standby mode by detection of an interrupt
5 4
STBIRQ5 STBIRQ4
0 0
R/W R/W
Standby Cancellation IRQ Setting Bit In standby mode, if an IRQ interrupt (IRQ is in the low level) is detected while the corresponding STBIRQ bit is set to 1, the standby mode is cancelled. 0: Disables canceling standby mode by detection of an IRQ interrupt 1: Enables canceling standby mode by detection of an IRQ interrupt
Rev. 1.0, 02/03, page 865 of 1294
Bit 3 2 1 0
Bit Name STBIRL3 STBIRL2 STBIRL1 STBIRL0
Initial value 0 0 0 0
R/W R/W R/W R/W R/W
Description Standby Cancellation IRL Setting Bit In standby mode, if an IRL interrupt (IRL is in the low level) is detected while the corresponding STBIRL bit is set to 1, the standby mode is cancelled. 0: Disables canceling standby mode by detection of an IRL interrupt 1: Enables canceling standby mode by detection of an IRL interrupt
The following table shows the relationship between the GPIOIC bits and the corresponding pins to which interrupts are generated.
Bit Name PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 STBRT8 STBRT7 STBRT6 STBIRQ5 STBIRQ4 STBIRL3 STBIRL2 STBIRL1 STBIRL0 Pin T2 T1 R2 R1 P2 P1 A13 A14 C18 J20 E2 E1 M19 M20 N19 N20 Pin Name MFI-RW/LCD_FLM MFI-RS/LCD_M_DISP MFI-MD/LCD_CL2 MFI-E/LCD_CL1 MFI-CS/LCD_DON MFI-INT/LCD_CLK SCIF2_CTS SCIF2_RTS USB_PENC FCE/AUDATA[3] VEPWC/IRQ5 VCPWC/IRQ4 IRL3 IRL2 IRL1 IRL0 Port PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 PTH6 PTH5 PTH1 PTK7 PTE0 PTE1
When a port pin is used for a GPIO interrupt source, it must be specified for an input pin through the corresponding port control register. The GPIO interrupt is a low-active level-sensed interrupt. After a GPIO interrupt is accepted, the GPIO pin level must be retained until the interrupt processing starts. The values of the bits specified as GPIO interrupt sources are ORed to detect an interrupt. The bit that has received an interrupt can be checked by reading the port control registers. The interrupt source code for the port pins is H'600, except for the IRL and IRQ pins. For the
Rev. 1.0, 02/03, page 866 of 1294
interrupt source codes for the IRL and IRQ pins and the priority level of the GPIO interrupt, refer to section 9, Interrupt Controller (INTC). 24.2.22 Port A Pull-Up Control Register (PAPUPR) PAPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTA7 to PTA2 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PACR, the settings in this register will be invalid.
Bit: 7 6 5 4 3 2 1 0 R 0 0 R
PA7 PA6 PA5 PA4 PA3 PA2 PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2
Bit Name PA7PUPR PA6PUPR PA5PUPR PA4PUPR PA3PUPR PA2PUPR
Initial Value 1 1 1 1 1 1 All 0
R/W R/W R/W R/W R/W R/W R/W R
Description Sets individual pull-up control for given pins of Port A 0: PTAn pull-up off 1: PTAn pull-up on
1, 0 --
Reserved These bits are always read as 0, and the write value should always be 0.
n = 7 to 2
24.2.23 Port B Pull-Up Control Register (PBPUPR) PBPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTB7 to PTB1 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PBCR, the settings in this register will be invalid.
Bit: 7 6 5 4 3 2 1 0 0 R
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 867 of 1294
Bit 7 6 5 4 3 2 1 0
Bit Name PB7PUPR PB6PUPR PB5PUPR PB4PUPR PB3PUPR PB2PUPR PB1PUPR --
Initial Value 1 1 1 1 1 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R
Description Sets individual pull-up control for pins of Port B 0: PTBn pull-up off 1: PTBn pull-up on
Reserved This bit is always read as 0, and the write value should always be 0.
n = 7 to 1
24.2.24 Port C Pull-Up Control Register (PCPUPR) PCPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTC7 to PTC0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PCCR, the settings in this register will be invalid.
7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PUPR PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 7 6 5 4 3 2 1 0
Bit Name PC7PUPR PC6PUPR PC5PUPR PC4PUPR PC3PUPR PC2PUPR PC1PUPR PC0PUPR
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Sets individual pull-up control for each pin of Port C 0: PTCn pull-up off 1: PTCn pull-up on
n = 7 to 0
Rev. 1.0, 02/03, page 868 of 1294
24.2.25 Port D Pull-Up Control Register (PDPUPR) PDPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTD7 to PTD0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PDCR, the settings in this register will be invalid.
7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PUPR PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 7 6 5 4 3 2 1 0
Bit Name PD7PUPR PD6PUPR PD5PUPR PD4PUPR PD3PUPR PD2PUPR PD1PUPR PD0PUPR
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Sets individual pull-up control for each pin of Port D 0: PTDn pull-up off 1: PTDn pull-up on
n = 7 to 0
24.2.26 Port E Pull-Up Control Register (PEPUPR) PEPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTE7 to PTE0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PECR, the settings in this register will be invalid.
7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PUPR PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Rev. 1.0, 02/03, page 869 of 1294
Bit 7 6 5 4 3 2 1 0
Bit Name PE7PUPR PE6PUPR PE5PUPR PE4PUPR PE3PUPR PE2PUPR PE1PUPR PE0PUPR
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Sets individual pull-up control for each pin of Port E 0: PTEn pull-up off 1: PTEn pull-up on
n = 7 to 0
24.2.27 Port F Pull-Up Control Register (PFPUPR) PFPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTF3 to PTF0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PFCR, the settings in this register will be invalid.
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 0 R 4 0 R 3 2 1 0 PF3 PF2 PF1 PF0 PUPR PUPR PUPR PUPR 1 1 1 1 R/W R/W R/W R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0, and the write value should always be 0.
7 to 4 --
3 2 1 0
PF3PUPR PF2PUPR PF1PUPR PF0PUPR
1 1 1 1
R/W R/W R/W R/W
Sets individual pull-up control of each pin of Port F 0: PTFn pull-up off 1: PTFn pull-up on
n = 3 to 0
Rev. 1.0, 02/03, page 870 of 1294
24.2.28 Port G Pull-Up Control Register (PGPUPR) PGPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTG7 to PTG0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PGCR, the settings in this register will be invalid.
7 6 5 4 3 2 1 0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PUPR PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Bit 7 6 5 4 3 2 1 0
Bit Name PG7PUPR PG6PUPR PG5PUPR PG4PUPR PG3PUPR PG2PUPR PG1PUPR PG0PUPR
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Sets individual pull-up control for each pin of Port G 0: PTGn pull-up off 1: PTGn pull-up on
n = 7 to 0
24.2.29 Port H Pull-Up Control Register (PHPUPR) PHPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTH7 to PTH0 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PHCR, the settings in this register will be invalid.
7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PUPR PUPR PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W R/W R/W Bit:
Rev. 1.0, 02/03, page 871 of 1294
Bit 7 6 5 4 3 2 1 0
Bit Name PH7PUPR PH6PUPR PH5PUPR PH4PUPR PH3PUPR PH2PUPR PH1PUPR PH0PUPR
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Sets individual pull-up control for each pin of Port H 0: PTHn pull-up off 1: PTHn pull-up on
n = 7 to 0
24.2.30 Port J Pull-Up Control Register (PJPUPR) PJPUPR is an 8-bit readable/writable register. Each bit of this register corresponds to PTJ7 to PTJ2, and when the pins of Port J are used by the peripheral modules, the pull-up control is performed individually. However, for the pins set to the GPIO in the PJCR, the settings in this register will be invalid.
Bit: 7 6 5 4 3 2 1 0 R 0 0 R
PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1, 0
Bit Name PJ7PUPR PJ6PUPR PJ5PUPR PJ4PUPR PJ3PUPR PJ2PUPR --
Initial Value 1 1 1 1 1 1 All 0
R/W R/W R/W R/W R/W R/W R/W R
Description Pull-up control of the pins of Port J can be set individually. 0: PTJn pull-up off 1: PTJn pull-up on
Reserved This bit is always read as 0, and the write value should always be 0.
n = 7 to 2
24.2.31 Port K Pull-Up Control Register (PKPUPR) PKPUPR is an 8-bit readable/writable register that individually controls the pull-up for pins PTK7 to PTK2 corresponding to each bit in the register when the given pin is used by a peripheral module. However, for the pins set to the GPIO in the PKCR, the settings in this register will be invalid.
Rev. 1.0, 02/03, page 872 of 1294
Bit:
7
6
5
4
3
2
1 0 R
0 0 R
PK7 PK6 PK5 PK4 PK3 PK2 PUPR PUPR PUPR PUPR PUPR PUPR Initial value: 1 1 1 1 1 1 R/W: R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1, 0
Bit Name PK7PUPR PK6PUPR PK5PUPR PK4PUPR PK3PUPR PK2PUPR --
Initial Value 1 1 1 1 1 1 All 0
R/W R/W R/W R/W R/W R/W R/W R
Description Sets individual pull-up control of pins of Port K 0: PTKn pull-up off 1: PTKn pull-up on
Reserved These bits are always read as 0, and the write value should always be 0.
n = 7 to 2
24.2.32 Mode-Pin Pull-Up Control Register (MDPUPR) MDPUPR is an 8-bit readable/writable register that individually controls the pull-up for the pins connected to each bit of the register field.
Bit: 7 6 5 4 3 2 1 0
MD MD MD MD MD MD MD MD PUPR7 PUPR6 PUPR5 PUPR4 PUPR3 PUPR2 PUPR1 PUPR0
Initial value: R/W:
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name MDPUPR7
Initial Value 0
R/W R/W
Description Controls pull-up of MD8 0: MD8 pull-up off 1: MD8 pull-up on
6
MDPUPR6
0
R/W
Controls pull-up of MD7 0: MD7 pull-up off 1: MD7 pull-up on
5
MDPUPR5
1
R/W
Controls pull-up of MD5 0: MD5 pull-up off 1: MD5 pull-up on
4
MDPUPR4
1
R/W
Controls pull-up of MD4/CE2B 0: MD4/CE2B pull-up off 1: MD4/CE2B pull-up on
Bit
Bit Name
Initial Value
R/W
Description Rev. 1.0, 02/03, page 873 of 1294
3
MDPUPR3
1
R/W
Controls pull-up of MD3/CE2A 0: MD3/CE2A pull-up off 1: MD3/CE2A pull-up on
2
MDPUPR2
0
R/W
Controls pull-up of MD2 0: MD2 pull-up off 1: MD2 pull-up on
1
MDPUPR1
0
R/W
Controls pull-up of MD1 0: MD1 pull-up off 1: MD1 pull-up on
0
MDPUPR0
0
R/W
Controls pull-up of MD0 0: MD0 pull-up off 1: MD0 pull-up on
24.2.33 Input-Pin Pull-Up Control Register (INPUPA) INPUPA is a 16-bit readable/writable register that individually controls the pull-up for the pin connected to each bit of the register field.
Bit: 15 MD6 PUP 1 R/W 14 13 12 RDY BREQ IRL0 PUP PUP PUP 1 1 1 R/W R/W R/W 11 IRL1 PUP 1 R/W 10 IRL2 PUP 1 R/W 9 IRL3 PUP 1 R/W 8 NMI PUP 1 R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Initial value: R/W:
Bit 15
Bit Name MD6PUP
Initial Value 1
R/W R/W
Description Controls pull-up of MD6/IOIS16 0: MD6/IOIS16 pull-up off 1: MD6/IOIS16 pull-up on
14
RDYPUP
1
R/W
Controls pull-up of RDY 0: RDY pull-up off 1: RDY pull-up on
13
BREQPUP
1
R/W
Controls pull-up of BREQ 0: BREQ pull-up off 1: BREQ pull-up on
12
IRL0PUP
1
R/W
Controls pull-up of IRL0 0: IRL0 pull-up off 1: IRL0 pull-up on
Rev. 1.0, 02/03, page 874 of 1294
Bit 11
Bit Name IRL1PUP
Initial Value 1
R/W R/W
Description Controls pull-up of IRL1 0: IRL1 pull-up off 1: IRL1 pull-up on
10
IRL2PUP
1
R/W
Controls pull-up of IRL2 0: IRL2 pull-up off 1: IRL2 pull-up on
9
IRL3PUP
1
R/W
Controls pull-up of IRL3 0: IRL3 pull-up off 1: IRL3 pull-up on
8
NMIPUP
1
R/W
Controls pull-up of NMI 0: NMI pull-up off 1: NMI pull-up on
7 to 0
--
All 0
R
Reserved These bits are always read as 0, and the write value should always be 0.
24.2.34 DMA Pin Control Register (DMAPCR) DMAPCR is a 16-bit readable/writable register that controls the states of the DMAC pins (DREQ0, DREQ1, DRAK0, DRAK1, DACK0, and DACK1) and DMABRG reset.
15 DREQ P0 Initial value: 1 R/W: R/W Bit: 14 0 R 13 DREQ P1 1 R/W 12 0 R 11 10 9 8 7 6 5 4 DACK DACK DACK DACK DRAK DRAK DRAK DRAK P0 D0 P1 D1 P0 D0 P1 D1 0 1 0 1 0 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W 3 0 R 2 0 R 1 0 R 0 BRG RST 0 R/W
Bit 15
Bit Name DREQP0
Initial value 1
R/W R/W
Description Controls pull-up for DREQ0. 0: DREQ0 pull-up off 1: DREQ0 pull-up on
14
0
R
Reserved This bit is always read as 0, and the write value should always be 0.
13
DREQP1
1
R/W
Controls the pull-up for DREQ1. 0: DREQ1 pull-up off 1: DREQ1 pull-up on
Rev. 1.0, 02/03, page 875 of 1294
Bit 12
Bit Name
Initial value 0
R/W R
Description Reserved This bit is always read as 0, and the write value should always be 0.
11 10
DACKP0 DACKD0
0 1
R/W R/W
Controls the pin state for DACK0 in software standby mode. 00: Hi-Z state 01: Output 10: Hi-Z state with pull-up on 11: Setting prohibited
9 8
DACKP1 DACKD1
0 1
R/W R/W
Controls the pin state for DACK1 in software standby mode. 00: Hi-Z state 01: Output 10: Hi-Z state with pull-up on 11: Setting prohibited
7 6
DRAKP0 DRAKD0
0 1
R/W R/W
Controls the pin state for DRAK0 in software standby mode. 00: Hi-Z state 01: Output 10: Hi-Z state with pull-up on 11: Setting prohibited
5 4
DRAKP1 DRAKD1
0 1
R/W R/W
Controls the pin state for DRAK1 in software standby mode. 00: Hi-Z state 01: Output 10: Hi-Z state with pull-up on 11: Setting prohibited
3 to 1
All 0
R
Reserved These bits are always read as 0, and the write value should always be 0.
0
BRGRST
0
R/W
Controls a DMABRG reset. 0: Cancels DMABRG reset 1: Resets DMABRG Note: For the BRGRST usage, refer to section 11.7.1, DMABRG Reset.
Rev. 1.0, 02/03, page 876 of 1294
24.2.35 Peripheral Module Select Register (IPSELR) IPSELR is a 16-bit readable/writable register. Modules using pins multiplexed are specified by this register when the modules are not dependent on either MFI mode or LCD mode. For details of pin multiplexing, see table 24.1, Multiplexed Pins Controlled by Port Control Registers. This register is valid only when peripheral modules are selected by PACR, PBCR (PTB7 to PTB5), PDCR, PFCR, or PJCR (PJT5 to PJT3) of the GPIO.
Bit: 15 14 13 12 11 10 9 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0
IPSELR IPSELR IPSELR IPSELR IPSELR IPSELR IPSELR 15 14 13 12 11 10 9
LCDMD LCDMD 1 0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
Bit 15 14
Bit Name IPSELR15 IPSELR14
Initial Value 0 0
R/W R/W R/W
Description Out of the modules HSPI, MMCIF, and SIM, select the one using the pins HSPI_TX/SIM_D/MCDAT, HSPI_RX, HSPI_CLK/SIM_CLK/MCCLK, and HSPI_CS/SIM_RST/MCCMD. 00: Selects HSPI 01: Selects MMCIF 10: Setting prohibited 11: Selects SIM
13
IPSELR13
0
R/W
Out of the modules HCAN2 and AUD, select the one using the pins CAN0_NERR/AUDCK, CAN0_RX/AUDATA[2], CAN0_TX/AUDATA[0], CAN1_NERR/AUDSYNC, CAN1_RX/AUDATA[3], and CAN1_TX/AUDATA[1]. 0: Selects HCAN2 1: Selects AUD
12
IPSELR12
0
R/W
Out of the modules ADC and AUD, select the one using the pins Reserved/AUDATA[3], Reserved/AUDATA[2], Reserved/AUDATA[1], Reserved/AUDCK, Reserved/AUDSYNC, and ADTRG/AUDATA[0]. 0: Reserved/ADC* 1: AUD Note: *Pull up the reserved pins internally in the PKCR register settings.
Rev. 1.0, 02/03, page 877 of 1294
Bit 11 10
Bit Name IPSELR11 IPSELR10
Initial Value 0 0
R/W R/W R/W
Description Out of the modules SSI[1]/[0] and HAC[1]/[0], select the one using the pins SSI0_SCK/HAC_SD_IN0/BS2, SSI0_WS/HAC_SYNC0, SSI0_SDATA/HAC_SD_OUT0, SSI1_SCK/HAC_SD_IN1, SSI1_SDATA/HAC_SD_OUT1, and SSI1_WS/HAC_SYNC1. 00: SSI[0], SSI[1] 01: HAC[0]. SSI[1] 10:Setting prohibited 11:HAC[0], HAC[1] Select the pins MFI-D8/LCD_DATA8 to MFID15/LCD_DATA15 of MFI/LCDC. 0: MFI/LCDC 1: Setting prohibited Reserved These bits are always read as 0, and the write value should always be 0.
9
IPSELR9
0
R/W
8 to 2
--
All 0
R
1 0
LCDMD1 LCDMD0
1 1
R/W R/W
LDCD mode settings 00: Mode 1 LCD_CL1 and LCD_FLM output LCD_CL2 output 01: Mode 2 LCD_CL1 and LCD_FLM output LCD_CL2 Hiz Other than above: Setting prohibited Note: When using the LCDC, be sure to set these bits to B'00 or B'01.
24.2.36 SCIF.Hi-z Control Register (SCIHZR) SCIHZR is a 16-bit readable/writable register that controls the pin state of the individual port pins in software standby mode when a Peripheral module (SCIF0 to SCIF2) is selected by the PGCR or PHCR. When each bit is 0, the corresponding pin retains the state before the software standby mode is entered. This register settings is ignored when the pins are specified as the GPIO port by PGCR or PHCR. This register setting is also ignored when the SCIF controls the pins.
15 14 13 12 11 10 9 8 7 6 5 4 3 SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI SCI CLK0 RXD0 TXD0 CLK1 CTS1 RTS1 RXD1 TXD1 CLK2 CTS2 RTS2 RXD2 TXD2 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: 2 0 R 1 0 R 0 0 R
Rev. 1.0, 02/03, page 878 of 1294
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 to 0
Bit Name SCICLK0 SCIRXD0 SCITXD0 SCICLK1 SCICTS1 SCIRTS1 SCIRXD1 SCITXD1 SCICLK2 SCICTS2 SCIRTS2 SCIRXD2 SCITXD2 --
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 All 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Description 0: Sets SCIF0_CLK Hi-Z state to off 1: Sets SCIF0_CLK Hi-Z state to on 0: Sets SCIF0_RXD Hi-Z state to off 1: Sets SCIF0_RXD Hi-Z state to on 0: Sets SCIF0_TXD Hi-Z state to off 1: Sets SCIF0_TXD Hi-Z state to on 0: Sets SCIF1_CLK Hi-Z state to off 1: Sets SCIF1_CLK Hi-Z state to on 0: Sets SCIF1_CTS Hi-Z state to off 1: Sets SCIF1_CTS Hi-Z state to on 0: Sets SCIF1_RTS Hi-Z state to off 1: Sets SCIF1_RTS Hi-Z state to on 0: Sets SCIF1_RXD Hi-Z state to off 1: Sets SCIF1_RXD Hi-Z state to on 0: Sets SCIF1_TXD Hi-Z state to off 1: Sets SCIF1_TXD Hi-Z state to on 0: Sets SCIF2_CLK Hi-Z state to off 1: Sets SCIF2_CLK Hi-Z state to on 0: Sets SCIF2_CTS Hi-Z state to off 1: Sets SCIF2_CTS Hi-Z state to on 0: Sets SCIF2_RTS Hi-Z state to off 1: Sets SCIF2_RTS Hi-Z state to on 0: Sets SCIF2_RXD Hi-Z state to off 1: Sets SCIF2_RXD Hi-Z state to on 0: Sets SCIF2_TXD Hi-Z state to off 1: Sets SCIF2_TXD Hi-Z state to on Reserved These bits are always read as 0, and the write value should always be 0.
24.2.37 Mode Select Register (MODSELR) MODESELR is an 8-bit readable/writable register that individually sets the mode of pins MFI-D2 to MFI-D7 and SSI0_SCK. When MFI mode/LCD mode is used, modules should be selected in IPSELR. However, when these pins are used as GPIOs, the settings in this register will be invalid.
Bit: 7 6 5 4 3 2 1 0 0 R
MOD MOD MOD MOD MOD MOD MOD SELR7 SELR6 SELR5 SELR4 SELR3 SELR2 SELR1
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Rev. 1.0, 02/03, page 879 of 1294
Bit 7
Bit Name MODSELR7
Initial Value 0
R/W R/W
Description Selects the mode of pin MFI-D2/LCD_DATA2/IRQ6 0: MFI mode/LCD mode (MFI/LCDC) 1: IRQ6
6
MODSELR6
0
R/W
Selects the mode of pin MFI-D3/LCD_DATA3/IRQ7 0: MFI mode/LCD mode (MFI/LCDC) 1: IRQ7
5
MODSELR5
0
R/W
Selects the mode of pin MFI-D4/LCD_DATA4/DREQ2 0: MFI mode/LCD mode (MFI/LCDC) 1: DREQ2
4
MODSELR4
0
R/W
Selects the mode of pin MFI-D5/LCD_DATA5/DRAK2/DACK2 0: MFI mode/LCD mode (MFI/LCDC) 1: DRAK2/DACK2
3
MODSELR3
0
R/W
Selects the mode of pin MFI-D6/LCD_DATA6/DREQ3 0: MFI mode/LCD mode (MFI/LCDC) 1: DREQ3
2
MODSELR2
0
R/W
Selects the mode of pin MFI-D7/LCD_DATA7/DRAK3/DACK3 0: MFI mode/LCD mode (MFI/LCDC) 1: DRAK3/DACK3
1
MODSELR1
0
R/W
Selects the mode of pin SSI0_SCK/HAC_SD_IN0/BS2 0: MFI mode/LCD mode (SSI/HAC) 1: BS2
0
--
0
R
Reserved This bit is always read as 0, and the write value should always be 0.
Rev. 1.0, 02/03, page 880 of 1294
Section 25 Hitachi Audio Codec Interface (HAC)
The HAC, the audio codec digital controller interface, supports bidirectional data transfer compliant with Audio Codec 97 (AC'97) Version 2.1. The HAC provides serial transmission to /reception from the AC97 codec. Each channel of the HAC can be connected to a single audio codec device. The HAC carries out data extraction from/insertion into audio frames. For data slots within both receive and transmit frames, the PIO transfer by the CPU or the DMA transfer by the DMAC can be used.
25.1
Features
The HAC has the following features: * Digital interface to a single AC'97 version 2.1 Audio Codec * PIO transfer of status slots 1 and 2 in Rx frames * PIO transfer of command slots 1 and 2 in Tx frames * PIO transfer of data slots 3 and 4 in Rx frames * PIO transfer of data slots 3 and 4 in Tx frames * Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Rx frames * Selectable 16-bit or 20-bit DMA transfer of data slots 3 and 4 in Tx frames * Accommodates various sampling rates by qualifying slot data with tag bits and monitoring the Tx frame request bits of Rx frames * Generates data ready, data request, overrun and underrun interrupts * Supports cold reset, warm reset, and power-down mode
Rev. 1.0, 02/03, page 881 of 1294
Figure 25.1 shows a block diagram of the HAC.
HAC receiver HAC_ SD_IN (0/1) Shift register for slot 1 Shift register for slot 2 Shift register for slot 3 HAC_ BIT_CLK(0/1) Request signal for slots 3 & 4 Shift register for slot 4 Data[19:0] Data[19:0] Data[19:0] Data[19:0] Control signal Bit control signal HAC transmitter HAC_ SD_OUT(0/1) Shift register for slot 1 Shift register for slot 2 Shift register for slot 3 Shift register for slot 4 HAC_SYNC(0/1) HAC_RES Data[19:0] Data[19:0] Data[19:0] Data[19:0] Control signal
Internal bus interface (Reception) CSAR RX buffer CSDR RX buffer PCML RX buffer PCMR RX buffer DMA request Interrupt request Internal bus interface (Transmission) CSAR TX buffer CSDR TX buffer PCML TX buffer PCMR TX buffer DMA control DMA request Interrupt request Data[31:0] Data[31:0]
Figure 25.1 Block Diagram
25.2
Input/Output Pins
Table 25.1 describes the HAC pin configuration. Table 25.1 Pin Configuration
Name HAC_BIT_CLK (0/1) HAC_SD_IN (0/1) HAC_SD_OUT (0/1) HAC_SYNC (0/1) HAC_RES
# of Pins
1 1 1 1 1
I/O Input Input Output Output Output
Function HAC serial data clock HAC serial data incoming to Rx frame HAC serial data outgoing from Tx frame HAC frame sync HAC reset (negative logic signal) (common to channels 0 and 1)
Rev. 1.0, 02/03, page 882 of 1294
HAC bridge bus
DMA control
25.3
Register Descriptions
This section describes the HAC registers. For details of register addresses and register statuses in each processing, see section 32, List of Registers. Since these registers function in the same way in both channels 0 and 1, they are not discriminated by channel number in the description below. Table 25.2 Register Configuration (1)
Ch. Register Name 0 Control and status register 0 Command/status address register 0 Command/status data register 0 PCM left channel register 0 PCM right channel register 0 TX interrupt enable register 0 TX status register 0 RX interrupt enable register 0 RX status register 0 HAC control register 0 1 Control and status register 1 Command/status address register 1 Command/status data register 1 PCM left channel register 1 PCM right channel register 1 TX interrupt enable register 1 TX status register 1 RX interrupt enable register 1 RX status register 1 HAC control register 1 Abbrev. HACCR0 R/W R/W P4 Address H'FE24 0008 H'FE24 0020 H'FE24 0024 H'FE24 0028 H'FE24 002C H'FE24 0050 H'FE24 0054 H'FE24 0058 H'FE24 005C H'FE24 0060 H'FE25 0008 H'FE25 0020 H'FE25 0024 H'FE25 0028 H'FE25 002C H'FE25 0050 H'FE25 0054 H'FE25 0058 H'FE25 005C H'FE25 0060 Area 7 Address H'1E24 0008 H'1E24 0020 H'1E24 0024 H'1E24 0028 H'1E24 002C H'1E24 0050 H'1E24 0054 H'1E24 0058 H'1E24 005C H'1E24 0060 H'1E25 0008 H'1E25 0020 H'1E25 0024 H'1E25 0028 H'1E25 002C H'1E25 0050 H'1E25 0054 H'1E25 0058 H'1E25 005C H'1E25 0060 Sync Size Clock 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
HACCSAR0 R/W HACCSDR0 R/W HACPCML0 R/W HACPCMR0 R/W HACTIER0 HACTSR0 HACRIER0 HACRSR0 HACACR0 HACCR1 R/W R/W R/W R/W R/W R/W
HACCSAR1 R/W HACCSDR1 R/W HACPCML1 R/W HACPCMR1 R/W HACTIER1 HACTSR1 HACRIER1 HACRSR1 HACACR1 R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 883 of 1294
Table 25.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI Manual Reset by RESET Pin/WDT/ Multiple Exceptions Standby Sleep by Sleep Instruction/ by Deep Sleep Hardware
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained *
Ch. Register Name
0 Control and status register 0 Command/status address register 0 Command/status data register 0 PCM left channel register 0 PCM right channel register 0 TX interrupt enable register 0 TX status register 0 RX interrupt enable register 0 RX status register 0 HAC control register 0 1 Control and status register 1 Command/status address register 1 Command/status data register 1 PCM left channel register 1 PCM right channel register 1 TX interrupt enable register 1 TX status register 1 RX interrupt enable register 1 RX status register 1 HAC control register 1
Abbrev.
HACCR0
by Software /Each Module
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0200 H'0000 0200
HACCSAR0 H'0000 0000 H'0000 0000 HACCSDR0 H'0000 0000 H'0000 0000 HACPCML0 H'0000 0000 H'0000 0000 HACPCMR0 H'0000 0000 H'0000 0000 HACTIER0 HACTSR0 HACRIER0 HACRSR0 HACACR0 HACCR1 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 H'8400 0000 H'0000 0200 H'0000 0200
HACCSAR1 H'0000 0000 H'0000 0000 HACCSDR1 H'0000 0000 H'0000 0000 HACPCML1 H'0000 0000 H'0000 0000 HACPCMR1 H'0000 0000 H'0000 0000 HACTIER1 HACTSR1 HACRIER1 HACRSR1 HACACR1 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 H'8400 0000
Note:
* After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin.
Rev. 1.0, 02/03, page 884 of 1294
25.3.1
Control and Status Register (HACCR)
HACCR is a 32-bit read/write register for controlling input/output and monitoring the interface status.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 CR 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 26 0 R 10 25 0 R 9 1 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 ST 0 W 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
CDRT WMRT 0 W 0 W
Bit
Bit Name
Initial Value All 0 0
R/W R R
Description Reserved Always 0 for read and write. Codec Ready 0: The HAC-connected codec is not ready. 1: The HAC-connected codec is ready.
31 to 16 15 CR
14 to 12 11 CDRT
All 0 0
R W
Reserved Always read as 0. Write prohibited. HAC Cold Reset Use a cold reset only after power-on, or only to exit from the power-down mode by the powerdown command. [Write] 0: Always write 0 to this bit before writing 1 again. 1: Performs a cold reset on the HAC. [Read] Always read as 0.
10
WMRT
0
W
HAC Warm Reset Use a warm reset only after power-up, or only to exit from the power-down mode by the powerdown command. [Write] 0: Always write 0 to this bit before writing 1 again. 1: Performs a warm reset on the HAC. [Read] Always read as 0.
9
1
R
Reserved Always 1 for read and write.
Rev. 1.0, 02/03, page 885 of 1294
Bit Bit 8 to 6 5
Bit Name Bit Name ST
Initial Value Initial Value All 0 0
R/W R/W R W
Description Description Reserved Always 0 for read and write. Start Transfer [Write] 1: Starts data transmission/reception. 0: Stops data transmission/reception at the end of the current frame. Do not take this action to terminate transmission/reception in normal operation. [Read access] Always read as 0.
4 to 0
All 0
R
Reserved Always 0 for read and write.
To place the off-chip codec device into the power-down mode, write 1 to bit 12 of the register index 26 in the off-chip codec via the HAC. When entering the power-down mode, the off-chip codec stops HAC_BIT_CLK and suspends the normal operation. The off-chip codec acts in the same manner at power-on. To resume the normal operation, perform a cold reset or a warm reset on the off-chip codec. 25.3.2 Command/Status Address Register (HACCSAR)
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read /written. When requesting a write to/read from a codec register, write the command register address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1. After the codec has responded to a read request (HACRSR.STARY = 1), the status address received via slot 1 can be read out from HACCSAR.
Bit: 31 Initial value: R/W: Bit: 0 R 30 0 R 14 CA2/ SA2 0 R/W 29 0 R 13 CA1/ SA1 0 R/W 28 0 R 12 CA0/ SA0 0 R/W 27 0 R 11 SLR EQ3 0 R 26 0 R 10 SLR EQ4 0 R 25 0 R 9 SLR EQ5 0 R 24 0 R 8 SLR EQ6 0 R 23 0 R 7 SLR EQ7 0 R 22 0 R 6 SLR EQ8 0 R 21 0 R 5 SLR EQ9 0 R 20 0 R 19 RW 0 R/W 18 17 16 CA6/ CA5/ CA4/ SA6 SA5 SA4 0 0 0 R/W R/W R/W 1 0 R 0 0 R
15 CA3/ SA3 Initial value: 0 R/W: R/W
4 3 2 SLR SLR SLR EQ10 EQ11 EQ12 0 0 0 R R R
Rev. 1.0, 02/03, page 886 of 1294
Bit
Bit Name
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. Codec Read/Write Command 0: Notifies the off-chip codec device of a write access to the register specified in the address field (CA6/SA6 to CA0/SA0). Write the data to HACCSDR in advance. When HACACR.TX12_ATOMIC is 1, the HAC transmits HACCSAR and HACCSDR as a pair in the same Tx frame. When HACACR.TX12_ATOMIC is 0, transmission of HACCSAR and HACCSDR in the same Tx frame is not guaranteed. 1: Notifies the off-chip codec device of a read access to the register specified in the address field (CA6/SA6 to CA0/SA0). Codec Control Register Addresses 6 to 0 /Codec Status Register Addresses 6 to 0 [Write] Specify the address of the codec register to be written. [Read] Indicate the status address received via slot 1, corresponding to the codec register whose data has been returned in HACCSDR. Slot Requests 3 to 12 Valid only in the Rx frame. Indicate whether the codec is requesting slot data in the next Tx frame. Automatically set by hardware, and correspond to bits 11 to 2 of slot 1 in the Rx frame. 0: Slot data is requested. 1: Slot data is not requested.
31 to 20 19 RW
18 17 16 15 14 13 12
CA6/SA6 CA5/SA5 CA4/SA4 CA3/SA3 CA2/SA2 CA1/SA1 CA0/SA0
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
11 10 9 8 7 6 5 4 3 2 1, 0
SLREQ3 SLREQ4 SLREQ5 SLREQ6 SLREQ7 SLREQ8 SLREQ9 SLREQ10 SLREQ11 SLREQ12
0 0 0 0 0 0 0 0 0 0 All 0
R R R R R R R R R R R
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 887 of 1294
25.3.3
Command/Status Data Register (HACCSDR)
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the command data to HACCSDR. The HAC then transmits the data to the codec via slot 2. After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related codec register address.
Bit: 31 Initial value: R/W: Bit: 0 R 30 0 R 29 0 R 28 0 R 12 CD8/ SD8 0 R/W 27 0 R 11 CD7/ SD7 0 R/W 26 0 R 25 0 R 24 0 R 8 CD4/ SD4 0 R/W 23 0 R 7 CD3/ SD3 0 R/W 22 0 R 6 CD2/ SD2 0 R/W 21 0 R 5 CD1/ SD1 0 R/W 20 0 R 4 CD0/ SD0 0 R/W 19 18 17 16 CD15/ CD14/ CD13/ CD12/ SD15 SD14 SD13 SD12 0 0 0 0 R/W R/W R/W R/W 3 0 R 2 0 R 1 0 R 0 0 R
15 14 13 CD11/ CD10/ CD9/ SD11 SD10 SD9 Initial value: 0 0 0 R/W: R/W R/W R/W
10 9 CD6/ CD5/ SD6 SD5 0 0 R/W R/W
Bit
Bit Name
Initial Value All 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All 0
R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Description Reserved Always 0 for read and write. Command Data 15 to 0/Status Data 15 to 0 Write data to these bits and then write the codec register address in HACCSAR. The HAC then transmits the data to the codec. Read these bits to get the contents of the codec register indicated by HACCSAR.
31 to 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 to 0 CD15/SD15 CD14/SD14 CD13/SD13 CD12/SD12 CD11/SD11 CD10/SD10 CD9/SD9 CD8/SD8 CD7/SD7 CD6/SD6 CD5/SD5 CD4/SD4 CD3/SD3 CD2/SD2 CD1/SD1 CD0/SD0
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 888 of 1294
25.3.4
PCM Left Channel Register (HACPCML)
HACPCML is a 32-bit read/write data register used for accessing the left channel of the codec in digital audio recording or stream playback. To transmit the PCM playback left channel data to the codec, write the data to HACPCML. To receive the PCM record left channel data from the codec, read HACPCML. The data is left justified to accommodate a codec with ADC/DAC resolution of 20 bits or less.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 D15 0 R/W 30 0 R 14 D14 0 R/W 29 0 R 13 D13 0 R/W 28 0 R 12 D12 0 R/W 27 0 R 11 D11 0 R/W 26 0 R 10 D10 0 R/W 25 0 R 9 D9 0 R/W 24 0 R 8 D8 0 R/W 23 0 R 7 D7 0 R/W 22 0 R 6 D6 0 R/W 21 0 R 5 D5 0 R/W 20 0 R 4 D4 0 R/W 19 D19 0 R/W 3 D3 0 R/W 18 D18 0 R/W 2 D2 0 R/W 17 D17 0 R/W 1 D1 0 R/W 16 D16 0 R/W 0 D0 0 R/W
Bit
Bit Name
Initial Value All 0 All 0
R/W R R/W
Description Reserved Always 0 for read and write. Data 19 to 0 Write the PCM playback left channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record left channel data from the codec.
31 to 20 19 to 0 D19 to D0
In 16-bit packed DMA mode, HACPCML is defined as follows:
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 LD9 0 R/W 9 RD9 0 R/W 24 LD8 0 R/W 8 RD8 0 R/W 23 LD7 0 R/W 7 RD7 0 R/W 22 LD6 0 R/W 6 RD6 0 R/W 21 LD5 0 R/W 5 RD5 0 R/W 20 LD4 0 R/W 4 RD4 0 R/W 19 LD3 0 R/W 3 RD3 0 R/W 18 LD2 0 R/W 2 RD2 0 R/W 17 LD1 0 R/W 1 RD1 0 R/W 16 LD0 0 R/W 0 RD0 0 R/W
LD15 LD14 LD13 LD12 LD11 LD10 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10
RD15 RD14 RD13 RD12 RD11 RD10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Rev. 1.0, 02/03, page 889 of 1294
Bit
Bit Name
Initial Value
R/W R/W
Description Left Data 15 to 0 Write the PCM playback left channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record left channel data from the codec.
31 to 16 LD15 to LD0 All 0
15 to 0
RD15 to RD0
All 0
R/W
Right Data 15 to 0 Write the PCM playback right channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record right channel data from the codec.
25.3.5
PCM Right Channel Register (HACPCMR)
HACPCMR is a 32-bit read/write register used for accessing the right channel of the codec in digital audio recording or stream playback. To transmit the PCM playback right channel data to the codec, write the data to HACPCMR. To receive the PCM record right channel data from the codec, read HACPCMR. The data is left justified to accommodate a codec with ADC/DAC resolution of 20-bit or less.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 D15 0 R/W 30 0 R 14 D14 0 R/W 29 0 R 13 D13 0 R/W 28 0 R 12 D12 0 R/W 27 0 R 11 D11 0 R/W 26 0 R 10 D10 0 R/W 25 0 R 9 D9 0 R/W 24 0 R 8 D8 0 R/W 23 0 R 7 D7 0 R/W 22 0 R 6 D6 0 R/W 21 0 R 5 D5 0 R/W 20 0 R 4 D4 0 R/W 19 D19 0 R/W 3 D3 0 R/W 18 D18 0 R/W 2 D2 0 R/W 17 D17 0 R/W 1 D1 0 R/W 16 D16 0 R/W 0 D0 0 R/W
Bit
Bit Name
Initial Value All 0 All 0
R/W R R/W
Description Reserved Always 0 for read and write. Data 19 to 0 Write the PCM playback right channel data to these bits. The HAC then transmits the data to the codec on an on-demand basis. Read these bits to get the PCM record right channel data from the codec.
31 to 20 19 to 0 D19 to D0
Rev. 1.0, 02/03, page 890 of 1294
25.3.6
TX Interrupt Enable Register (HACTIER)
HACTIER is a 32-bit read/write register that enables or disables HAC TX interrupts.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 28 PLTF PRTF RQIE RQIE 0 0 R/W R/W 13 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 24 0 R 23 0 R 7 0 R 22 0 R 6 0 R 21 0 R 5 0 R 20 0 R 4 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
9 8 PLTF PRTF UNIE UNIE 0 0 R/W R/W
Bit 31, 30 29
Bit Name PLTFRQIE
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. PCML TX Request Interrupt Enable 0: Disables PCML TX request interrupts 1: Enables PCML TX request interrupts
28
PRTFRQIE
0
R/W
PCMR TX Request Interrupt Enable 0: Disables PCMR TX request interrupts 1: Enables PCMR TX request interrupts
27 to 10 9 PLTFUNIE
All 0 0
R R/W
Reserved Always 0 for read and write. PCML TX Underrun Interrupt Enable 0: Disables PCML TX underrun interrupts 1: Enables PCML TX underrun interrupts
8
PRTFUNIE
0
R/W
PCMR TX Underrun Interrupt Enable 0: Disables PCMR TX underrun interrupts 1: Enables PCMR TX underrun interrupts
7 to 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 891 of 1294
25.3.7
TX Status Register (HACTSR)
HACTSR is a 32-bit read/write register that indicates the status of the HAC TX controller. Writing 0 to the bit will initialize it.
Bit: 31 CMD AMT 1 R/W 15 Initial value: R/W: 0 R 30 CMD DMT 1 R/W 14 0 R 29 PLT FRQ 1 R/W 13 0 R 28 PRT FRQ 1 R/W 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 PLT FUN 0 R/W
2
24 0 R 8 PRT FUN 0 R/W
23 0 R 7 0 R
22 0 R 6 0 R
21 0 R 5 0 R
20 0 R 4 0 R
19 0 R 3 0 R
18 0 R 2 0 R
17 0 R 1 0 R
16 0 R 0 0 R
Initial value: R/W: Bit:
Bit 31
Bit Name CMDAMT
Initial Value 1
R/W* R/W
Description Command Address Empty 0: CSAR Tx buffer contains untransmitted data. 1: CSAR Tx buffer is empty and ready to store 1 data.* Restrictions related to the CMDAMT bit are described in 25.5.5. For details of HAC initialization steps, see the operational flow in 25.5.6.
30
CMDDMT
1
R/W
Command Data Empty 0: CSDR Tx buffer contains untransmitted data. 1: CSDR Tx buffer is empty and ready to store 1 data. *
29
PLTFRQ
1
R/W
PCML TX Request 0: PCML Tx buffer contains untransmitted data. 1: PCML TX buffer is empty and needs to store data. In DMA mode, writing to HACPCML will automatically clear this bit to 0.
28
PRTFRQ
1
R/W
PCMR TX Request 0: PCMR Tx buffer contains untransmitted data. 1: PCMR TX buffer is empty and needs to store data. In DMA mode, writing to HACPCMR will automatically clear this bit to 0.
27 to 10
All 0
R
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 892 of 1294
Bit 9
Bit Name PLTFUN
Initial Value 0
R/W* R/W
2
Description PCML TX Underrun 0: No PCML TX underrun has occurred. 1: PCML TX underrun has occurred because the codec has requested slot 3 with PLTFRQ = 1.
8
PRTFUN
0
R/W
PCMR TX Underrun 0: No PCMR TX underrun has occurred. 1: PCMR TX underrun has occurred because the codec has requested slot 4 with PRTFRQ = 1.
7 to 0
All 0
R
Reserved Always 0 for read and write.
Notes: *1 CMDAMT and CMDDMT have no associated interrupts. Poll these bits until they are read as 1 before writing a new command to HACCSAR/HACCSDR. When bit 19 (RW) of HACCSAR is 0 and TX12_ATOMIC is 1, take the following steps: 1. Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC initialization by any reset event. 2. After making the settings in HACCSDR and HACCSAR, poll CMDDMT and CMDAMT until they are cleared to 1, and then initialize these bits. 3. Now the next write to a register is available. *2 These bits are read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
25.3.8
RX Interrupt Enable Register (HACRIER)
HACRIER is a 32-bit read/write register that enables or disables HAC RX interrupts.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 28 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 21 20 19 STAR STDR PLRF PRRF YIE YIE RQIE RQIE 0 0 0 0 R/W R/W R/W R/W 6 0 R 5 0 R 4 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 0 R
13 12 PLRF PRRF OVIE OVIE 0 0 R/W R/W
Rev. 1.0, 02/03, page 893 of 1294
Bit
Bit Name
Initial Value All 0 0
R/W R R/W
Description Reserved Always 0 for read and write. Status Address Ready Interrupt Enable 0: Disables status address ready interrupts. 1: Enables status address ready interrupts.
31 to 23 22 STARYIE
21
STDRYIE
0
R/W
Status Data Ready Interrupt Enable 0: Disables status data ready interrupts. 1: Enables status data ready interrupts.
20
PLRFRQIE
0
R/W
PCML RX Request Interrupt Enable 0: Disables PCML RX request interrupts. 1: Enables PCML RX request interrupts.
19
PRRFRQIE
0
R/W
PCMR RX Request Interrupt Enable 0: Disables PCMR RX request interrupts. 1: Enables PCMR RX request interrupts.
18 to 14 13 PLRFOVIE
All 0 0
R R/W
Reserved Always 0 for read and write. PCML RX Overrun Interrupt Enable 0: Disables PCML RX overrun interrupts. 1: Enables PCML RX overrun interrupts.
12
PRRFOVIE
0
R/W
PCMR RX Overrun Interrupt Enable 0: Disables PCMR RX overrun interrupts. 1: Enables PCMR RX overrun interrupts.
11 to 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 894 of 1294
25.3.9
RX Status Register (HACRSR)
HACRSR is a 32-bit read/write register that indicates the status of the HAC RX controller. Writing 0 to the bit will initialize it.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13
PLR FOV
28 0 R 12
PRR FOV
27 0 R 11 0 R
26 0 R 10 0 R
25 0 R 9 0 R
24 0 R 8 0 R
23 0 R 7 0 R
22
21
20
PLR FRQ
19
PRR FRQ
18 0 R 2 0 R
17 0 R 1 0 R
16 0 R 0 0 R
STARY STDRY
0 R/W 6 0 R
0 R/W 5 0 R
0 R/W 4 0 R
0 R/W 3 0 R
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0 0
R/W* R R/W
Description Reserved Always 0 for read and write. Status Address Ready 0: HACCSAR (status address) is not ready. 1: HACCSAR (status address) is ready.
31 to 23 22 STARY
21
STDRY
0
R/W
Status Data Ready 0: HACCSDR (status data) is not ready. 1: HACCSDR (status data) is ready.
20
PLRFRQ
0
R/W
PCML RX Request 0: PCML RX data is not ready. 1: PCML RX data is ready and must be read. In DMA mode, reading HACPCML automatically clears this bit to 0.
19
PRRFRQ
0
R/W
PCMR RX Request 0: PCMR RX data is not ready. 1: PCMR RX data is ready and must be read. In DMA mode, reading HACPCMR automatically clears this bit to 0.
18 to 14 13 PLRFOV
All 0 0
R R/W
Reserved Always 0 for read and write. PCML RX Overrun 0: No PCML RX data overrun has occurred. 1: PCML RX data overrun has occurred because the HAC has received new data from slot 3 with PLRFRQ = 1.
Rev. 1.0, 02/03, page 895 of 1294
Bit Bit 12
Bit Name Bit Name PRRFOV
Initial Value Initial Value 0
R/W* R/W* R/W
Description Description PCMR RX Overrun 0: No PCMR RX data overrun has occurred. 1: PCMR RX data overrun has occurred because the HAC has received new data from slot 4 with PRRFRQ = 1.
11 to 0 Note: *
All 0
R
Reserved Always 0 for read and write.
This register is read/write. Writing 0 to the bit initializes it but writing 1 has no effect.
25.3.10 HAC Control Register (HACACR) HACACR is a 32-bit read/write register used for controlling the HAC interface.
Bit: 31 Initial value: R/W: Bit: 1 R 15 Initial value: R/W: 0 R 30
DMA RX16
29
DMA TX16
28 0 R 12 0 R
27 0 R 11 0 R
26
TX12_ ATOMIC
25 0 R 9 0 R
24
23
22
21
20 0 R 4 0 R
19 0 R 3 0 R
18 0 R 2 0 R
17 0 R 1 0 R
16 0 R 0 0 R
RXDMAL TXDMAL RXDMAR TXDMAR _EN _EN _EN _EN
0 R/W 14 0 R
0 R/W 13 0 R
1 R/W 10 0 R
0 R/W 8 0 R
0 R/W 7 0 R
0 R/W 6 0 R
0 R/W 5 0 R
Bit 31 30
Bit Name DMARX16
Initial Value 1 0
R/W R R/W
Description Reserved Always 1 for read and write.. 16-bit RX DMA Enable 0: Disables 16-bit packed RX DMA mode. Enables the RXDMAL_EN and RXDMAR_EN settings. 1: Enables 16-bit packed RX DMA mode. Disables the RXDMAL_EN and RXDMAR_EN settings.
29
DMATX16
0
R/W
16-bit TX DMA Enable 0: Disables 16-bit packed TX DMA mode. Enables the TXDMAL_EN and TXDMAR_EN settings. 1: Enables 16-bit packed TX DMA mode. Disables the TXDMAL_EN and TXDMAR_EN settings.
Rev. 1.0, 02/03, page 896 of 1294
Bit Bit 28, 27 26
Bit Name Bit Name TX12_ATOMIC
Initial Value Initial Value All 0 1
R/W R/W R R/W
Description Description Reserved Always 0 for read and write. TX Slot 1 and 2 Atomic Control 0: Transmits TX data in HACCSAR and that in HACCSDR separately. (Setting prohibited) 1: Transmits TX data in HACCSAR and that in HACCSDR in the same frame if bit 19 in HACCSAR is 0 (write). (HACCSAR must be written last.)
25 24
RXDMAL_EN
0 0
R R/W
Reserved Always 0 for read and write. RX DMA Left Enable 0: Disables 20-bit RX DMA for HACPCML. 1: Enables 20-bit RX DMA is for HACPCML.
23
TXDMAL_EN
0
R/W
TX DMA Left Enable 0: Disables 20-bit TX DMA for HACPCML. 1: Enables 20-bit TX DMA for HACPCML.
22
RXDMAR_EN
0
R/W
RX DMA Right Enable 0: Disables 20-bit RX DMA for HACPCMR. 1: Enables 20-bit RX DMA for HACPCMR.
21
TXDMAR_EN
0
R/W
TX DMA Right Enable 0: Disables 20-bit TX DMA for HACPCMR. 1: Enables 20-bit TX DMA for HACPCMR.
20 to 0
All 0
R
Reserved Always 0 for read and write.
Rev. 1.0, 02/03, page 897 of 1294
25.4
AC 97 Frame Slot Structure
Figure 25.2 shows the AC97 frame slot structure. This LSI supports slots 0 to 4 only. Slots 5 to 12 are out of scope.
Slot No. HAC_SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12
HAC_SD_OUT (transmit) HAC_SD_IN (receive)
TAG
CMD Addr
CMD Data
PCML PCMR LINE1 PCM PCML PCMR PCM Front Front DAC Center Surr Surr LFE PCM Right LINE1 PCM MIC ADC Reser Reser ved ved
LINE2 HSET IO DAC DAC CTRL
TAG
Status Status PCM Addr Data Left
Reser LINE2 HSET IO ved ADC Status ADC
Figure 25.2 AC97 Frame Slot Structure Table 25.3 AC97 Transmit Frame Structure
Slot 0 1 2 3 4 5 6 7 8 9 10 11 12 Name SDATA_OUT TAG Control CMD Addr write port Control DATA write port PCM L DAC playback PCM R DAC playback Modem Line 1 DAC PCM Center PCM Surround L PCM Surround R PCM LFE Modem Line 2 DAC Modem handset DAC Modem IO control Description Codec IDs and Tags indicating valid data Read/write command and register address Register write data Left channel PCM output data Right channel PCM output data Modem 1 output data (unsupported) Center channel PCM data (unsupported) Surround left channel PCM data (unsupported) Surround right channel PCM data (unsupported) LFE channel PCM data (unsupported) Modem 2 output data (unsupported) Modem handset output data (unsupported) Modem control IO output (unsupported)
Rev. 1.0, 02/03, page 898 of 1294
Table 25.4 AC97 Receive Frame Structure
Slot 0 1 2 3 4 5 6 7 to 9 10 11 12 Name SDATA_IN TAG Status ADDR read port Status DATA read port PCM L ADC record PCM R ADC record Modem Line 1 ADC Dedicated Microphone ADC Reserved Modem Line 2 ADC Modem handset input DAC Modem IO status Description Tags indicating valid data Register address and slot request Register read data Left channel PCM input data Right channel PCM input data Modem 1 input data (unsupported) Optional PCM data (unsupported) Reserved Modem 2 input data (unsupported) Modem handset input data (unsupported) Modem control IO input (unsupported)
25.5
25.5.1
Operation
Receiver
The HAC receiver receives serial audio data input on the HAC_SD_IN pin, synchronous to HAC_BIT_CLK. From slot 0, the receiver extracts tag bits that indicate which other slots contain valid data. It will update the receive data only when receiving valid slot data indicated by the tag bits. Supporting data only in slots 1 to 4, the receiver ignores tag bits and data related to slots 5 to 12. It loads valid slot data to the corresponding shift register to hold the data for PIO or DMA transfer, and sets the corresponding status bits. It is possible to read 20-bit data within a 32-bit register using PIO. In the case of RX overrun, the new data will overwrite the current data in the RX buffer of the HAC.
Rev. 1.0, 02/03, page 899 of 1294
25.5.2
Transmitter
The HAC transmitter outputs serial audio data on the HAC_SD_OUT pin, synchronous to HAC_BIT_CLK. The transmitter sets the tag bits in slot 0 to indicate which slots in the current frame contain valid data. It loads data slots to the current TX frame in response to the corresponding slot request bits from the previous RX frame. The transmitter supports data only in slots 1 to 4. The TX buffer holds data that has been transferred using PIO or DMA, and sets the corresponding status bit. It is possible to write 20-bit data within a 32-bit register using PIO. In the case of a TX underrun, the HAC will transmit the current TX buffer data until the next data arrives. 25.5.3 DMA
The HAC supports DMA transfer for slots 3 and 4 of both the RX and TX frames. Specify the slot data size for DMA transfer, 16 or 20 bits, with the DMARX16 and DMATX16 bits in HACACR. When the data size is 20 bits, transfer of data slots 3 and 4 requires two local bus access cycles. Since each of the receiver and transmitter has its DMA request, the stereo mode generates a DMA request for slots 3 and 4 separately. The mono mode generates a DMA request for just one slot. When the data size is 16 bits, data from slots 3 and 4 are packed into a single 32-bit quantity (left data and right data are in PCML), which requires only one local bus access cycle. It may be necessary to halt a DMA transfer before the end count is reached, depending on system applications. If so, clear the corresponding DMA bit in HACACR to 0 (DMA disabled). To resume a DMA transfer, reprogram the DMAC and then set the corresponding DMA bit to 1 (DMA enabled). 25.5.4 Interrupts
Interrupts can be used for flag events from the receiver and transmitter. Make the setting for each interrupt in the corresponding interrupt enable register. Interrupts include a request to the CPU to read/write slot data, overrun and underrun. To get the interrupt source, read the status register. Writing 0 to the bit will clear the corresponding interrupt. 25.5.5 Restrictions Related to HACTCR.CMDAMT
When setting a codec register address in HACCSAR, the HACTSR.CMDAMT bit may accidentally be set to 1 despite that the specified address has not yet been transferred to the codec. Take the following measures when accessing a codec register:
Rev. 1.0, 02/03, page 900 of 1294
(1) Writing a codec register address to HACCSAR Write a codec register address to HACCSAR twice with an interval of 100ns. (2) Writing data to a codec register After writing data to a codec register, verify the write data by reading this codec register. If the write is unsuccessful, carry out writing again. (3) Reading from a codec register When HACTSR.CMDAMT is accidentally set to 1, a read access to the codec register is not performed and therefore neither HACRSR.STARY nor HACRSR.STDRY is set to 1 to indicate data reception. If HACRSR.STARY and HACRSR.STDRY stay 0 for a longer time than expected in normal read operation, it should be regarded as timeout. Carry out reading again.
For details of the initialization sequence, see 25.5.6, Initialization Sequence.
Rev. 1.0, 02/03, page 901 of 1294
25.5.6
Initialization Sequence
Figure 25.3 shows an example of the initialization sequence.
START
HAC Cold reset (HACCR = H'0000 0A00)
Start transfer (HACCR=H'0000220)
HAC module initialization
Enable TX/RX (e.g.: Set HACACR to H'85E0 0000; 20-bit DMA, TX slots 1 & 2 atomic control)
Codec ready? (HACCR = H'0000 8200) Yes
No
Set DMAC
*
Set read address to #h'26. (HACCSAR = H'000A 6000)
External codec device initialization
Off-chip codec internal status ADC, DAC, Analog, REF = ready? (HACCSDR = H'0000 00F0)
No
Yes Set read volume and sampling rate (1) HACTSR = H'0000 0000 (2) Set HACCSAR and HACCSDR
Start DMA transfer (Receiver/Transmitter) Note: * Refer to section 11, Direct Memory Access Controller (DMAC).
Figure 25.3 Initialization Sequence
Rev. 1.0, 02/03, page 902 of 1294
Write to codec.
Prerequisite: HACACR.TX12_ATOMIC=1
Set RetryCnt to 0.
Disable interrupts.
Write 0 to HACTSR.CMDAMT. Write 0 to HACTSR.CMDDMT.
Set data in HACCSDR.
Set Addr in HACCSAR.
Wait (90nsSet data in HACCSDR.
Set Addr in HACCSAR.
Disable interrupts.
Clear LoopCnt to 0.
TSR.CMDAMT = 1& TSR.CMDDMT = 1 Yes
No Wait for 1 s. LoopCnt ++
E1 < LoopCnt 1 Yes RetryCnt ++
No
5 < RetryCnt Yes Return Error
No
Notes: E1: Loop count required in the target system (21Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write
Rev. 1.0, 02/03, page 903 of 1294
Read codec.
Input: RegN (address of the codec register to be read)
RegN = Last_Reg? No
Yes
Read_codec_aux (RegV) RegV = H'7C (Vender ID1) Error No Error Yes Last_Reg: Address of the register read last time Dummy read
Read_codec_aux (RegN) : Data acquisition Yes
In continuous reading of registers in some off-chip codec devices, the data in the register previously read may be read again. In such case, take the steps in this flowchart.
Error No Data return
Error
Read_codec_aux
Input: RegN (address of the codec register to be read)
Send_read_request (RegN)
Yes Error No Send_read_request (RegN)
Yes Error No Get_codec_data (RegN) : Data 1 acquisition Yes Error No Get_codec_data (RegN) : Data 2 acquisition Yes Error No Data 2 return Error Dummy processing (Discard the first data)
Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read
Rev. 1.0, 02/03, page 904 of 1294
Send_read_request
Input: RegN (address of the codec register to be read)
Disable interrupts.
Write 0 to HACRSR.STARY.
Set RegN in HACCSAR.
Wait (90nsSet RegN in HACCSAR.
Enable interrupts
WaitLoop_CMDAMT
Error No Return
Yes
Error
Get_codec_data
Input: RegN (address of the codec register to be read)
Clear LoopCnt2 to 0.
WaitLoop_RSR
Error No Assign HACCSAR read value to Addr.
Yes
Error
Addr (R) = RegN? Yes Assign HACCSDR read value to DataT.
No Wait for 5 s. LoopCnt2 ++
E2 < LoopCnt 2 Yes DataT is returned. Error
No
Note: E2: Loop count required in the target system (13Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (cont)
Rev. 1.0, 02/03, page 905 of 1294
WaitLoop_CMDAMT
Clear LoopCnt3 to 0.
HACTSR.CMDAMT=1 Yes Write 0 to HACTSR.CMDAMT.
No Wait for 1 s. LoopCnt3 ++
Return
E3 < LoopCnt 3 Yes Error
No
WaitLoop_RSR
Clear LoopCnt4 to 0.
HACRSR.STARY=1 & HACRSR.STDRY=1 Yes Write 0 to HACRSR.START. Write 0 to HACRSR.STDRY.
No Wait for 1 s. LoopCnt4 ++
E4 < LoopCnt 4 Return Yes Error Note: E3, E4: Loop count required in the target system (21No
Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (cont)
Rev. 1.0, 02/03, page 906 of 1294
25.5.7
Power-Down Mode
It is possible to stop the supply of clock to the HAC using the CSTP15 and CSTP16 bits in CLKSTP00, which is a register used in power-down modes. To cancel module standby mode and resume the supply of clock to the HAC, write 1 to the corresponding bits in CLKSTPCLR00. It enables all accesses to the HAC. To place the HAC into the power-down mode, take the following steps: 1. Check that all data transfers have ended. Also check that the transmit buffer is empty and the receive buffer has been read out to be empty. 2. Disable all DMA requests and interrupt requests. 3. Place the codec into power-down mode. 4. Write 1 to the CSTP15 and CSTP16 bits in CLKSTP00. 25.5.8 Notes
The HAC_SYNC signal is generated by the HAC to indicate the position of slot 0 within a frame. When using two channels of the HAC simultaneously, connect the HAC_RES pin to the reset pins on both of the connected codecs. 25.5.9 Reference
AC'97 Component Specification, Revision 2.1
Rev. 1.0, 02/03, page 907 of 1294
Rev. 1.0, 02/03, page 908 of 1294
Section 26 Multimedia Card Interface (MMCIF)
This LSI supports a multimedia card interface (MMCIF). The MMC mode interface can be utilized. The MMCIF is a clock-synchronous serial interface that transmits/receives data that is distinguished in terms of command and response. A number of commands/responses are predefined in the multimedia card. As the MMCIF specifies a command code and command type/response type upon the issuance of a command, commands extended by the secure multimedia card (Secure-MMC) and additional commands can be supported in the future within the range of combinations of currently defined command types/response types.
26.1
Features
The MMCIF has the following features: * Interface that complies with The MultiMediaCard System Specification Version 2.11 * Supports MMC mode * 20-Mbps bit rate (max.) for the card interface at a peripheral operating clock of 20 MHz * Incorporates 64 data-transfer FIFOs of 16 bits * Supports DMA transfer * Four interrupt sources FIFO empty/full, command/response/data transfer complete, transfer error, and FIFO ready * Interface via the MCCLK output (transfer clock output) pin, the MCCMD input/output (command output/response input) pin, and the MCDAT input/output (data input/output) pin
Rev. 1.0, 02/03, page 909 of 1294
Figure 26.1 shows a block diagram of the MMCIF.
MMCIF
MMC_D FIFO Peripheral bus Data transmission/ reception control
Internal bus interface
Command transmission/ response reception control
MMC_CMD
intreq_mmc[3:0]
Interrupt control
MMC mode control
Card clock generator
MMC_CLK
Figure 26.1 Block Diagram of MMCIF
26.2
Input/Output Pins
Table 26.1 summarizes the pins of the MMCIF. Table 26.1 Pin Configuration
Symbol MCCLK MCCMD MCDAT I/O Output Input/Output Input/Output Function Card clock output Command output/response input Data input/output
Note: For insertion/detachment of a card or for signals switching over between open-drain and CMOS modes, use ports of this LSI.
Rev. 1.0, 02/03, page 910 of 1294
26.3
Register Descriptions
The MMCIF has the following registers. For more information on addresses of registers and register states in each processing, refer to section 32, List of Registers. Table 26.2 Register Configuration (1)
Register Name Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Command start register Operation control register Card status register Interrupt control register 0 Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register Command timeout control register Abbrev. CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 R/W R/W R/W R/W R/W R/W -- P4 Address H'FE50 0000 H'FE50 0001 H'FE50 0002 H'FE50 0003 H'FE50 0004 H'FE50 0005 H'FE50 0006 H'FE50 000A H'FE50 000B H'FE50 000C H'FE50 000D H'FE50 000E H'FE50 000F H'FE50 0010 H'FE50 0011 H'FE50 0014 H'FE50 0016 H'FE50 0018 H'FE50 0019 H'FE50 0020 H'FE50 0021 H'FE50 0022 H'FE50 0023 H'FE50 0024 H'FE50 0025 H'FE50 0026 H'FE50 0027 Area 7 Address Size H'1E50 0000 H'1E50 0001 H'1E50 0002 H'1E50 0003 H'1E50 0004 H'1E50 0005 H'1E50 0006 H'1E50 000A H'1E50 000B H'1E50 000C H'1E50 000D H'1E50 000E H'1E50 000F H'1E50 0010 H'1E50 0011 H'1E50 0014 H'1E50 0016 H'1E50 0018 H'1E50 0019 H'1E50 0020 H'1E50 0021 H'1E50 0022 H'1E50 0023 H'1E50 0024 H'1E50 0025 H'1E50 0026 H'1E50 0027 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
CMDSTRT R/W OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Transfer byte number count register TBCR Mode register Command type register Response type register Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 MODER CMDTYR RSPTYR RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7
Rev. 1.0, 02/03, page 911 of 1294
Register Name Response register 8 Response register 9 Response register 10 Response register 11 Response register 12 Response register 13 Response register 14 Response register 15 Response register 16 Data timeout register Data register FIFO pointer clear register DMA control register Interrupt control register 2 Interrupt status register 2 Receive data timing select register
Abbrev. RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 DTOUTR DR FIFOCLR DMACR INTCR2 INTSTR2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W
P4 Address H'FE50 0028 H'FE50 0029 H'FE50 002A H'FE50 002B H'FE50 002C H'FE50 002D H'FE50 002E H'FE50 002F H'FE50 0030 H'FE50 0032 H'FE50 0040 H'FE50 0042 H'FE50 0044 H'FE50 0046 H'FE50 0048 H'FE50 004A
Area 7 Address Size H'1E50 0028 H'1E50 0029 H'1E50 002A H'1E50 002B H'1E50 002C H'1E50 002D H'1E50 002E H'1E50 002F H'1E50 0030 H'1E50 0032 H'1E50 0040 H'1E50 0042 H'1E50 0044 H'1E50 0046 H'1E50 0048 H'1E50 004A 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 8
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
RDTIMSEL R/W
Table 26.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'00 H'00 H'00 H'00 H'00 H'00 Manual Reset by RESET Pin/WDT/ Multiple Exception H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0x H'00 Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Register Name Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Command start register Operation control register Card status register Interrupt control register 0
Abbrev. CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5
CMDSTRT H'00 OPCR CSTR INTCR0 H'00 H'0x H'00
Rev. 1.0, 02/03, page 912 of 1294
Register Name Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register Command timeout control register
Abbrev. INTCR1 INTSTR0 INTSTR1 CLKON CTOCR
Power-on Reset by RESET Pin/WDT/ H-UDI H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFF H'xxxx H'00 H'00
Manual Reset by RESET Pin/WDT/ Multiple Exception H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'FFFF H'xxxx H'00 H'00
Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Transfer byte number count register TBCR Mode register Command type register Response type register Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 Response register 8 Response register 9 Response register 10 Response register 11 Response register 12 Response register 13 Response register 14 Response register 15 Response register 16 Data timeout register Data register FIFO pointer clear register DMA control register MODER CMDTYR RSPTYR RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 DTOUTR DR FIFOCLR DMACR
Rev. 1.0, 02/03, page 913 of 1294
Register Name Interrupt control register 2 Interrupt status register 2 Receive data timing select register
Abbrev. INTCR2 INTSTR2
Power-on Reset by RESET Pin/WDT/ H-UDI H'00 H'0x
Manual Reset by RESET Pin/WDT/ Multiple Exception H'00 H'0x H'00
Standby by Sleep Software/ by Sleep Each Instruction/ by Deep Sleep Hardware Module Retained Retained Retained * Retained Retained Retained
RDTIMSEL H'00
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin.
26.3.1
Mode Register (MODER)
MODER is an 8-bit readable/writable register that specifies the MMCIF operating mode. The following sequence should be repeated when the MMCIF uses the multimedia card: Send a command, wait for the end of the command sequence and the end of the data busy state, and send a next command. The series of operations from command sending, command response reception, data transmission/reception, and data response reception is called as the command sequence. The command sequence starts from sending a command by setting the START bit in CMDSTRT to 1, and ends when all necessary data transmission/reception and response reception have been completed. The multimedia card supports the data busy state such that only the specific command is accepted to write/erase data to/from the flash memory in the card during command sequence execution and after command sequence execution has ended. The data busy state is indicated by a low level output from the card side to the MCDAT pin.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 MODE 0 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Operating Mode Specifies the MMCIF operating mode. 0: Operates in MMC mode 1: Setting prohibited
0
MODE
0
R/W
Rev. 1.0, 02/03, page 914 of 1294
26.3.2
Command Type Register (CMDTYR)
CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits TY4 to TY2 specify the additional settings. All of bits TY4 to TY2 should be cleared to 0 or only one of them should be set to 1. Bits TY4 to TY2 can only be set to 1 if the corresponding settings in TY1 and TY0 allow that setting.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 TY4 0 R/W 3 TY3 0 R/W 2 TY2 0 R/W 1 TY1 0 R/W 0 TY0 0 R/W
Bit 7 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Type 4 Set this bit to 1 when specifying the CMD12 command. Bits TY1 and TY0 should be set to 00. Type 3 Set this bit to 1 when specifying stream transfer. Bits TY1 and TY0 should be set to 01 or 10. The command sequence of the stream transfer specified by this bit ends when it is aborted by the CMD12 command.
4
TY4
0
R/W
3
TY3
0
R/W
2
TY2
0
R/W
Type 2 Set this bit to 1 when specifying multiblock transfer. Bits TY1 and TY0 should be set to 01 or 10. The command sequence of the multiblock transfer specified by this bit ends when it is aborted by the CMD12 command.
1 0
TY1 TY0
0 0
R/W R/W
Types 1 and 0 These bits specify the existence and direction of transfer data. 00: A command without data transfer 01: A command with read data reception 10: A command with write data transmission 11: Setting prohibited
Rev. 1.0, 02/03, page 915 of 1294
26.3.3
Response Type Register (RSPTYR)
RSPTYR is an 8-bit readable/writable register that specifies command format in conjunction with CMDTYR. Bits RTY2 to RTY0 specify the number of response bytes, and bits RTY5 and RTY4 specify the additional settings.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 4 3 0 R 2 1 0
RTY5 RTY4 0 R/W 0 R/W
RTY2 RTY1 RTY0 0 R/W 0 R/W 0 R/W
Bit 7, 6
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Response Type 5 Sets data busy status from the MMC card. 0: A command without data busy 1: A command with data busy
5
RTY5
0
R/W
4
RTY4
0
R/W
Response Type 4 Specifies that the command response CRC is checked through CRC7. Bits RTY2 to RTY0 should be set to 100 or 101. 0: Does not check CRC through CRC7 1: Checks CRC through CRC7
3
0
R
Reserved These bits are always read as 0. The write value should always be 0. Response Types 2 to 0 These bits specify the number of command response bytes. 000: A command needs no command response. 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: A command needs 6-byte command responses. Specified by R1, R1b, R3, R4, and R5 responses. 101: A command needs a 17-byte command response. Specified by R2 response. 110: Setting prohibited 111: Setting prohibited
2 1 0
RTY2 RTY1 RTY0
0 0 0
R/W R/W R/W
Rev. 1.0, 02/03, page 916 of 1294
Table 26.3 summarizes the correspondence between the commands described in the MultiMediaCard System Specification Version 2.11 and the settings of the CMDTYR and RSPTYR registers. Table 26.3 Correspondence between Commands and Settings of CMDTYR and RSPTYR
CMD INDEX CMD0 CMD1 CMD2 CMD3 CMD4 CMD7 CMD9 CMD10 CMD11 CMD12 CMD13 CMD15 CMD16 CMD17 CMD18 CMD20 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMDTYR Abbreviation GO_IDLE_STATE SEND_OP_COND ALL_SEND_CID SET_RELATIVE_ADDR SET_DSR
SELECT/DESELECT_CARD
RSPTYR 2 3 4
2 to 0
resp R3 R2 R1 R1b R2 R2 R1 R1b R1 R1 R1 R1 R1 R1 R1 R1 R1 R1b R1b R1 R1 R1 R1
1 and 0
4
5
00 00 00 00 00 00 00 00 01 00 00 00 00 01 01 10 10 10 10 10 00 00 01 00 00 00 1 1 1 1 1
000 100 101 100 000 100 101 101 100 100 100 000 100 100 100 100 100 100 100 100 100 100 100 100 100 100 * * * * * * * * * * * * * * 1 1 * * * 1 * 1 *
SEND_CSD SEND_CID
READ_DAT_UNTIL_STOP
STOP_TRANSMISSION SEND_STATUS GO_INACTIVE_STATE SET_BLOCKLEN READ_SINGLE_BLOCK
READ_MULTIPLE_BLOCK WRITE_DAT_UNTIL_STOP
WRITE_BLOCK
WRITE_MULTIPLE_BLOCK
PROGRAM_CID PROGRAM_CSD SET_WRITE_PROT CLR_WRITE_PROT SEND_WRITE_PROT TAG_SECTOR_START TAG_SECTOR_END UNTAG_SECTOR
Rev. 1.0, 02/03, page 917 of 1294
CMD INDEX CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD55 CMD56
CMDTYR Abbreviation TAG_ERASE_GROUP_ START TAG_ERASE_GROUP_ END UNTAG_ERASE_GROUP ERASE FAST_IO GO_IRQ_STATE LOCK_UNLOCK APP_CMD GEN_CMD resp R1 R1 R1 R1b R4 R5 R1b R1 R1b
1 and 0
RSPTYR 2 3 4
2 to 0
4 * * * * * * * * *
5
00 00 00 00 00 00 10 00 10 or 11
100 100 100 100 100 100 100 100 100
1
1
1
Notes: * Command response CRC can be checked. 1. A blank means value 0.
Rev. 1.0, 02/03, page 918 of 1294
26.3.4
Transfer Byte Number Count Register (TBCR)
TBCR is an 8-bit readable/writable register that specifies the number of bytes to be transferred (block size) for each single block transfer command. TBCR specifies the number of data block bytes not including the start bit, end bit, and CRC. The multiblock transfer command corresponds to the number of bytes of each data block. This setting is ignored by the stream transfer command.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 C3 0 R/W 2 C2 0 R/W 1 C1 0 R/W 0 C0 0 R/W
Bit 7 to 4 3 2 1 0
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Transfer Data Block Size Four or more bytes should be set before executing a command with data transfer. 0000: 1 byte (for forced erase) 0001: Setting prohibited 0010: 4 bytes 0011: 8 bytes 0100: 16 bytes 0101: 32 bytes 0110: 64 bytes 0111: 128 bytes 1000: 256 bytes 1001: 512 bytes 1010: 1024 bytes 1011: 2048 bytes 1100 to 1111: Setting prohibited
CS3 CS2 CS1 CS0
0 0 0 0
R/W R/W R/W R/W
Rev. 1.0, 02/03, page 919 of 1294
26.3.5
Command Registers 0 to 5 (CMDR0 to CMDR5)
The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table 26.4, and the command is transmitted when the START bit in CMDSTRT is set to 1. Table 26.4 CMDR Configuration
Register CMDR0 CMDR1 to CMDR4 CMDR5 Contents Start bit, Host bit, and command index Command argument CRC and End bit Operation Write command indexes. Clear the Start bit to 0 and set the Host bit to 1. Write command arguments. Setting of CRC is unnecessary (automatic calculation). End bit is fixed to 1 and its setting is unnecessary.
* CMDR0
Bit: Initial value: R/W: 7 Start 0 R/W 6 Host 0 R/W 0 R/W 0 R/W 5 4 3 INDEX 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0
Bit 7 6 5 to 0
Bit Name Start Host INDEX
Initial Value 0 0 All 0
R/W R/W R/W R/W
Description Start bit (This bit should be cleared to 0) Transmission bit (This bit should be set to 1) Command indexes
* CMDR1 to CMDR4
Bit: Initial value: R/W: 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Bit 7 to 0
Bit Name --
Initial Value All 0
R/W R/W
Description Command arguments See specifications for the MMC card.
Rev. 1.0, 02/03, page 920 of 1294
* CMDR5
Bit: Initial value: R/W: 7 6 5 CRC 0 R 0 R 0 R 0 R 0 R 0 R 0 R 4 3 2 1 0 End 0 R
Bit 7 to 1 0
Bit Name CRC End
Initial Value All 0 0
R/W R R
Description These bits are always read as 0. The write value should always be 0. This bit is always read as 0. The write value should always be 0.
26.3.6
Response Registers 0 to 16 (RSPR0 to RSPR16)
RSPR0 to RSPR16 are command response registers, which are seventeen 8-bit registers. The number of command response bytes differs according to the command. The number of command response bytes can be specified by RSPTYR in the MMCIF. The command response is shifted-in from bit 0 in RSPR16, and shifted to the number of command response bytes x 8 bits. Table 26.5 summarizes the correspondence between the number of command response bytes and valid RSPR register.
Rev. 1.0, 02/03, page 921 of 1294
Table 26.5 Correspondence between Command Response Byte Number and RSPR
MMC Mode Response RSPR registers RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 6 bytes (R1, R1b, R3, R4, R5) 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 17 bytes (R2) 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte 17th byte
RSPR0 to RSPR16 are simple shift registers. A command response that has been shifted in is not automatically cleared, and it is continuously shifted until it is shifted out from bit 7 in RSPR0. To clear unnecessary bytes to H'00, write an arbitrary value to each RSPR. Clearing an RSPR is completed two transfer clock cycles after an arbitrary value is written to the RSPR. * RSPR0 to RSPR16
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0 RSPR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Rev. 1.0, 02/03, page 922 of 1294
Bit 7 to 0
Bit Name RSPR
Initial Value All 0
R/W R/W
Description These bits are cleared to H'00 by writing an arbitrary value. RSPR0 to RSPR16 comprise a continuous 17-byte shift register.
26.3.7
Command Start Register (CMDSTRT)
CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission, representing the start of a command sequence. The following operations should have been completed before the command sequence starts. * Analysis of prior command response, clearing the command response register write if necessary * Analysis/transfer of receive data of prior command if necessary * Preparation of transmit data of the next command if necessary * Setting of CMDTYR, RSPTYR, and TBCR * Setting of CMDR0 to CMDR4 The CMDR0 to CMDR4, CMDTYR, RSPTYR, and TBCR registers should not be changed until command transmission has ended (the CWRE flag in CSTR has been set to 1). Command sequences are controlled by the sequencers in both the MMCIF side and the MMC card side. Normally, these operate synchronously. However, if an error occurs or a command is aborted, these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit in OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command sequence should be started only after the end of the command sequence on both the MMCIF and card sides is confirmed.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 START 0 R/W
Bit 7 to 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Starts command transmission when 1 is written. This bit is automatically cleared. When 0 is written to this bit, its previous value is retained.
0
START
0
R/W
Rev. 1.0, 02/03, page 923 of 1294
26.3.8
Operation Control Register (OPCR)
OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or continues data transfer.
Bit: 7
CMD OFF
6 0 R
5
RD_ CONTI
4
DATAEN
3 0 R
2 0 R
1 0 R
0 0 R
Initial value: R/W:
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name CMDOFF
Initial Value 0
R/W R/W
Description Command Off Aborts all command operations (MMCIF command sequence) when 1 is written after a command is transmitted. This bit is then cleared automatically. Write enabled period: From command transmission completion to command sequence end Write of 0: Operation is not affected. Write of 1: Command sequence is forcibly aborted.* * The transfer clock output resumes if the transfer clock has been halted during the command sequence.
6
--
0
R
Reserved This bit is always read as 0. The write value should always be 0. Read Continue Transfer clock output and read data reception are resumed when 1 is written while the transfer clock has been halted by FIFO full or termination of block reading in multiblock read. This bit is cleared automatically when 1 is written and reading is resumed Write enabled period: While MCCLK for read data reception is halted Write of 0: Operation is not affected. Write of 1: Resumes MCCLK output and read data reception.
5
RD_ CONTI
0
R/W
Rev. 1.0, 02/03, page 924 of 1294
Bit 4
Bit Name DATAEN
Initial Value 0
R/W R/W
Description Data Enable Starts write data transmission by a command with write data. This bit is cleared automatically when 1 is written. Resumes transfer clock output and write data transmission when the transfer clock has been halted by FIFO empty or termination of one block writing in multiblock write. Write enabled period: (1) after receiving a response to a command with write data, (2) while transfer clock is halted by FIFO empty, (3) when one block writing in multiblock write is terminated Write of 0: Operation is not affected. Write of 1: Starts or resumes transfer clock output and write data transmission.
3 to 0
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Some states of the multimedia card cause command sequence on the multimedia card side to stop. Table 26.6 shows the card states in which a command sequence is halted. In this case, the command sequence should also be aborted by setting the CMDOFF bit to 1 on the MMCIF side. Table 26.6 Card States in which Command Sequence is Halted
Card Operating Mode MMC mode Command response Error Status When the error detection bit in the card status (32 bits) in the command response data transmitted by the card is set. When the CRCERI bit is set due to an error in the CRC status to be transmitted from the card is set while block data is transmitted to the card.
Data status
In write data transmission, the contents of the command response and data response should be analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK) output should be temporarily halted by FIFO full/empty, and it should be resumed when the preparation has been completed.
Rev. 1.0, 02/03, page 925 of 1294
In multiblock transfer, the transfer clock output should be temporarily halted at every block break to select either to continue to the next block or to abort the multiblock transfer command by issuing the CMD12 command, and the transfer clock output should be resumed. To continue to the next block, the RD_CONTI and DATAEN bits should be set to 1. To issue the CMD12 command, the CMDOFF bit should be set to 1 to abort the command sequence on the MMCIF side. Note: The FIFO full interrupt source must be cleared (FIFO data read) only after five or more transfer clock cycles have been passed since the interrupt occurred. 26.3.9 Command Timeout Control Register (CTOCR)
CTOCR specifies the period to generate a timeout for the command response. The counter (CTOUTC), to which the peripheral bus does not have access, counts the transfer clock to monitor the command timeout. The initial value of CTOUTC is 0, and CTOUTC starts counting the transfer clock from the start of command transmission. CTOUTC is cleared and stops counting the transfer clock when command response reception has been completed, or when the command sequence has been aborted by setting the CMDOFF bit to 1. When the command response cannot be received, CTOUTC continues counting the transfer clock, and enters the command timeout error state when the number of transfer clock cycles reaches the number specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is set. As CTOUTC continues counting transfer clock, the CTERI flag setting condition is repeatedly generated. To perform command timeout error handling, the command sequence should be aborted by setting the CMDOFF bit to 1, and then the CTERI flag should be cleared to prevent extra-interrupt generation.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0
CTSEL1 CTSEL0
0 R/W
0 R/W
Bit 7 to 2
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 926 of 1294
Bit 1 0
Bit Name CTSEL1 CTSEL0
Initial Value 0 0
R/W R/W R/W
Description Command Timeout Select 00: 128 transfer clock cycles from command transmission completion to response reception completion 01: 256 transfer clock cycles from command transmission completion to response reception completion 10: Setting prohibited 11: Setting prohibited
Note: If R2 response (17-byte command response) is requested and CTSEL0 is cleared to 0, a timeout is generated during response reception. Therefore, set CTSEL0 to 1.
26.3.10 Data Timeout Register (DTOUTR) DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor the data timeout. The prescaler always counts the peripheral clock, and outputs a count pulse for every 10,000 peripheral clock cycles. The initial value of DTOUTC is 0, and DTOUTC starts counting the prescaler output from the start of the command sequence. DTOUTC is cleared when the command sequence has ended, or when the command sequence has been aborted by setting the CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output. When the command sequence does not end, DTOUTC continues counting the prescaler output, and enters the data timeout error states when the number of prescaler outputs reaches the number specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1 is set. As DTOUTC continues counting prescaler output, the DTERI flag setting condition is repeatedly generated. To perform data timeout error handling, the command sequence should be aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent extra-interrupt generation. For a command with data busy status, data timeout cannot be monitored since the command sequence is terminated before entering the data busy state. Timeout in the data busy state should be monitored by firmware.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTOUTR 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
Rev. 1.0, 02/03, page 927 of 1294
Bit 15 to 0
Bit Name DTOUTR
Initial Value All 1
R/W R/W
Description Data Timeout Time/10,000 Data timeout time: Peripheral clock cycle x DTOUTR setting value x 10,000.
26.3.11 Card Status Register (CSTR) CSTR indicates the MMCIF status during command sequence execution.
Bit: 7
BUSY
6
FIFO_ FULL
5
FIFO_ EMPTY
4
CWRE
3
DTBUSY
2
DTBUSY _TU
1 0 R
0
REQ
Initial value: R/W:
0 R
0 R
0 R
0 R
0 R
R
0 R
Bit 7
Bit Name BUSY
Initial Value 0
R/W R
Description Command Busy Indicates command execution status. When the CMDOFF bit in OPCR is set to 1, this bit is cleared to 0 because the MMCIF command sequence is aborted. 0: Idle state waiting for a command, or data busy state 1: Command sequence execution in progress
6
FIFO_ FULL
0
R
FIFO Full This bit is set to 1 when the FIFO becomes full while data is being received from the card, and cleared to 0 when RD_CONTI is set to 1 or the command sequence is completed. Indicates whether the FIFO is empty or not. 0: The FIFO is empty. 1: The FIFO is full.
5
FIFO_ EMPTY
0
R
FIFO Empty This bit is set to 1 when the FIFO becomes empty while data is being sent to the card, and cleared to 0 when DATA_EN is set to 1 or the command sequence is completed. Indicates whether the FIFO holds data or not. 0: The FIFO includes data. 1: The FIFO is empty.
Rev. 1.0, 02/03, page 928 of 1294
Bit 4
Bit Name CWRE
Initial Value 0
R/W R
Description Command Register Write Enable Indicates whether the CMDR command is being transmitted or has been transmitted. 0: The CMDR command has been transmitted, or the START bit in CMDSTRT has not been set yet, so the new command can be written. 1: The CMDR command is waiting for transmission or is being transmitted. If a new command is written, a malfunction will result.
3
DTBUSY
0
R
Data Busy Indicates command execution status. Indicates that the card is in the busy state after the command sequence of a command without data transfer which includes the busy state in the response, or a command with write data has been ended. 0: Idle state waiting for a command, or command sequence execution in progress 1: Card is in the data busy state after command sequence termination.
2
DTBUSY_ TU
--
R
Data Busy Pin Status Indicates the MCDAT pin level. By reading this bit, the MCDAT level can be monitored. 0: A low level is input to the MCDAT pin. 1: A high level is input to the MCDAT pin.
1
--
0
R
Reserved This bit is always read as 0. The write value should always be 0. Interrupt Request Indicates whether an interrupt is requested or not. An interrupt request is the logical OR of the INTSTR0 and INTSTR1 flags. The INTSTR0 and INTSTR1 flags set is controlled by the enable bits in INTCR0 and INTCR1. 0: No interrupt requested. 1: Interrupt requested.
0
REQ
0
R
Rev. 1.0, 02/03, page 929 of 1294
26.3.12 Interrupt Control Registers 0 to 2 (INTCR0 to INTCR2) The INTCR registers enable or disable interrupts. * INTCR0
Bit: 7 FEIE Initial value: R/W: 0 R/W 6 5 4 3 2 1 DBS YIE 0 R/W 0 0 R FFIE DRPIE DTIE CRPIE CMDIE 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 7
Bit Name FEIE
Initial Value 0
R/W R/W
Description FIFO Empty Interrupt Enable 0: Disables FIFO empty interrupt (disables FEI flag setting). 1. Enables FIFO empty interrupt (enables FEI flag setting).
6
FFIE
0
R/W
FIFO Full Interrupt Enable 0: Disables FIFO full interrupt (disables FFI flag setting). 1: Enables FIFO full interrupt (enables FFI flag setting).
5
DRPIE
0
R/W
Data Response Interrupt Enable 0: Disables data response interrupt (disables DPRI flag setting). 1: Enables data response interrupt (enables DPRI flag setting).
4
DTIE
0
R/W
Data Transfer End Interrupt Enable 0: Disables data transfer end interrupt (disables DTI flag setting). 1: Enables data transfer end interrupt (enables DTI flag setting).
3
CRPIE
0
R/W
Command Response Receive End Interrupt Enable 0: Disables command response receive end interrupt (disables CRPI flag setting). 1: Enables command response receive end interrupt (enables CRPI flag setting).
2
CMDIE
0
R/W
Command Transmit End Interrupt Enable 0: Disables command transmit end interrupt (disables CMDI flag setting). 1: Enables command transmit end interrupt (enables CMDI flag setting).
Rev. 1.0, 02/03, page 930 of 1294
Bit 1
Bit Name DBSYIE
Initial Value 0
R/W R/W
Description Data Busy End Interrupt Enable 0: Disables data busy end interrupt (disables DBSYI flag setting). 1: Enables data busy end interrupt (enables DBSYI flag setting).
0
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
* INTCR1
Bit: 7 6 5 INTR Q0E 0 R/W 4 0 R 3 0 R 2 1 INTR INTR Q2E Q1E Initial value: 0 0 R/W: R/W R/W CRCE DTE RIE RIE 0 0 R/W R/W 0 CTE RIE 0 R/W
Bit 7
Bit Name INTRQ2E
Initial Value 0
R/W R/W
Description MMCI2 Interrupt Enable 0: Disables MMCI2 interrupt. 1: Enables MMCI2 interrupt.
6
INTRQ1E
0
R/W
MMCI1 Interrupt Enable 0: Disables MMCI1 interrupt. 1: Enables MMCI1 interrupt.
5
INTRQ0E
0
R/W
MMCI0 Interrupt Enable 0: Disables MMCI0 interrupt. 1: Enables MMCI0 interrupt.
4, 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. CRC Error Interrupt Enable 0: Disables CRC error interrupt (disables CRCERI flag setting). 1: Enables CRC error interrupt (enables CRCERI flag setting).
2
CRCERIE
0
R/W
Rev. 1.0, 02/03, page 931 of 1294
Bit 1
Bit Name DTERIE
Initial Value 0
R/W R/W
Description Data Timeout Error Interrupt Enable 0: Disables data timeout error interrupt (disables DTERI flag setting). 1: Enables data timeout error interrupt (enables DTERI flag setting).
0
CTERIE
0
R/W
Command Timeout Error Interrupt Enable 0: Disables command timeout error interrupt (disables CTERI flag setting). 1: Enables command timeout error interrupt (enables CTERI flag setting).
* INTCR2
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0
FRDYIE
0 R/W
Bit 7 to 1 0
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. FIFO Ready Interrupt Enable 0: Disables FIFO ready interrupt (disables flag setting). 1: Enables FIFO ready interrupt (enables flag setting).
FRDYIE
0
R/W
26.3.13 Interrupt Status Registers 0 to 2 (INTSTR0 to INTSTR2) The INTSTR registers enable or disable MMCIF interrupts MMCI3 to MMCI0. * INTSTR0
Bit: Initial value: R/W: 7 FEI 0 R/W 6 FFI 0 R/W 5 DRPI 0 R/W 4 DTI 0 R/W 3 2 1 0 0 R CRPI CMDI DBSYI 0 R/W 0 R/W 0 R/W
Rev. 1.0, 02/03, page 932 of 1294
Bit 7
Bit Name FEI
Initial Value 0
R/W R/W
Description FIFO Empty Interrupt 0: No interrupt [Clearing condition] Write 0 after reading FEI = 1. 1: Interrupt requested [Setting condition] When FIFO becomes empty while FEIE = 1 and data is being transmitted (when the FIFO_EMPTY bit in CSTR is set)
Interrupt output MMCI0
6
FFI
0
R/W
FIFO Full Interrupt 0: No interrupt [Clearing condition] Write 0 after reading FFI = 1. 1: Interrupt requested [Setting condition] When FIFO becomes full while FFIE = 1 and data is being received (when the FIFO_FULL bit in CSTR is set)
MMCI0
5
DRPI
0
R/W
Data Response Interrupt 0: No interrupt [Clearing condition] Write 0 after reading DRPI = 1. 1: Interrupt requested [Setting condition] When the CRC status is received while DRPIE = 1.
MMCI1
4
DTI
0
R/W
Data Transfer End Interrupt 0: No interrupt [Clearing condition] Write 0 after reading DTI = 1. 1: Interrupt requested [Setting condition] When the number of bytes of data transfer specified in TBCR ends while DTIE = 1.
MMCI1
Rev. 1.0, 02/03, page 933 of 1294
Bit 3
Bit Name CRPI
Initial Value 0
R/W R/W
Description Command Response Receive End Interrupt 0: No interrupt [Clearing condition] Write 0 after reading CRPI = 1. 1: Interrupt requested [Setting condition] When command response reception ends while CRPIE = 1.
Interrupt output MMCI1
2
CMDI
0
R/W
Command Transmit End Interrupt 0: No interrupt [Clearing condition] Write 0 after reading CMDI = 1. 1: Interrupt requested [Setting condition] When command transmission ends while CMDIE = 1. (When the CWRE bit in CSTR is cleared.)
MMCI1
1
DBSYI
0
R/W
Data Busy End Interrupt 0: No interrupt [Clearing condition] Write 0 after reading DBSYI = 1. 1: Interrupt requested [Setting condition] When data busy state is canceled while DBSYIE = 1. (When the DTBUSY bit in CSTR is cleared.)
MMCI1
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 934 of 1294
* INTSTR1
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 1 0 CRC DTERI CTERI ERI 0 0 0 R/W R/W R/W
Bit 7 to 3
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. CRC Error Interrupt 0: No interrupt [Clearing condition] Write 0 after reading CRCERI = 1. 1: Interrupt requested [Setting condition] When a CRC error for command response or receive data or a CRC status error for transmit data response is detected while CRCERIE = 1. For the command response, CRC is checked when the RTY4 in RSPTYR is enabled.
Interrupt outputs --
2
CRCERI
0
R/W
MMCI2
1
DTERI
0
R/W
Data Timeout Error Interrupt 0: No interrupt [Clearing condition] Write 0 after reading DTERI = 1. 1: Interrupt requested [Setting condition] When a data timeout error specified in DTOUTR occurs while DTERIE = 1.
MMCI2
0
CTERI
0
R/W
Command Timeout Error Interrupt 0: No interrupt [Clearing condition] Write 0 after reading CTERI = 1. 1: Interrupt requested [Setting condition] When a command timeout error specified in TOCR occurs while CTERIE = 1.
MMCI2
Rev. 1.0, 02/03, page 935 of 1294
* INTSTR2
Bit: 7 Initial value: R/W: 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 FRDY FRDYI _TU 0 R R/W
Bit 7 to 2
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. FIFO Ready Flag Regardless of set values of DMAEN and FRDYIE, this bit is read as 0 when FIFO data amount matches the condition set in DMACR[2:0], and otherwise, read as 1. FIFO Ready Interrupt 0: No interrupt [Clearing condition] Write 0 after reading FRDYI = 1. 1: Interrupt requested [Setting condition] When remained FIFO data does not match the assert condition set in DMACR while DMAEN = 1 and FRDYIE = 1. Note: FRDYI will be set on the setting condition after clearing. To clear it, disable the flag setting by FRDYIE in INTCR2.
Interrupt outputs
1
FRDY _TU
R
0
FRDYI
0
R/W
MMCI3
Rev. 1.0, 02/03, page 936 of 1294
26.3.14 Transfer Clock Control Register (CLKON) CLKON controls the transfer clock frequency and clock ON/OFF. Bits CSEL2 to CSEL0 must be set to 100 for the peripheral clock to be 20-MHz in order to achieve a 20-Mbps transfer clock in the MMCIF. At this time, bits CSEL2 to CSEL0 should be set to 000 for the 200-kbps transfer clock in Card Identification Mode in MMC mode. In a command sequence, do not perform clock ON/OFF or frequency modification.
Bit: Initial value: R/W: 7
CLKON
6 0 R
5 0 R
4 0 R
3 0 R
2
1
0
CSEL2 CSEL1 CSEL0
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name CLKON
Initial Value 0
R/W R/W
Description Clock On 0: Fixes the transfer clock output from the MCCLK pin to low level. 1: Outputs the transfer clock from the MCCLK pin.
6 to 3
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Transfer Clock Frequency Select 000: Uses the 1/100-divided peripheral clock as a transfer clock. 001: Uses the 1/8-divided peripheral clock as a transfer clock. 010: Uses the 1/4-divided peripheral clock as a transfer clock. 011: Uses the 1/2-divided peripheral clock as a transfer clock. 100: Use the peripheral clock as a transfer clock. 101 to 111: Setting prohibited
2 1 0
CSEL2 CSEL1 CSEL0
0 0 0
R/W R/W R/W
Rev. 1.0, 02/03, page 937 of 1294
26.3.15 Data Register (DR) DR is a register for reading/writing FIFO data. Word/byte access is enabled to addresses of this register.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 DR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0
Bit 15 to 0
Bit Name DR
Initial Value --
R/W R/W
Description Register for reading/writing FIFO data. Word/byte access is enabled. When DR is accessed in words, the upper and lower bytes are transmitted or received in that order. Word access and byte access can be done in random order. However, (DR address + 1) cannot be accessed in bytes.
The following shows examples of DR access. When data is written to DR in the following steps 1 to 4, the transmit data is stored in the FIFO as shown in figure 26.2. 1. Write word data H'0123 to DR. 2. Write byte data H'45 to DR. 3. Write word data H'6789 to DR. 4. Write byte data H'AB to DR. When the receive data is stored in the FIFO as shown in figure 26.2 (for example, after data is started to be received while the FIFO is empty and data is received in the order of H'01, H'23, ..., H'AB), data can be read from DR in the following steps 5 to 8. 5. Read byte data H'01 from DR. 6. Read word data H'2345 from DR. 7. Read byte data H'67 from DR. 8. Ready word data H'89AB from DR.
Rev. 1.0, 02/03, page 938 of 1294
1 word (2 bytes)
H'01
H'23
H'45 64 words H'89
H'67
H'AB
. . .
FIFO
. . .
Figure 26.2 DR Access Example 26.3.16 FIFO Pointer Clear Register (FIFOCLR) The FIFO write/read pointer is cleared by writing an arbitrary value to FIFOCLR.
Bit: Initial value: R/W: 7 6 5 4 3 2 1 0
FIFOCLR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Bit 7 to 0
Bit Name FIFOCLR
Initial Value H'00
R/W W
Description The FIFO pointer is cleared by writing an arbitrary value to this register.
Rev. 1.0, 02/03, page 939 of 1294
26.3.17 DMA Control Register (DMACR) DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal. The DMA request signal is output based on a value that has been set to SET2 to SET0.
Bit: Initial value: R/W: 7
DMAEN
6 0 R
5 0 R
4 0 R
3 0 R
2
SET2
1
SET1
0
SET0
0 R/W
0 R/W
0 R/W
0 R/W
Bit 7
Bit Name DMAEN
Initial Value 0
R/W R/W
Description DMA Enable 0: Disables output of DMA request signal. 1: Enables output of DMA request signal. Reserved These bits are always read as 0. The write value should always be 0. DMA Request Signal Assert Condition Sets DMA request signal assert condition. 000: Not output 001: FIFO remained data is 1/4 or less of FIFO capacity. 010: FIFO remained data is 1/2 or less of FIFO capacity. 011: FIFO remained data is 3/4 or less of FIFO capacity. 100: FIFO remained data is 1 byte or more. 101: FIFO remained data is 1/4 or more of FIFO capacity. 110: FIFO remained data is 1/2 or more of FIFO capacity. 111: FIFO remained data is 3/4 or more of FIFO capacity.
6 to 3
All 0
R
2 1 0
SET2 SET1 SET0
0 0 0
R/W R/W R/W
Rev. 1.0, 02/03, page 940 of 1294
26.3.18 Receive Data Timing Select Register (RDTIMSEL) RDTIMSEL selects the acquisition timing of receive response or receive data from the card. Consider the timing according to the multimedia card standards to set this register.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 RTSEL 0 R/W
Bit 7 to 1
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Receive Data Timing Selection 0: Receives data at the falling of MCCLK 1: Receives data at the rising of MCCLK
0
RTSEL
0
R/W
26.4
Operation
The multimedia card is an external storage media that can be easily connected or disconnected. The MMCIF operates in MMC mode. Insert a card and supply power to it. Then operate the MMCIF by applying the transfer clock after setting an appropriate transfer clock frequency. Do not connect or disconnect the card during command sequence execution or in the data busy state. 26.4.1 Operations in MMC Mode
MMC mode is an operating mode in which the transfer clock is output from the MCCLK pin, command transmission/response receive occurs via the MCCMD pin, and data is transmitted/received via the MCDAT pin. In this mode the next command can be issued while data is being transmitted/received. This feature is efficient for multiblock or stream transfer. In this case, the next command is the CMD12 command, which aborts the current command sequence.
Rev. 1.0, 02/03, page 941 of 1294
In MMC mode, broadcast commands that simultaneously issue commands to multiple cards are supported. After information of the inserted cards is recognized by a broadcast command, a relative address is given to each card. One card is selected by the relative address, other cards are deselected, and then various commands are issued to the selected card. Commands in MMC mode are basically classified into three types: broadcast, relative address, and flash memory operation commands. The card can be operated by issuing these commands appropriately according to the card state. (1) Operation of Broadcast Commands The CMD0, CMD1, CMD2, and CMD4 are broadcast commands. These commands and the CMD3 command comprise a sequence assigning relative addresses to individual cards. In this sequence, the CMD output format is open drain, and the command response is wired-OR. During the issuance of this command sequence, the CSEL2 to CSEL0 bits in the CLKON register should be set to 000 and the transfer clock frequency should be set sufficiently slow. * All cards are initialized to the idle state by the CMD0. * The operation condition registers (OCR) of all cards are read via wired-OR and cards that cannot operate are deactivated by the CMD1. The cards that are not deactivated enter the ready state. * The card identifications (CID) of all cards in the ready state are read via wired-OR by the CMD2. Each card compares it's CID and data on the MCCMD, and if they are different, the card aborts the CID output. Only one card in which the CID can be entirely output enters the acknowledge state. When the R2 response is necessary, set CTOCR to H'01. * A relative address (RCA) is given to the card in the acknowledge state by the CMD3. The card to which the RCA is given enters the standby state. * By repeating CMD2 and CMD3, RCAs are given to all cards in the ready state to make them enter the standby state. (2) Operation of Relative Address Commands The CMD7, CMD9, CMD10, CMD13, CMD15, CMD39, and CMD55 are relative address commands that address the card by RCA. The relative address commands are used to read card administration information and original information, and to change the specific card states. The CMD7 sets one addressed card to the transfer state, and the other cards to the standby state. Only the card in the transfer state can execute flash-memory operation commands, other than broadcast or relative-address commands.
Rev. 1.0, 02/03, page 942 of 1294
(3) Operation of Commands Not Requiring Command Response Some broadcast commands do not require a command response. Figure 26.3 shows an example of the command sequence for commands that do not require a command response. Figure 26.4 shows the operational flow for commands that do not require a command response. * Make settings to issue the command. * Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept driven until the end bit output is completed. * The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command transmit end interrupt (CMDI).
Input/output pins MCCLK
MCCMD
Command output (48 bits)
MCDAT CMDSTRT (START) INTSTR0 (CMDI) CSTR (CWRE) Command transmission period (BUSY) Command sequence period (REQ) Command transmission started Command transmission ended Cleared by software
Figure 26.3 Example of Command Sequence for Commands Not Requiring Command Response
Rev. 1.0, 02/03, page 943 of 1294
Start of command sequence
Set command data to CMDR0 to CMDR4
Set command type to CMDTYR
Set command response type to RSPTYR
Set the START bit in CMDSTRT to 1
(CMDI) interrupt detected? Yes End of command sequence
No
Figure 26.4 Example of Operational Flow for Commands Not Requiring Command Response (4) Operation of Commands without Data Transfer Broadcast, relative address, and flash memory operation commands include a number of commands that do not include data transfer. Such commands execute the desired data transfer using command arguments and command responses. For a command that is related to timeconsuming processing such as flash memory write/erase, the card indicates the data busy state via the MCDAT. Figures 26.5 and 26.6 show examples of the command sequence for commands without data transfer. Figure 26.7 shows the operational flow for commands without data transfer.
Rev. 1.0, 02/03, page 944 of 1294
* Make settings to issue the command. * Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept driven until the end bit output is completed. Command transmission completion can be confirmed by the command transmit end interrupt (CMDI). * The command response is received from the card. If the card returns no command response, the command response is detected by the command timeout error (CTERI). * The end of the command sequence is detected by poling the BUSY flag in CSTR or by the command response receive end interrupt (CRPI). * The end of data busy state is detected by the data busy end interrupt (DBSYI).
Input/output pins MCCLK MCCMD MCDAT CMDSTRT (START) INTSTR0 (CMDI) (CRPI) (DBSYI) CSTR (CWRE) Command output (48 bits) Command response reception (No busy state)
Command transmission started
Response reception completed
Command transmission period
(BUSY) (DTBUSY_TU) (DTBUSY) (REQ)
Command sequence execution period
Figure 26.5 Example of Command Sequence for Commands without Data Transfer (No Data Busy State)
Rev. 1.0, 02/03, page 945 of 1294
Input/output pins MCCLK MCCMD Command output (48 bits) Command response reception (Busy state)
MCDAT
CMDSTRT (START) INTSTR0 (CMDI) (CRPI) (DBSYI) CSTR (CWRE) (BUSY)
Command transmission started
Response reception completed Busy state completed
Command transmission period
Command sequence execution period (DTBUSY_TU)
(DTBUSY)
Data busy period
(REQ)
Figure 26.6 Example of Command Sequence for Commands without Data Transfer (with Data Busy State)
Rev. 1.0, 02/03, page 946 of 1294
Start of command sequence
Set command data to CMDR0 to CMDR4
Set command type to CMDTYR
Set command response type to RSPTYR
Set the START bit in CMDSTRT to 1
(CRPI) interrupt detected? Yes Not BUSY (DTBUSY) check BUSY
No
(CRCERI) interrupt detected? Yes
No
No
(DBSYI) interrupt detected? Yes
End of command sequence
Abnormal end of command sequence
Figure 26.7 Example of Operational Flow for Commands without Data Transfer
Rev. 1.0, 02/03, page 947 of 1294
(5) Commands with Read Data Flash memory operation commands include a number of commands involving read data. Such commands confirm the card status by the command argument and command response, and receive card information and flash memory data from the MCDAT pin. The number of bytes of the flash memory to be read is specified by CMD16 as a block size, or if not specified, reading is continued until it is aborted by CMD12 during multiblock or stream transfer. In multiblock transfer, the transfer operation is suspended for every block and an instruction to continue or end the command sequence is waited for. Whether the command sequence is suspended or not during the sequence depends on the size of the block and FIFO. The command sequence ends without suspending the data transfer when block size FIFO size. When block size > FIFO size, the command sequence is suspended by FIFO full. Once the command sequence is suspended, data in FIFO is processed before the command sequence is continued. In multiblock transfer, the command sequence is suspended for every block. In multiblock transfer, when a block size is set to 4 or 8 bytes and the CMDOFF bit of OPCR is set to 1 for only one block, the command response may not be received correctly. Therefore, when a block size is set to 4 or 8 bytes, the command sequence must be completed after reading at least two blocks. Figures 26.8 to 26.11 show examples of the command sequence for commands with read data. Figures 26.12 to 26.14 show the operational flows for commands with read data. * Make settings to issue the command, and clear FIFO. * Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept driven until the end bit output is completed. Command transmission completion can be confirmed by the command transmit end interrupt (CMDI). * The command response is received from the card. If the card does not return the command response, the command response is detected by the command timeout error (CTERI). * Read data is received from the card. * The inter-block suspension in multiblock transfer and suspension by the FIFO full are detected by the data transfer end interrupt (DTI) and FIFO full interrupt (FFI), respectively. To continue the command sequence, the RD_CONTI bit in OPCR should be set to 1. To end the command sequence, the CMDOFF bit in OPCR should be set to 1, and the CMD12 should be issued. * The end of the command sequence is detected by poling the BUSY flag in CSTR or by the data transfer end interrupt (DTI).
Rev. 1.0, 02/03, page 948 of 1294
Input/output pins MCCLK CMD17 (READ_SINGLE_BLOCK) MCCMD MCDAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) CSTR (CWRE) Single block read command execution sequence Command transmission started Read data Command response
Command
(BUSY) (FIFO_FULL) (REQ)
Figure 26.8 Example of Command Sequence for Commands with Read Data (Block Size FIFO Size)
Rev. 1.0, 02/03, page 949 of 1294
Input/output pins MCCLK CMD17 (READ_SINGLE_BLOCK) MCCMD MCDAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) CSTR (CWRE) Reading data from FIFO Command transmission started Command Command response Read data Transfer clock Transfer clock transmission halted transmission resumed Block data Block data reception suspended reception resumed Read data
(BUSY) (FIFO_FULL) (REQ)
Single block read command execution sequence
Figure 26.9 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size)
Rev. 1.0, 02/03, page 950 of 1294
Input/output pins MCCLK Transfer clock halted CMD18(READ_MULTIPLE_BLOCK) MCCMD Command Command response Command transmission started
Transfer clock transmission resumed CMD12(STOP_TRANSMISSION) Command Read data Command response
MCDAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) (BTI) CSTR (CWRE) (BUSY)
Read data
Read data
Block data reception ended
Multiblock read command execution sequence (FIFO_FULL) (REQ)
Stop command execution sequence
Figure 26.10 Example of Command Sequence for Commands with Read Data (Multiblock Transfer)
Rev. 1.0, 02/03, page 951 of 1294
Input/output pins MCCLK Transfer clock Transfer clock transmission transmission resumed halted MCCMD CMD11(READ_DAT_UNTIL_STOP) Command MCDAT CMDSTRT (START) OPCR (RD_CONTI) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (FFI) CSTR (CWRE) (BUSY) Command response Data reception Data reception resumed suspended Read data Command transmission started Read data Read data Transfer clock transmission resumed CMD12(STOP_TRANSMISSION) Command Command response
Data reception ended
Read data from FIFO
Stream read command execution sequence
Stop command execution sequence
(FIFO_FULL) (REQ)
Figure 26.11 Example of Command Sequence for Commands with Read Data (Stream Transfer)
Rev. 1.0, 02/03, page 952 of 1294
Start of command sequence
Set the number of transfer bytes (block size) to (TBCR)
Execute CMD16
: Set block length
Execute CMD17
: Execute single block data read
(CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Yes
Response status? No error
Error
(DTI) interrupt detected? No
Yes
Set the (CMDOFF) bit to 1
(CRCERI) interrupt detected? No No (FFI) interrupt detected? Yes Yes Block data read completed? No Read data from FIFO
Yes
Set the (RD_CONTI) bit to 1
End of command sequence
Abnormal end of command sequence
Figure 26.12 Example of Operational Flow for Commands with Read Data (Single Block Transfer)
Rev. 1.0, 02/03, page 953 of 1294
Start of command sequence
Set the number of transfer bytes (block size) to (TBCR)
Execute CMD16
: Set block length
Execute CMD17
: Execute multiblock data read
(CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Yes
Response status? No error
Error
(DTI) interrupt detected? No
Yes
(CRCERI) interrupt detected? No No (FFI) interrupt detected? Yes Yes Block data read completed? No Read data from FIFO Yes Block data read? No
Yes
Set the (CMDOFF) bit to 1 Read data from FIFO Set the (CMDOFF) bit to 1 Set the (CMDOFF) bit to 1 Execute CMD12
Set the (RD_CONTI) bit to 1
Execute CMD12
End of command sequence
Abnormal end of command sequence
Figure 26.13 Example of Operational Flow for Commands with Read Data (Multiblock Transfer)
Rev. 1.0, 02/03, page 954 of 1294
Start of command sequence
Execute CMD11
: Execute stream data read
Yes (CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Response status? No error
Error
No
(FFI) interrupt detected? Yes
Read data from FIFO
No
Data read completed? Yes
Set the (RD_CONTI) bit to 1
Set the (CMDOFF) bit to 1
Set the (CMDOFF) bit to 1
Execute CMD12
End of command sequence
Abnormal end of command sequence
Figure 26.14 Example of Operational Flow for Commands with Read Data (Stream Transfer)
Rev. 1.0, 02/03, page 955 of 1294
(6) Commands with Write Data Flash memory operation commands include a number of commands involving write data. Such commands confirm the card status by the command argument and command response, and transmit card information and flash memory data via the MCDAT pin. For a command that is related to time-consuming processing such as flash memory write, the card indicates the data busy state via the MCDAT pin. The number of bytes of flash memory to be written is specified by CMD16 as a block size, or if not specified, writing is continued until it is aborted by CMD12 during multiblock or stream transfer. In multiblock transfer, the transfer operation is suspended for every block and an instruction to continue or end the command sequence is waited for. The suspension of the command sequence depends on the size of the block and FIFO. The command sequence ends without suspending the data transfer when block size FIFO size. When block size > FIFO size, the command sequence is suspended by FIFO empty. Once the command sequence is suspended, the next data is written to the FIFO before the command sequence is continued. In multiblock transfer, the command sequence is suspended for every block. Figures 26.15 to 26.18 show examples of the command sequence for commands with write data. Figures 26.19 to 26.21 show the operational flows for commands with write data. * Make settings to issue a command, and set write data to FIFO. * Set the START bit in CMDSTRT to 1 to start command transmission. MCCMD must be kept driven until the end bit output is completed. * Command transmission completion can be confirmed by the command transmit end interrupt (CMDI). * The command response is received from the card. * If the card returns no command response, the command response is detected by the command timeout error (CTERI). * Set the DATAEN bit in OPCR to 1 to start write data transmission. MCDAT must be kept driven until the end bit output is completed. * Inter-block suspension in multiblock transfer and suspension according to the FIFO empty are detected by the data transfer end interrupt (DTI), data response interrupt (DRPI), and FIFO empty interrupt (FEI), respectively. In addition, after the end of data transfer (DRPI detection), the data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, cancellation of the data busy state is detected by the data busy end interrupt (DBSYI). To continue the command sequence, write data should be written to the FIFO, and the DATAEN bit in OPCR should be set to 1. To end the command sequence, the CMDOFF bit in OPCR should be set to 1, and the CMD12 should be issued.
Rev. 1.0, 02/03, page 956 of 1294
* The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer end interrupt (DTI), or data response interrupt (DRPI). * The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the end of the data busy state is detected by the data busy end interrupt (DBSYI). Note: In a write to the card by stream transfer, the MMCIF continues data transfer to the card even after a FIFO empty interrupt is detected. In this case, complete the command sequence after at least 24 transfer clock cycles.
Input/output pins MCCLK CMD24(WRITE_SINGLE_BLOCK) MCCMD Command Command response MCDAT CMDSTRT (START) OPCR (DATAEN) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU) Single block write command execution sequence Command transmission started Write data Status Busy
(REQ)
Figure 26.15 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size)
Rev. 1.0, 02/03, page 957 of 1294
Input/output pins MCCLK CMD24(WRITE_SINGLE_BLOCK) MCCMD Command Command response MCDAT CMDSTRT Command transmission started
Transfer clock transmission halted
Transfer clock transmission resumed
Write data
Write data Busy
Block data Block data transmission transmission suspended resumed Writing data to FIFO
(START) OPCR (DA TA EN) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU)
Single block write command execution sequence
(REQ)
Figure 26.16 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size)
Rev. 1.0, 02/03, page 958 of 1294
Input/output pins MCCLK CMD25 WRITE_MULTIPE_BLOCK MCCMD Command Command response MCDAT CMDSTRT (START) OPCR (DATAEN) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU) (REQ) Stop command execution sequence Command transmission started Block data transmission started Next block data transmission started Block data reception ended Write data Status Write data Write data Command Command response CMD12(STOP_TRANSMISSION)
Figure 26.17 Example of Command Sequence for Commands with Write Data (Multiblock Transfer)
Rev. 1.0, 02/03, page 959 of 1294
Input/output pins MCCLK
Transfer clock transmission halted CMD20 (WRITE_DAT_UNTIL_STOP)
Transfer clock transmission resumed
Transfer clock transmission halted
Transfer clock transmission resumed CMD12(STOP_TRANSMISSION)
MCCMD Command MCDAT CMDSTRT (START) OPCR (DATAEN) (CMDOFF) INTSTR0 (CMDI) (CRPI) (DTI) (DRPI) (DBSYI) (FEI) CSTR (CWRE) (BUSY) Stream write command execution sequence (FIFO_EMPTY) (DTBUSY) (DTBUSY_TU) (REQ) Command transmission started Write data Write data Write data Data transmission ended Data Data Command transmission transmission response suspended resumed Data transmission suspended Command Command response Busy
Writing data to FIFO
Stop command execution sequence
Figure 26.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)
Rev. 1.0, 02/03, page 960 of 1294
Start of command sequence
Set the number of transfer bytes (block size) to (TBCR) Write data to FIFO
Execute CMD16
: Set block length
Execute CMD24
: Execute single block data write
(CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Yes
Response status? No error Set the (DATAEN) bit to 1
Error
(DTI) interrupt detected? No
Yes Yes
(CRCERI) interrupt detected? No No (DRPI) interrupt detected? Yes No
No No
(FFI) interrupt detected? Yes
(DTBUSY) check Yes (DBSYI) interrupt detected? Yes
Yes
Block data read completed? No Read data from FIFO
No Set the (CMDOFF) bit to 1
End of command sequence
Abnormal end of command sequence
Figure 26.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer)
Rev. 1.0, 02/03, page 961 of 1294
Start of command sequence
Execute CMD16 Set the number of transfer bytes (block size) to (TBCR) Write data to FIFO Execute CMD25
: Set block length
: Execute multiblock data write
(CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Yes
Response status? No error Set the (DATAEN) bit to 1
Error
(DTI) interrupt detected? No
Yes Yes
(CRCERI) interrupt detected? No No (DRPI) interrupt detected? Yes No (DTBUSY) check Yes (DBSYI) interrupt detected? Yes Yes Next block write? No Set the (CMDOFF) bit to 1
No
(FEI) interrupt detected? Yes
Yes
Block data write completed? No Write data to FIFO
No
Set the (CMDOFF) bit to 1
Set the (CMDOFF) bit to 1 Execute CMD12
Execute CMD12 End of command sequence Abnormal end of command sequence
Figure 26.20 Example of Operational Flow for Commands with Write Data (Multiblock Transfer)
Rev. 1.0, 02/03, page 962 of 1294
Start of command sequence Write data to FIFO Execute CMD20 : Execute stream data write
(CRCERI) interrupt detected? No No (CRPI) interrupt detected? Yes Read response register
Yes
Response status? No error
Error
Set the (DATAEN) bit to 1
No
(FEI) interrupt detected? Yes
Write data to FIFO
No
Data write completed? Yes Set the (CMDOFF) bit to 1
Set the (DATAEN) bit to 1
Set the (CMDOFF) bit to 1
Execute CMD12 Abnormal end of command sequence End of command sequence
Figure 26.21 Example of Operational Flow for Commands with Write Data (Stream Transfer)
Rev. 1.0, 02/03, page 963 of 1294
26.5
MMCIF Interrupt Sources
Table 26.7 lists the MMCIF interrupt sources. The interrupt sources are classified into four groups, and four interrupt vectors are assigned. Each interrupt source can be individually enabled by the enable bits in INTCR0 to INTCR2. Disabled interrupt sources do not set the flag. Table 26.7 MMCIF Interrupt Sources
Name MMCI0 Interrupt source FIFO empty FIFO full MMCI1 Data response Data transfer end Command response receive end Command transmit end Data busy end MMCI2 CRC error Data timeout error Command timeout error MMCI3 FIFO ready Interrupt flag FEI FFI DRPI DTI CRPI CMDI DBSYI CRCERI DTERI CTERI FRDYI
Rev. 1.0, 02/03, page 964 of 1294
26.6
26.6.1
Operations when Using DMA
Operation in Read Sequence
*
In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC . Transmit the read command after setting DMACR. Figure 26.22 shows the operational flow for a read sequence. * Clear FIFO and make settings in DMACR. * Read command transmission is started. * Read data is received from the card. * After the read sequence, data remains in FIFO. If necessary, write 100 to SET[2:0] in DMACR to read all data from FIFO. * Confirm that the DMAC transfer is completed and set the DMAEN bit in DMACR to 0. * When the DMAEN bit in DMACR is set to 1, the FIFO_FULL bit in CSTR and FFI bit in INTSTR0 can not be set. Note: *Access from the DMAC to FIFO must be done in bytes or words. 26.6.2 Operation in Write Sequence
To transfer data to FIFO with the DMAC, set MMCIF (DMACR) after setting the DMAC. Then, start transfer to the card after a FIFO ready interrupt. Figure 26.23 shows the operational flow for write sequence. * Make settings in DMACR, and set write data to FIFO. * After receiving write command response, confirm whether data above the condition of DMACR setting is written to FIFO by a FIFO ready interrupt (FRDYI). Then, set 1 to the DATAEN bit in OPCR to start write-data transmission. In a write to the card by stream transfer, the MMCIF continues data transfer to the card even after a FIFO empty interrupt is detected. Therefore, complete the write sequence after at least 24 card clock cycles. * Confirm that the DMAC transfer is all completed and be sure to set the DMAEN bit in DMACR to 0. * When the DMAEN bit in DMACR is set to 1, the FIFO_EMPTY bit in CSTR and the FEI bit in INSTR0 can not be set. * Some combinations of DMACR settings and data transfer count will generate no FIFO ready interrupt (FRDYI) and data will remain in FIFO. In this case, set the DATAEN bit in OPCR to 1 to start write-data transmission.
Rev. 1.0, 02/03, page 965 of 1294
CPU Start transfer-ready
MMCIF
DMAC
FIFO data amount Clear FIFO
Set DMAC-related conditions Set DMACR (DMA enable on)
Start transfer
No
DMA enable? Yes Assert condition DMA request assert condition? Yes DMA request assert No
Transfer end? Yes
No
DMAC initiation Transfer-end interrupt processing Read from FIFO
No DMA transfer end? Yes
DMA transfer-end interrupt processing
End
Figure 26.22 Example of Read Sequence Flow
Rev. 1.0, 02/03, page 966 of 1294
CPU
MMCIF
DMAC
Start transfer-ready
Set DMAC-related condition Set DMACR (DMA enable on)
DMA request assert
DMAC initiation
No
Higher than specified capacity? Yes
Write to FIFO
DMA transfer end? No FIFO ready interrupt processing Yes
DMA transfer-end interrupt processing
Start transfer FIFO data amount
Start specified capacity No DMA enable? Yes Assert condition DMA request assert condition? Yes DMA request assert No
No Transfer end? Yes
Transfer-end interrupt processing
End
Figure 26.23 Example of Write Sequence Flow
Rev. 1.0, 02/03, page 967 of 1294
26.7
Register Accesses with Little Endian Specification
When the little endian is specified, the access size for registers or that for memory where the corresponding data is stored should be fixed. For example, if data read from the MMCIF with the word size is written to memory and then it is read from memory with the byte size, data misalignment occurs.
Rev. 1.0, 02/03, page 968 of 1294
Section 27 Multifunctional Interface (MFI)
This LSI incorporates a multifunctional interface (MFI) for use in high-speed transfer of data to external devices which cannot share an external bus. The MFI is a parallel interface with selectable 8-bit/16-bit bus width, and can be directly connected to 68/80-series system interfaces. The MFI allows external devices to read from and write to 2-kbyte on-chip RAM exclusively for MFI use (MFRAM), in 32-bit units. Access to this MFRAM is available via the MFI and the CPU of this LSI. The MFI supports interrupts issued to this LSI by an external device, and those sent from this LSI to the external device. Using the MFRAM and these interrupt functions enables software-based data transfer between external devices and the on-chip CPU and connection to external devices not having bus privileges.
27.1
Features
* Provides reading from/writing to the 2-kbyte on-chip MFRAM in 32-bit units via MFI pins, and in 8-, 16-, or 32-bit units from the on-chip CPU. * Supports a high-speed asynchronous interface with selectable 8-bit/16-bit bus width; allows selection of 68- or 80-series during reset period. * Automatic address increments and endian settings are configurable. * Writing to specific bits of MFI on-chip registers from an external device will issue interrupts to this LSI. Conversely, this LSI is able to send interrupts from the on-chip CPU to the external device. * Provides 7 interrupt source bits each for internal interrupts and for external interrupts. It allows software-based control of 128 different interrupts with high-speed data transfer using interrupts.
Rev. 1.0, 02/03, page 969 of 1294
Figure 27.1 is a block diagram of the MFI.
MFI
MFIMCR
MFIDATA
MFRAM (2 kbytes)
MFIEICR
MFIADR
MFIIDX
Select
MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-MD MFI-INT
MFIGSR
Control circuit
Figure 27.1 MFI block diagram
Rev. 1.0, 02/03, page 970 of 1294
Peripheral bus
MFID15-MFID0 (In 8-bit mode, only the lower 8 bits are valid)
MFISCR
MFIIICR
27.2
Input/Output Pins
Table 27.1 shows the MFI pin configuration. To use the MFI , set pin MD7 to MFI mode (MD7 = 0). Table 27.1 Pin Configuration
Name MFI data MFI chip select MFI register select MFI enable/write Abbreviation MFI-D15 to MFI-D0 MFI-CS MFI-RS I/O Input/ Output Input Input Description Address/data/command input/output to the MFI Pins MFI-D7 to MFI-D0 are valid in 8-bit mode. Chip select input to the MFI Selects MFI access types 0: Normal access 1: Index/status register access MFI-E/WR Input For a 68-series interface, enable signal to start data writing and reading For an 80-series interface, write strobe signal; data writing at low level For a 68-series interface, select signal for data writing or reading For an 80-series interface, read strobe signal; data reading at low level Selects the MFI 68/80-series interface mode 0: 80-series interface 1: 68-series interface This pin is sampled at a power-on reset by the RESET pin. Do not change the level of this pin after a power-on reset. MFI interrupt MFI-INT Output Interrupt request to an external device from the MFI
MFI readwrite/read
MFI-RW/RD
Input
MFI mode
MFI-MD
Input
Rev. 1.0, 02/03, page 971 of 1294
27.3
Register Descriptions
The MFI has the following registers. For information on the register addresses and register states during various processing states, refer to section 32, List of Registers. Table 27.2 Register Configuration (1)
Register Name MFI index register MFI general status register MFI status/control register MFI memory control register Abbrev. MFIIDX MFIGSR MFISCR R/W R/W*1 R/W R/W*2
4
P4 Address H'FE2C 0000 H'FE2C 0004 H'FE2C 0008 H'FE2C 000C H'FE2C 0010 H'FE2C 0014
5
Area 7 Address Size H'1E2C 0000 H'1E2C 0004 H'1E2C 0008 H'1E2C 000C H'1E2C 0010 H'1E2C 0014 H'1E2C 0018 H'1E2C 001C H'1E2E 0000 H'1E2E 07FF 32 32 32 32 32 32 32 32 32 32
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
MFIMCR R/W* R/W
MFI on-chip interrupt control register MFIIICR
MFI external interrupt control register MFIEICR R/W MFI address register MFI data register MFIADR R/W*
H'FE2C 0018 H'FE2C 001C H'FE2E 0000 H'FE2E 07FF
MFIDATA R/W MFRAM Start MFRAM End R/W R/W
Rev. 1.0, 02/03, page 972 of 1294
Table 27.2 Register Configuration (2)
Register Name
Abbrev.
Power-on Reset by RESET Pin/WDT/ H-UDI
Manual Reset by RESET Pin/WDT/ Multiple Exception
Standby Sleep by by Sleep Software Instruction /Each /Deep by Sleep Hardware Module
MFI index register MFI general status register MFI status/control register MFI memory control register
MFIIDX
H'0000
H'0000 H'0000
3 3
Retained Retained
*
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
MFIGSR H'0000
MFISCR H'0040/H'0050* H'0040/H'0050* Retained MFIMCR H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined Retained Retained Retained Retained Retained Retained Retained
MFI on-chip interrupt control register MFIIICR
MFI external interrupt control register MFIEICR H'0000 MFI address register MFI data register MFIADR H'0000 MFIDATA H'0000 MFRAM Start MFRAM End Undefined Undefined
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. *1. The external device can write to this register only when the MFI-RS pin is driven high. The on-chip CPU cannot write to this register. *2. The external device can write to bit 6 only via the MFI. The on-chip CPU cannot write to this bit. Perform a reading of MFISCR after changing this bit to check for malfunctions. *3. 80-series interface: 0040; 68-series interface: 0050 *4. The external device can write to bits 7, 5, 3, and 0 only via the MFI. The on-chip CPU cannot write to these bits. *5. The external device can write to bits 10 to 2 only via the MFI. The on-chip CPU cannot write to these bits.
Rev. 1.0, 02/03, page 973 of 1294
27.3.1
MFI Index Register (MFIIDX)
The MFIIDX is a 32-bit register which is used to specify the register for reading from and writing to via the MFI. Set this register holding the MFI-RS pin low. The external device can write to this register only when the MFI-RS pin is driven high.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 22 0 R 6 21 0 R 5 20 0 R 4 19 0 R 3 18 0 R 2 17 0 R 1 16 0 R 0
REG5 REG4 REG3 REG2 REG1 REG0 BYTE1 BYTE0 0 0 0 0 0 0 0 0 R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Specifies MFI on-chip register 5 to 0. 000000: MFIGSR 000010: MFIMCR 000100: MFIEICR 000110: MFIDATA 000001: MFISCR 000011: MFIIICR 000101: MFIADR
7 to 2
REG5 to REG0
All 0
R/W*
Settings other than the above are prohibited.
Rev. 1.0, 02/03, page 974 of 1294
Bit 1 0
Bit Name BYTE1 BYTE0
Initial Value 0 0
R/W R/W* R/W*
Description Specifies byte position for on-chip register. Specifies which 8 or 16 bits of the 32-bit register are to be accessed. * MFISCR.BO = 0 8-bit bus 00: Register bits 31 to 24 01: Register bits 23 to 16 10: Register bits 15 to 8 11: Register bits 7 to 0 * MFISCR.BO = 1 8-bit bus 00: Register bits 7 to 0 01: Register bits 15 to 8 10: Register bits 23 to 16 11: Register bits 31 to 24 16-bit bus Register bits 15 to 0 Setting prohibited Register bits 31 to 16 Setting prohibited 16-bit bus Register bits 31 to 16 Setting prohibited Register bits 15 to 0 Setting prohibited
However, with MFIDATA selected by bits REG5 to REG0, each time reading from or writing to MFIDATA from the external device occurs, bits BYTE1 and BYTE0 change according to the following rules. 8-bit bus: 00 16-bit bus: 00 01 10 10 00 11 00 10... etc. 01... etc.
Note: * The external device can write to these bits via the MFI only when the MFI-RS pin is 1. The on-chip CPU cannot write to these bits.
27.3.2
MFI General Status Register (MFIGSR)
The MFIGSR is a 32-bit register which an MFI-connected external device uses to indicate its status to the on-chip CPU and vice versa. When the MFI-RS pin is driven high, this register is read-only via the MFI. To write to the MFIGSR from the MFI, specify MFIGSR setting bits REG5 to REG0, drive the MFI-RS pin low and then perform writing. In this state, the MFIGSR can also be read.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 22 0 R 21 0 R 20 0 R 19 0 R 18 0 R 17 0 R 16 0 R
7 6 5 4 3 2 1 0 STA STA STA STA STA STA STA STA TUS7 TUS6 TUS5 TUS4 TUS3 TUS2 TUS1 TUS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 975 of 1294
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. General status These bits can be read from and written to by the software of an MFI-connected external device and by the on-chip CPU. These bits are not modified by hardware other than a power-on reset.
7 to 0
STATUS7 to STATUS0
All 0
R/W
27.3.3
MFI Status/Control Register (MFISCR)
The MFISCR is a 32-bit readable/writable register which is used to control the MFI mode and state.
Bit: 31 Initial value: R/W: Bit: 0 R 15 Initial value: R/W: 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 0 R 22 0 R 6 SCR MD2 1 R/W*1 21 0 R 5 0 R 20 0 R 4 SCR MD0 0 R 19 0 R 3 0 R 18 0 R 2 0 R 17 0 R 1 EDN 0 R/W 16 0 R 0 BO 0 R/W
Bit 31 to 7
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
6
SCRM D2
1
R/W*
MFI mode 2 Specifies the MFI bus width. Changing this bit immediately takes effect to change the bus width. 0: 8-bit mode 1: 16-bit mode Note: In order to check for malfunctions, perform a dummy reading of MFISCR after changing this bit.
Rev. 1.0, 02/03, page 976 of 1294
Bit 5
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
4
SCRMD0
0
R
MFI mode 0 The MFI-MD pin value is sampled at a power-on reset by the RESET pin. Indicates whether the MFI is the 68- or the 80-series interface. Indicates the value of the MFI-MD signal. 0: 80-series interface 1: 68-series interface
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Endian setting (for MFRAM access) Specifies the byte order when accessing the MFRAM from the on-chip CPU. See figure 27.2. (Can be set independently from the MD5 pin setting of this LSI.) 0: Big endian 1: Little endian
1
EDN
0
R/W
0
BO
0
R/W
Byte order Specifies the byte order of MFIDATA corresponding to MFIADR. 0: Big endian 1: Little endian
Notes: *
The external device can write to this bit via the MFI. The on-chip CPU cannot write to this bit.
31 Byte Word Longword 00 00
MFRAM 01 10 10 00 When EDN = 0 11
0 Byte Word Longword
31 11 10
MFRAM 10 01 00 00 When EDN = 1 00
0
Relation between lower two bits of address and access size used when accessing MFRAM
Figure 27.2 Differences in EDN Bit Settings
Rev. 1.0, 02/03, page 977 of 1294
27.3.4
MFI Memory Control Register (MFIMCR)
The MFIMCR is a 32-bit register that the external device uses to control the MFRAM via the MFI.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 LOCK 0 R/W*1 22 0 R 6 0 R 21 0 R 5 WT*3 0 R/W*1 20 0 R 4 0 R 19 0 R 3 RD*3 0 R/W*1 18 0 R 2 0 R 17 0 R 1 0 R 16 0 R 0 AI/AD 0 R/W*1
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
1
7
LOCK
0
R/W*
Lock This bit is used to lock read/write operations during continuous access. Writing 1 to the LOCK bit retains the values of the RD and WT bits simultaneously set until clearing the LOCK bit to 0. Setting both the RD and LOCK bits simultaneously to 1 puts the MFI in the continuous read mode; setting both the WT and LOCK bits simultaneously to 1 results in the continuous write mode. Do not set the RD and WT bits simultaneously to 1. Reserved This bit is always read as 0. The write value should always be 0.
6
0
R
5
WT*
3
0
R/W*
1
Write Setting this bit to 1 writes the MFIDATA value to the 2 MFRAM address indicated by MFIADR.* * Setting both the WT and LOCK bits simultaneously to 1 results in the continuous write mode and enables 4 high-speed data transfer * . The WT value remains 1 until the WT bit is next written to 0, or until the LOCK bit is cleared to 0. If not setting the LOCK bit simultaneously to 1, writing to MFRAM is performed only once. The WT bit is automatically cleared to 0.
*
Rev. 1.0, 02/03, page 978 of 1294
Bit 4
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
1
3
RD*
3
0
R/W*
Read Setting this bit to 1 reads the MFRAM data indicated by 2 MFIADR into MFIDATA.* * Setting the RD and LOCK bits simultaneously to 1 results in the continuous read mode, and enables high-speed data transfer. The RD bit remains 1 until the RD bit is next written to 0, or until the LOCK bit is cleared to 0. If not setting the LOCK bit simultaneously to 1, reading of MFRAM is performed only once. The RD bit is automatically cleared to 0
*
2, 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1
0
AI/AD
0
R/W*
Address auto-increment/decrement This bit is valid only when the LOCK bit is 1. Each time an MFRAM read or write operation occurs, the value in MFIADR is automatically changed by +4 or by -4. 0: Auto-increment (+4) 1: Auto-decrement (-4)
Notes: *1. The external device can write to this bit via the MFI. The on-chip CPU cannot write to this bit. *2. If the on-chip CPU and the external device via the MFI access MFRAM concurrently, the access via the MFI is handled first. *3. Do not set the WT and RD bits simultaneously to 1. *4. Performs continuous writing to MFRAM in 32-bit units. Data with a length of less than 32 bits is not written to MFRAM.
Rev. 1.0, 02/03, page 979 of 1294
27.3.5
MFI Internal Interrupt Control Register (MFIIICR)
The MFIIICR is a 32-bit register that an MFI-connected external device uses to issue interrupts to the on-chip CPU.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 IIC6 0 R/W 22 0 R 6 IIC5 0 R/W 21 0 R 5 IIC4 0 R/W 20 0 R 4 IIC3 0 R/W 19 0 R 3 IIC2 0 R/W 18 0 R 2 IIC1 0 R/W 17 0 R 1 IIC0 0 R/W 16 0 R 0 IIR 0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Internal interrupt source Bits used to specify the interrupt source generated by the IIR. Both the MFI-connected external device and the on-chip CPU can write to these bits. Using these bits enables fast interrupt handling. These bits are completely under software control, and their values have no effect on the operation of the LSI. Internal interrupt request While this bit is 1, an interrupt request is issued to the on-chip CPU.
7 6 5 4 3 2 1 0
IIC6 IIC5 IIC4 IIC3 IIC2 IIC1 IIC0 IIR
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 980 of 1294
27.3.6
MFI External Interrupt Control Register (MFIEICR)
The MFIEICR is a 32-bit register that the on-chip CPU uses to issue interrupts an MFI-connected external device.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 0 R 25 0 R 9 0 R 24 0 R 8 0 R 23 0 R 7 EIC6 0 R/W 22 0 R 6 EIC5 0 R/W 21 0 R 5 EIC4 0 R/W 20 0 R 4 19 0 R 3 18 0 R 2 EIC1 0 R/W 17 0 R 1 EIC0 0 R/W 16 0 R 0 EIR 0 R/W
EIC3 EIC2 0 R/W 0 R/W
Bit 31 to 8
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. External interrupt source Bits used to specify the interrupt source generated by the EIR. Both the MFI-connected external device and the on-chip CPU can write to these bits. Using these bits enables fast interrupt handling. These bits are completely under software control, and their values have no effect on the operation of the LSI. External interrupt request While this bit is 1, the MFI-INT pin is asserted low and interrupt request is issued to the external device from this LSI.
7 6 5 4 3 2 1 0
EIC6 EIC5 EIC4 EIC3 EIC2 EIC1 EIC0 EIR
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 981 of 1294
27.3.7
MFI Address Register (MFIADR)
The MFIADR is a 32-bit register which indicates the address in the MFRAM to be accessed by the external device via the MFI. Specifying continuous access to the MFRAM in the LOCK bit in MFIMCR automatically performs auto-increment (+4) or auto-decrement (-4) of the address according to the AI/AD bit in MFIMCR, and updates MFIADR each time the external device accesses the MFRAM.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 0 R 30 0 R 14 0 R 29 0 R 13 0 R 28 0 R 12 0 R 27 0 R 11 0 R 26 0 R 10 A10 0 R/W* 25 0 R 9 A9 24 0 R 8 A8 23 0 R 7 A7 22 0 R 6 A6 21 0 R 5 A5 20 0 R 4 A4 19 0 R 3 A3 18 0 R 2 A2 17 0 R 1 0 R 16 0 R 0 0 R
0 0 0 0 0 R/W* R/W* R/W* R/W* R/W*
0 0 0 R/W* R/W* R/W*
Bit 31 to 11
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Address Specifies the memory space in the 2-kbyte MFRAM to be accessed by the external device via the MFI, with 32bit alignment. Reserved These bits are always read as 0. The write value should always be 0.
10 to 2
A10 to A2
All 0
R/W*
1, 0
All 0
R
Note:
* The external device can write to these bits via the MFI. The on-chip CPU cannot write to these bits.
Rev. 1.0, 02/03, page 982 of 1294
27.3.8
MFI Data Register (MFIDATA)
The MFIDATA is a 32-bit register which is used to hold data to be written to the MFRAM and data read from the MFRAM. It is possible to use the MFDATA for data transfer between an MFIconnected external device and the software on this LSI if this register is not used for accessing the MFRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI MFI DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16
Initial value: R/W: Bit:
0 R/W 15
0 R/W 14
0 R/W 13
0 R/W 12
0 R/W 11
0 R/W 10
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
MFI MFI MFI MFI MFI MFI MFI MFI DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8
MFI MFI DATA7 DATA6
MFI MFI DATA5 DATA4
MFI MFI DATA3 DATA2
MFI MFI DATA1 DATA0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 31 to 0
Bit Name MFIDA TA31 to MFIDA TA0
Initial Value All 0
R/W R/W
Description 32-bit data
Rev. 1.0, 02/03, page 983 of 1294
27.4
27.4.1
Operation
Overview
Access to the MFI is controlled by a combination of settings in the MFI-CS, MFI-RS, MFI-E/WR, and MFI-RW/RD pins. Table 27.3 shows the relationship between combinations of these signals and MFI operations. For access to MFIIDX and MFIGSR, refer to table 27.4. Table 27.3 MFI Operations
68 Series MFI-CS MFIMFI-RS MFI-E /WR WR MFI-RW /RD RD 80 Series MFI-E /WR WR MFI-RW /RD RD Operation
1 0 0 0 0 0 0 Note: *
x 0 0 1 1 x x
x 1 1 1 1 0
x 1 0 1 0 x
x 1 0 1 0 1 0
x 0 1 0 1 1 0
No operation (NOP) Read from register specified by MFIIDX[7:0] Write to register specified by MFIIDX[7:0] Read from MFIGSR[7:0]* Write to MFIIDX[7:0]* No operation (NOP) Setting prohibited
Performs reading and writing with MFI-D7 to MFI-D0 when using the MFI with a 16-bit width. x: Don't care
Table 27.4 Access to MFIIDX and MFIGSR
External device* CPU MFIIDX MFIGSR Note: * [31:0] [31:0] When the MFI-RS pin is driven high. 8 bits [7:0] [7:0] 16 bits [15:0] [15:0]
Rev. 1.0, 02/03, page 984 of 1294
27.4.2
Connections
Figure 27.3 shows an example of the recommended connections between the MFI and an external device.
68-Series 16-bit parallel External device /CS A1 E R/W D15 - D0 MFI MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D15 - MFI-D0 80-Series 16-bit parallel External device /CS A1 /WR /RD D15 - D0 MFI MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D15 - MFI-D0
68-Series 8-bit parallel External device /CS A1 E R/W D7 - D0 MFI MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D7 - MFI-D0
80-Series 8-bit parallel External device /CS A1 /WR /RD D7 - D0 MFI MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D7 - MFI-D0
Figure 27.3 Example of MFI Connections 27.4.3 Memory Map
Table 27.5 shows the memory space in the internal MFRAM. Table 27.5 Memory Map
Start address Access by external device via MFI Access by on-chip CPU H'0000 H'FE2E 0000 End address H'07FF H'FE2E 07FF Size 2 kbytes 2 kbytes
Rev. 1.0, 02/03, page 985 of 1294
27.5
Interface (Basic)
This section describes the 8-bit parallel interface using the MFI. The MFI interface enables access to the 68 and 80 series. Access via the MFI is complete within a fixed time. 27.5.1 68-Series 8-Bit Parallel Interface
Figure 27.4 shows the basic read/write sequence for the 68-series 8-bit parallel interface. MFI access is limited to the period during which the MFI-E/WR signal is driven high and the MFI-CS signal is simultaneously driven low. During this period, a write operation is performed with the MFI-RW/RD signal driven low; a read operation is performed with this signal driven high. The MFI-RS signal indicates whether this is normal access or index/status register access; the low level indicates normal access, and the high level indicates an index/status register access. For details of the timing, refer to section 33, the AC Characteristics.
Write cycle MFI-CS MFI-RS Read cycle
MFI-E/WR
MFI-RW/RD MFI-D15 - MFI-D0 WT_D RD_D WT_D: Write data RD_D: Read data
Figure 27.4 Basic Timing for the MFI 68-Series Interface
Rev. 1.0, 02/03, page 986 of 1294
27.5.2
80-Series 8-Bit Parallel Interface
Figure 27.5 shows the basic read/write sequence for the 80-series 8-bit parallel interface. In the 80-series interface, read operations are limited to the period during which both the MFI-RW/RD and MFI-CS signals are driven low. Write operations are limited to the period during which both the MFI-E/WR and the MFI-CS signals are driven low. The MFI-RS signal has the same function as in the 68-series interface.
Write cycle MFI-CS MFI-RS Read cycle
MFI-E/WR
MFI-RW/RD MFI-D15 - MFI-D0 WT_D RD_D WT_D: Write data RD_D: Read data
Figure 27.5 Basic Timing of the MFI 80-Series Interface
Rev. 1.0, 02/03, page 987 of 1294
27.6
Interface (Details)
This section describes the details of the interface, for the case of the 68-series interface. 27.6.1 Writing to MFIIDX/Reading from MFIGSR
Figure 27.6 shows writing to MFIIDX and reading from MFIGSR.
MFIIDX write cycle MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D15 - MFI-D0 WT_D RD_D WT_D: Write data RD_D: Read data MFIGSR read cycle
Figure 27.6 Writing to MFIIDX and Reading from MFIGSR 27.6.2 Reading from/Writing to MFI Register
As shown in figure 27.7, to read from/write to the MFI registers, specify a register and a byte position to be accessed by writing to MFIIDX while the MFI-RS is driven high. Then, read from or write to the register specified by MFIIDX with the MFI-RS pin driven low.
Write to index MFI-CS MFI-RS MFI-E/WR MFI-RW/RD MFI-D7 - MFI-D0
MFIIDX WT_D RD_D
Write to register
Read from register
Register selection
WT_D: Write data RD_D: Read data
Figure 27.7 MFI Register Settings
Rev. 1.0, 02/03, page 988 of 1294
27.6.3
Continuous Data Writing to MFRAM via MFI
Figure 27.8 shows the timing chart for continuous data transfer to the MFRAM via the MFI. As shown in this timing chart, setting the starting address and the data to be written first will enable continuous data transfer subsequently. It provides effective data transfer to this LSI using DMA transfer and others.
MFI-CS MFI-RS MFI-E/WR MFI-RW/RD 16 AH 17 AL 18 D1 19 D2 1A D3 1B D4 0B A0 18 D D D D D D D D D D MFI-D7-MFI-D0
MFIADR setting Bits 15-8 = AH Bits 7-0 = AL
Data for first write operation set in MFIDATA
MFIMCR set to MFIDATA continuous write selection and auto increment
Continuous data write
Figure 27.8 Continuous Data Writing to MFRAM (8-Bit Bus Width, MFISCR.SCRMD2 = 0) 27.6.4 Continuous Reading from MFRAM via MFI
Figure 27.9 shows the timing chart for continuous reading from the MFRAM via the MFI. As shown in this timing chart, setting the start address will enable continuous data reading subsequently. It provides effective data transfer from this LSI using DMA transfer and others.
MFI-CS MFI-RS MFI-E/WR MFI-RW/RD 16 AH 17 AL 0B 84 18 D D D D D D D D D D D D D D D D D D MFI-D7-MFI-D0
MFIADR setting MFIMCR set to MFIDATA Bits 15-8 = AH continuous write selection Bits 7-0 = AL and auto increment
Continuous data read
Figure 27.9 Continuous Data Reading from MFRAM (8-Bit Bus Width, MFISCR.SCRMD2 = 0)
Rev. 1.0, 02/03, page 989 of 1294
Rev. 1.0, 02/03, page 990 of 1294
Section 28 Hitachi User Debug Interface (H-UDI)
The H-UDI is serial input/output interface using the pin functions and transfer protocol compliant with JTAG (IEEE 1149.4: IEEE Standards Test Access Port and Boundary-Scan Architecture) standards. The H-UDI is also used for emulator connection. Do not use H-UDI functions when using an emulator. Refer to the appropriate emulator manual for the method of connecting the emulator. The H-UDI consists of six pins: TCK, TMS, TDI, TDO, TRST, and ASEBRK/BRKACK. The pin functions and serial communication protocol conform to the JTAG standards. This LSI has additional six pins for emulator connection: (AUDSYNC, AUDCK, and AUDATA[3] to AUDATA[0]). The pins for emulator connection can also be multiplexed for other functions and are assigned to the module specified by the settings of IPSELR in the PFC. The H-UDI contains two separate TAP controllers, one for controlling the boundary-scan function and another for other functions. Asserting TRST, for example at a power-on reset, activates the boundary-scan TAP controller. To use the TAP controller for other functions, input a switchover command to the H-UDI. The CPU has no access to the boundary-scan TAP controller. Figure 28.1 shows a block diagram of the H-UDI. To initialize the TAP (Test Access Port) controller, control registers and boundary-scan TAP controller, assert TRST active low, or set the TMS pin to 1 and apply TCK for 5 or more cycles. This initialization sequence is independent of the reset pin for this LSI. Other circuits are initialized by the reset pin. The H-UDI has four registers: SDIR, SDDR (SDDRH and SDDRL), and SDINT. SDBSR configures the JTAG-compliant boundary-scan system, SDIR is used for commands, SDDR is used for data, and SDINT is used for H-UDI interrupts. SDIR is directly accessed from the TDI and TDO pins.
Rev. 1.0, 02/03, page 991 of 1294
ASEBRK/BRKACK
Break controller
Interrupt/reset etc
Boundary-scan TAP controller
Pin multiplexer
SDBSR
Decoder
TCK TMS TRST TDI TAP controller
SDIR
SDINT
SDDRH
SDDRL TDO CAN0_NERR/AUDSYNC CAN1_NERR/AUDCK CAN0_TX/AUDATA[0] CAN1_TX/AUDATA[1] CAN0_RX/AUDATA[2] CAN1_RX/AUDATA[3] FSC/AUDSYNC FOE/AUDCK ADTRG/AUDATA[0] FWE/AUDATA[1] FCDE/AUDATA[2] FCE/AUDATA[3]
PFC IPSELR
Pin mutiplexer
Trace controller
Figure 28.1 H-UDI Block Diagram
Rev. 1.0, 02/03, page 992 of 1294
Peripheral bus
Shift register
28.1
Input/Output Pins
Table 28.1 shows the pin configuration for the H-UDI. Table 28.1 Pin Configuration
Pin Name Clock Abbreviation TCK I/O Input Function When Not in Use
1
Functions as the serial clock input pin Open* prescribed in the JTAG standards. Data input to the H-UDI via the TDI pin or data output via the TDO pin is performed in sync with this signal. Mode Select Input Open* Changing this signal in sync with a TCK signal determines the significance of data input via the TDI pin. Its protocol conforms to the JTAG standards (IEEE standards 1149.1).
Mode
TMS
Input
1
Reset
TRST
Input
H-UDI Reset Input Connected This signal is received asynchronously with a to ground 23 TCK signal. Asserting this signal low resets ** the JTAG interface circuit. At power- on, assert the TRST pin low for a given period, whether or not JTAG is used. This differs from the IEEE standards. Data Input Entering this signal in sync with a TCK signal will send data to the H-UDI circuit. Open*
1
Data Input
TDI
Input
Data Output
TDO
Output Data Output Reading this signal in sync with a TCK signal will read out data from the H-UDI circuit. Input/ Emulator Connection Only Output
Open
Emulator
ASEBRK/ BRKACK
Open*
1
Rev. 1.0, 02/03, page 993 of 1294
Pin Name Emulator
Abbreviation AUDSYNC/ AUDCK/ AUDATA[3] to AUDATA[0]
I/O
Function
When Not in Use
4
Output Emulator Connection Open* When bit 13 of IPSELR in the PFC is set to 1, signals are output to the following pins. CAN0_TX/AUDATA[0] CAN1_TX/AUDATA[1] CAN0_RX/AUDATA[2] CAN1_RX/AUDATA[3] CAN0_NERR/AUDCK CAN1_NERR/AUDSYNC When bit 12 of IPSELR in the PFC is set to 1, signals are output to the following pins. ADTRG/AUDATA[0] FWE/AUDATA[1] FCDE/AUDATA[2] FCE/AUDATA[3] FOE/AUDCK FSC/AUDSYNC
Notes: *1. This pin is pulled up in this LSI. Using external pull-up resistors will not affect the use of interrupts or resets via the H-UDI or emulators on the board. *2. Design the TRST pin so that it can retain low while the RESET pin is asserted low at a power on reset and can control reset independently, to use interrupts or resets via the H-UDI or emulators on the board. *3. This pin should be connected to ground, the RESET, or another pin that operates in the same manner as the RESET pin. However, note that connecting this pin to a ground pin will cause the following problem. Since the TRST pin is pulled up within this LSI, a weak current flows when the pin is externally connected to ground. The value of the current is determined by a resistance of the pull-up MOS for the port pin. Although this current does not affect the operation of this LSI, it consumes unnecessary power. *4. Pull up these pins when not using them as emulator pins and they are not in the output state.
The maximum frequency of a TCK (TMS, TDI, and TDO) signal is 20 MHz, or 2 MHz when boundary scan function is used. Set the TCK clock or the CPG of this LSI so that the frequency of TCK is lower than the frequency of the peripheral clock of this LSI.
Rev. 1.0, 02/03, page 994 of 1294
28.2
Boundary Scan TAP Controllers (EXTEST, SAMPLE/PRELOAD, and BYPASS)
The H-UDI contains two separate TAP controllers: one for controlling the boundary-scan function and another for controlling the H-UDI reset and interrupt functions. Assertion of TRST, for example at power-on reset, activates the boundary-scan TAP controller and enables the boundaryscan function prescribed in the JTAG standards. Executing a switchover command to the H-UDI allows usage of the H-UDI reset and H-UDI interrupts. This LSI, however, has the following limitations: * Clock-related pins (EXTAL, XTAL, and CKIO) are out of the scope of the boundary-scan test. * Reset-related pins (RESET, MRESET, and CA) are out of the scope of the boundary-scan test. * H-UDI-related pins (TCK, TDI, TDO, TMS, TRST, and ASEBRK/BRKACK) are out of the scope of the boundary-scan test. * Analog pins (AN0 to AN3, USB_DM, and USB_DP) are out of the scope of the boundaryscan test. * I C pins (I2C0_SDA, I2C0_SCL, I2C1_SDA, and I2C1_SCL) are out of the scope of the boundary-scan test.
2
* To perform EXTEST, assert MRESET pin low, negate the RESET pin high and assert the CA pin low. To perform SAMPLE/PRELOAD, assert the CA pin high and negate the RESET pin low. * To perform the boundary scan (EXTEST, SAMPLE/PRELOAD, or BYPASS), supply a clock signal to the EXTAL pin and perform a power-on reset with the RESET pin. The input clock frequency should be in the range of 1 to 34 MHz. Perform the boundary scan after the poweron oscillation settling time (tOSC1) has elapsed. The supply of a clock signal to the EXTAL pin may be suspended after tOSC1 has elapsed. For details of power-on oscillation settling time, see section 33, Electrical Characteristics. * During the boundary scan (EXTEST, SAMPLE/PRELOAD, and BYPASS), the maximum TCK signal frequency is 2 MHz. * The external controller has 3-bit access to the boundary-scan TAP controller via the H-UDI. Table 28.2 shows the commands supported by the boundary-scan TAP controller.
Rev. 1.0, 02/03, page 995 of 1294
Table 28.2 Commands Supported by Boundary-Scan TAP Controller
Bit 2 0 0 0 Bit 1 0 0 1 Bit 0 0 1 1 Description EXTEST SAMPLE/PRELOAD H-UDI (switchover command) BYPASS mode
Other than above
28.2.1
Boundary Scan Register (SDBSR)
SDBSR is a shift register, located on the PAD, for controlling the input/output pins. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary-scan test complying with the JTAG standards (IEEE1149.1) can be carried out. Table 28.3 shows the correspondence between pins of this LSI and the SDBSR values.
Rev. 1.0, 02/03, page 996 of 1294
Table 28.3 (1)
Bit
SDBSR Configuration
I/O* Bit 466 IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 Abbreviation HSPI_TX HSPI_TX HSPI_TX HSPI_RX HSPI_RX HSPI_RX SSI1_SDATA/HAC_SD_OUT1 SSI1_SDATA/HAC_SD_OUT1 SSI1_SDATA/HAC_SD_OUT1 STATUS0 STATUS0 STATUS0 SSI0_SCK/HAC_SD_IN0/BS2 SSI0_SCK/HAC_SD_IN0/BS2 SSI0_SCK/HAC_SD_IN0/BS2 SSI0_WS/HAC_SYNC0 SSI0_WS/HAC_SYNC0 SSI0_WS/HAC_SYNC0 SSI0_SDATA/HAC_SD_OUT0 SSI0_SDATA/HAC_SD_OUT0 SSI0_SDATA/HAC_SD_OUT0 HAC_RES HAC_RES HAC_RES RDY RDY RDY HAC_BIT_CLK0 HAC_BIT_CLK0 HAC_BIT_CLK0 DCK DCK DCK SSI1_SCK/HAC_SD_IN1 I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN
Abbreviation From TDI
499 498 497 496 495 494 493 492 491 490 489 488 487 486 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467
SCIF2_TXD SCIF2_TXD SCIF2_TXD SCIF1_CLK SCIF1_CLK SCIF1_CLK SCIF2_CLK SCIF2_CLK SCIF2_CLK NMI NMI NMI CMT_CTR3 CMT_CTR3 CMT_CTR3 CMT_CTR2 CMT_CTR2 CMT_CTR2 CMT_CTR1 CMT_CTR1 CMT_CTR1 CMT_CTR0/TCLK CMT_CTR0/TCLK CMT_CTR0/TCLK STATUS1 STATUS1 STATUS1 HSPI_CLK HSPI_CLK HSPI_CLK HSPI_CS HSPI_CS HSPI_CS
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 997 of 1294
Table 28.3 (2)
Bit 432 431 430 429 428 427 426 425 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402
SDBSR Configuration
I/O* OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Bit 401 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 Abbreviation MFI-D9/LCD_DATA9 MFI-D1/LCD_DATA1 MFI-D1/LCD_DATA1 MFI-D1/LCD_DATA1 MFI-D10/LCD_DATA10 MFI-D10/LCD_DATA10 MFI-D10/LCD_DATA10 MFI-D2/LCD_DATA2/IRQ6 MFI-D2/LCD_DATA2/IRQ6 MFI-D2/LCD_DATA2/IRQ6 MFI-D11/LCD_DATA11 MFI-D11/LCD_DATA11 MFI-D11/LCD_DATA11 MFI-D3/LCD_DATA3/IRQ7 MFI-D3/LCD_DATA3/IRQ7 MFI-D3/LCD_DATA3/IRQ7 CS1 CS1 CS1 CS2 CS2 CS2 MFI-D12/LCD_DATA12 MFI-D12/LCD_DATA12 MFI-D12/LCD_DATA12 MFI-D4/LCD_DATA4/DREQ2 MFI-D4/LCD_DATA4/DREQ2 MFI-D4/LCD_DATA4/DREQ2 MFI-D13/LCD_DATA13 MFI-D13/LCD_DATA13 MFI-D13/LCD_DATA13 I/O* Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control
Abbreviation SSI1_SCK/HAC_SD_IN1 SSI1_SCK/HAC_SD_IN1 SSI1_WS/HAC_SYNC1 SSI1_WS/HAC_SYNC1 SSI1_WS/HAC_SYNC1 HAC_BIT_CLK1 HAC_BIT_CLK1 HAC_BIT_CLK1 VCPWC/IRQ4 VCPWC/IRQ4 VCPWC/IRQ4 VEPWC/IRQ5 VEPWC/IRQ5 VEPWC/IRQ5 BREQ BREQ BREQ MFI-D8/LCD_DATA8 MFI-D8/LCD_DATA8 MFI-D8/LCD_DATA8 MFI-D0/LCD_DATA0 MFI-D0/LCD_DATA0 MFI-D0/LCD_DATA0 CS0 CS0 CS0 BACK BACK BACK MFI-D9/LCD_DATA9 MFI-D9/LCD_DATA9
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 998 of 1294
Table 28.3 (3)
Bit 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341
SDBSR Configuration
I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control Bit 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 Abbreviation MFI-CS/LCD_DON MFI-CS/LCD_DON MFI-CS/LCD_DON MFI-E/LCD_CL1 MFI-E/LCD_CL1 MFI-E/LCD_CL1 MFI-MD/LCD_CL2 MFI-MD/LCD_CL2 MFI-MD/LCD_CL2 CS6 CS6 CS6 A0 A0 A0 MFI-RS/LCD_M_DISP MFI-RS/LCD_M_DISP MFI-RS/LCD_M_DISP MFI-RW/LCD_FLM MFI-RW/LCD_FLM MFI-RW/LCD_FLM BS BS BS A1 A1 A1 D0 D0 D0 I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control
Abbreviation MFI-D5/LCD_DATA5/DRAK2/DACK2 MFI-D5/LCD_DATA5/DRAK2/DACK2 MFI-D5/LCD_DATA5/DRAK2/DACK2 CS4 CS4 CS4 A20 A20 A20 MFI-D14/LCD_DATA14 MFI-D14/LCD_DATA14 MFI-D14/LCD_DATA14 MFI-D6/LCD_DATA6/DREQ3 MFI-D6/LCD_DATA6/DREQ3 MFI-D6/LCD_DATA6/DREQ3 MFI-D15/LCD_DATA15 MFI-D15/LCD_DATA15 MFI-D15/LCD_DATA15 MFI-D7/LCD_DATA7/DRAK3/DACK3 MFI-D7/LCD_DATA7/DRAK3/DACK3 MFI-D7/LCD_DATA7/DRAK3/DACK3 CS5 CS5 CS5 A21 A21 A21 MFI-INT/LCD_CLK MFI-INT/LCD_CLK MFI-INT/LCD_CLK
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 999 of 1294
Table 28.3 (4)
Bit 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281
SDBSR Configuration
I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control Bit 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 Abbreviation D6 D6 D6 D10 D10 D10 D11 D11 D11 D8 D8 D8 D7 D7 D7 RD/CASS/FRAME RD/CASS/FRAME RD/CASS/FRAME RD/WR RD/WR RD/WR A2 A2 A2 CKE CKE CKE WE1/DQM1 WE1/DQM1 WE1/DQM1 I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control
Abbreviation D15 D15 D15 D3 D3 D3 D1 D1 D1 D14 D14 D14 D2 D2 D2 D13 D13 D13 D12 D12 D12 D5 D5 D5 D4 D4 D4 D9 D9 D9
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 1000 of 1294
Table 28.3 (5)
Bit 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 228 231 230 229 228 227 226 225 224 223 222 221
SDBSR Configuration
I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control Bit 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 Abbreviation A11 A11 A11 A12 A12 A12 A13 A13 A13 A14 A14 A14 A15 A15 A15 A18 A18 A18 WE3/DQM3 WE3/DQM3 WE3/DQM3 WE2/DQM2 WE2/DQM2 WE2/DQM2 CS3 CS3 CS3 RAS RAS RAS I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control
Abbreviation WE0/DQM0 WE0/DQM0 WE0/DQM0 A3 A3 A3 A4 A4 A4 A5 A5 A5 A6 A6 A6 A7 A7 A7 A17 A17 A17 A8 A8 A8 A9 A9 A9 A10 A10 A10
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 1001 of 1294
Table 28.3 (6)
Bit 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161
SDBSR Configuration
I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control Bit 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 Abbreviation D18 D18 D18 D29 D29 D29 D30 D30 D30 D17 D17 D17 D31 D31 D31 D16 D16 D16 D28 D28 D28 D20 D20 D20 CAN1_TX/AUDATA[1] CAN1_TX/AUDATA[1] CAN1_TX/AUDATA[1] CAN0_TX/AUDATA[0] CAN0_TX/AUDATA[0] CAN0_TX/AUDATA[0] I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control
Abbreviation A16 A16 A16 A19 A19 A19 D23 D23 D23 D24 D24 D24 D22 D22 D22 D25 D25 D25 D21 D21 D21 D26 D26 D26 D27 D27 D27 D19 D19 D19
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 1002 of 1294
Table 28.3 (7)
Bit 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101
SDBSR Configuration
I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control Bit 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 Abbreviation IRL2 IRL2 IRL2 IRL3 IRL3 IRL3 Reserved/AUDATA[1] Reserved/AUDATA[1] Reserved/AUDATA[1] ADTRG/AUDATA[0] ADTRG/AUDATA[0] ADTRG/AUDATA[0] Reserved/AUDATA[3] Reserved/AUDATA[3] Reserved/AUDATA[3] Reserved/AUDATA[2] Reserved/AUDATA[2] Reserved/AUDATA[2] Reserved/AUDSYNC Reserved/AUDSYNC Reserved/AUDSYNC Reserved/AUDCK Reserved/AUDCK Reserved/AUDCK MD8 MD7 MD7 MD7 MD5 MD5 I/O* IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN IN OUT Control IN OUT
Abbreviation A23 A23 A23 A22 A22 A22 CAN1_RX/AUDATA[3] CAN1_RX/AUDATA[3] CAN1_RX/AUDATA[3] CAN0_RX/AUDATA[2] CAN0_RX/AUDATA[2] CAN0_RX/AUDATA[2] A25 A25 A25 A24 A24 A24 CAN1_NERR/AUDSYNC CAN1_NERR/AUDSYNC CAN1_NERR/AUDSYNC CAN0_NERR/AUDCK CAN0_NERR/AUDCK CAN0_NERR/AUDCK IRL0 IRL0 IRL0 IRL1 IRL1 IRL1
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 1003 of 1294
Table 28.3 (8)
Bit 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SDBSR Configuration
I/O* Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT Bit 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 Abbreviation MD4/CE2B MD3/CE2A MD3/CE2A MD3/CE2A DRAK0 DRAK0 DRAK0 MD1 SCIF0_TXD SCIF0_TXD SCIF0_TXD SCIF0_RXD SCIF0_RXD SCIF0_RXD MD2 MD0 SCIF0_CLK SCIF0_CLK SCIF0_CLK SCIF1_RTS SCIF1_RTS SCIF1_RTS SCIF2_RTS SCIF2_RTS SCIF2_RTS SCIF1_CTS SCIF1_CTS SCIF1_CTS SCIF2_CTS SCIF2_CTS I/O* Control IN OUT Control IN OUT Control IN IN OUT Control IN OUT Control IN IN IN OUT Control IN OUT Control IN OUT Control IN OUT Control IN OUT
Abbreviation MD5 MD6/IOIS16 MD6/IOIS16 MD6/IOIS16 DREQ1 DREQ1 DREQ1 DREQ0 DREQ0 DREQ0 USB_OVC USB_OVC USB_OVC DACK1 DACK1 DACK1 DRAK1 DRAK1 DRAK1 UCLK UCLK UCLK DACK0 DACK0 DACK0 USB_PENC USB_PENC USB_PENC MD4/CE2B MD4/CE2B
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
Rev. 1.0, 02/03, page 1004 of 1294
Table 28.3 (9)
Bit 10 9 8 7 6 5
SDBSR Configuration
I/O* Control IN OUT Control IN OUT Bit 4 3 2 1 Abbreviation SCIF2_RXD SCIF1_TXD SCIF1_TXD SCIF1_TXD To TDO I/O* Control IN OUT Control
Abbreviation SCIF2_CTS SCIF1_RXD SCIF1_RXD SCIF1_RXD SCIF2_RXD SCIF2_RXD
Note: * Control is an active-high signal. When Control is driven high, the corresponding pin is driven according to the OUT value.
28.3
Register Descriptions
The H-UDI has the following registers. For details of the addresses of SDIR, SDDR (SDDRH and SDDRL), and SDINT and the status in each operating mode, see section 32, List of Registers. Table 28.4 Register Configuration (1)
CPU Side Register Name Instruction register Data register H Data register L Interrupt source register Bypass register Boundary scan register Abbrev. SDIR R/W P4 Address R H'FFF0 0000 Area 7 Address Size H'1FF0 0000 H'1FF0 0008 H'1FF0 000A H'1FF0 0014 -- -- 16 Initial Value*1 H'FFFF Sync Clock Pck
SDDR/SDDRH R/W H'FFF0 0008 SDDRL SDINT SDBPR SDBSR R/W H'FFF0 000A R/W H'FFF0 0014 -- -- -- --
32/16 Undefined Pck 16 16 -- -- Undefined Pck H'000 Pck
Undefined -- Undefined --
Rev. 1.0, 02/03, page 1005 of 1294
Table 28.4 Register Configuration (2)
H-UDI Side Register Name Instruction register Data register H Data register L Interrupt source register Bypass register Boundary scan register Abbrev. SDIR R/W R/W Size 32 -- -- 32 1 -- Initial Value*1 H'FFFF FFFD (Fixed value*2) -- -- H'0000 0000 Undefined Undefined Sync Clock Pck Pck Pck Pck -- --
SDDR/SDDRH -- SDDRL SDINT SDBPR SDBSR -- W*3 R/W R/W
Table 28.4 Register Configuration (3)
Power-on Reset by RESET Pin/WDT/ H-UDI H'FFFF*4 Manual Reset by RESET Pin/WDT/ Multiple Exception Retained Retained Retained Retained Standby Sleep by Sleep Instruction/ Deep Sleep Retained Retained Retained Retained by Software/ Each by Hardware Module * Retained Retained Retained Retained
Register Name Instruction register Data register H Data register L Interrupt source register
Abbrev. SDIR
SDDR/SDDRH Undefined SDDRL SDINT Undefined H'0000
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. *1. Initialized when the TRST pin is low or the TAP controller is in the Test-Logic-Reset state. *2. Always read as the fixed value (H'FFFF FFFD) from the H-UDI side. *3. Using the H-UDI interrupt command sets the LSB to 1. *4. Reserved bits are read as undefined values. For details, see each of the register descriptions.
Rev. 1.0, 02/03, page 1006 of 1294
28.3.1
Instruction Register (SDIR)
SDIR is a 16-bit register that is read only for the CPU. Set a command via the serial input (TDI). SDIR is initialized when TRST is driven low or the TAP controller enters the Test-Logic-Reset state. The H-UDI can write to SDIR irrespective of the CPU mode. Operation is not guaranteed when a reserved command is set to this register.
Bit: Initial value: R/W: 15 TI7 1 R 14 TI6 1 R 13 TI5 1 R 12 TI4 1 R 11 TI3 1 R 10 TI2 1 R 9 TI1 1 R 8 TI0 1 R 7 1 R 6 1 R 5 1 R 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R
Bit
Bit Name Initial Value
R/W R
Description Test Instruction Bit 0110xxxx: H-UDI, reset, negate 0111xxxx: H-UDI, reset, assert 101xxxxx: H-UDI interrupt 11111111: Initial value Other than above: Setting prohibited
15 to 8 TI7 to TI0 All 1
7 to 0
--
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
28.3.2
Data Register H and L (SDDRH, SDDRL)
SDDR is a 32-bit register that comprises two 16-bit registers: SDDRH and SDDRL. SDDRH and SDDRL can be read from/written to by the CPU. The register value is not initialized by the CPU reset but is initialized by TRST. * SDDRH
Bit: Initial value: R/W: 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W
* SDDRL
Bit: Initial value: R/W: 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W
Rev. 1.0, 02/03, page 1007 of 1294
28.3.3
Interrupt Source Register (SDINT)
SDINT is a 16-bit register that can be read from/written to by the CPU. Specifying an H-UDI interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While SDIR contains an H-UDI interrupt command, SDINT is connected between the TDI and TDO pins. SDINT can be read as a 32-bit register; the upper 16 bits will be 0 and the lower 16 bits represent the SDINT register. The CPU can write 0 alone to the INTREQ bit. As long as this bit is set to 1, an interrupt request will continue to be generated. Therefore, the INTREQ bit must be cleared to 0 during the interrupt handler. The SDINT register is initialized when TRST is driven low or the TAP controller enters the Test-Logic-Reset state.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0
INTREQ
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Interrupt Request Indicates whether or not an interrupt request by an HUDI interrupt command has occurred. Clearing this bit to 0 by the CPU cancels an interrupt request. Writing 1 to this bit retains the previous value.
15 to 1 --
0
INTREQ
0
R/W
Rev. 1.0, 02/03, page 1008 of 1294
28.4
28.4.1
Operation
TAP Control
Figure 28.2 shows the internal states of TAP controller. The state transitions conform to the JTAG standards. * State transitions occur according to the TMS value at the rising edge of a TCK signal. * The TDI value is sampled at the rising edge of a TCK signal and shifted at the falling edge of a TCK signal. * The TDO value is changed at the falling edge of a TCK signal. The TDO signal is in a Hi-Z state other than in the Shift-DR or Shift-IR state. * Clearing TRST to 0 places the TAP controller into the Test-Logic-Reset state asynchronously with a TCK signal.
1 Test-logic-reset 0 0 Run-test/idle 1 Select-DR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 1 1 Select-IR-scan 0 1
0
0
Figure 28.2 TAP Controller State Transitions
Rev. 1.0, 02/03, page 1009 of 1294
28.4.2
H-UDI Reset
A power-on reset can be performed with an SDIR command. Sending an H-UDI reset assert command and then an H-UDI reset negate command from the H-UDI pin resets the H-UDI (see figure 28.3). The required time from the H-UDI reset assert command to H-UDI reset negate command is the same as the time for holding the reset pin low for a power-on reset.
H-UDI pin
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Normal
Reset
Reset processing
Figure 28.3 H-UDI Reset 28.4.3 H-UDI Interrupt
To generate an interrupt using the H-UDI interrupt function, set the appropriate command in SDIR via the H-UDI. An H-UDI interrupt is a general exception/interrupt operation, resulting in branching to the VBR address. The H-UDI returns from the interrupt handler with a RTE instruction. When an H-UDI interrupt occurs, the exception code H'600 is stored in the interrupt event register (INTEVT). The priority level for the H-UDI interrupt is controlled by bits IPR3 to IPR0 in IPRC. Specifying the appropriate command (Update-IR) sets the INTREQ bit to 1 and then asserts an HUDI interrupt request signal. Since this signal is not negated until the INTREQ bit is cleared to 0 by software, the interrupt request will not be missed. While SDIR contains an H-UDI interrupt command, SDINT is connected between the TDI and TDO pins.
Rev. 1.0, 02/03, page 1010 of 1294
28.5
Usage Notes
* Once an SDIR command is set, it will not be modified unless a TRST signal is asserted, the TAP controller enters the Test-Logic-Reset state, or other command is re-issued via the HUDI. * An H-UDI interrupt or an H-UDI reset can be accepted to cancel sleep mode. Neither of these signals can be accepted in standby mode. * H-UDI functions cannot be used in standby mode. To retain the TAP controller state before and after standby mode, drive a TCK signal high when placing this LSI into standby mode. * The H-UDI can also be used for emulator connection. Therefore, H-UDI functions cannot be used when an emulator is used.
Rev. 1.0, 02/03, page 1011 of 1294
Rev. 1.0, 02/03, page 1012 of 1294
Section 29 A/D Converter (ADC)
This LSI includes a 10-bit successive-approximation A/D converter with a selection of up to four analog input channels.
29.1
Features
The A/D converter has the following features. * 10-bit resolution * 4 input channels * High-speed conversion Conversion time: maximum 8 s per channel (when Pck = 34 MHz with CKSL[1:0] = 01) * Three conversion modes Single mode: A/D conversion of one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Four data registers A/D conversion results are transferred for storage into 16-bit data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at the end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. * A/D conversion end signal can be switched Interrupt request or DMAC activation can be selected by the DMASL bit in A/D control/status register (ADCSR). * Absolute error: 4 LSB
Rev. 1.0, 02/03, page 1013 of 1294
Figure 29.1 shows a block diagram of the A/D converter.
Off-chip
On-chip ADC module
A/D converter
Bus interface
AVCC_ADC 10-bit A/D
Successive approximation register
ADDRC
AVSS_ADC
AN0 AN1 AN2 AN3 Analog multiplexer
+
-
Control circuit Comparator Sample-andhold circuit
ADDRD
ADDRA
ADDRB
ADCSR
Bus interface
Module data bus
Peripheral bus Interface
ADI
ADTRG
Legend: ADCSR ADDRA ADDRB ADDRC ADDRD : A/D conversion control/status register : A/D conversion data register A : A/D conversion data register B : A/D conversion data register C : A/D conversion data register D
Figure 29.1 A/D Converter Block Diagram
Rev. 1.0, 02/03, page 1014 of 1294
29.2
Input/Output Pins
Table 29.1 shows the pin configuration for the A/D converter. AVCC_ADC and AVSS_ADC are the power supply for the analog circuits in the A/D converter. AVCC_ADC also functions as the A/D converter reference voltage. Table 29.1 Pin Configuration
Pin Name Analog power-supply Analog ground Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 A/D external trigger input Abbreviation AVCC_ADC AVSS_ADC AN0 AN1 AN2 AN3 ADTRG I/O Input Input Input Input Input Input Input Function Analog power supply and A/D conversion reference voltage Analog ground Analog input Analog input Analog input Analog input External trigger input for starting A/D conversion
Rev. 1.0, 02/03, page 1015 of 1294
29.3
Register Descriptions
The A/D converter has the following registers. For details of register addresses and register states during each process, see section 32, List of Register. Table 29.2 Register Configuration (1)
Register Name A/D conversion data register A A/D conversion data register B A/D conversion data register C A/D conversion data register D Abbrev. ADDRA ADDRB ADDRC ADDRD R/W R R R R R/W*
2
P4 Address H'FE28 0000 H'FE28 0002 H'FE28 0004 H'FE28 0006 H'FE28 0008
Area 7 Address Size H'1E28 0000 H'1E28 0002 H'1E28 0004 H'1E28 0006 H'1E28 0008 16 16 16 16 16
Sync Clock Pck Pck Pck Pck Pck
A/D conversion control/status register ADCSR
Table 29.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'0000 H'0000 H'0000 H'0000 H'0040 Standby Manual Reset by by RESET Sleep Software/ by Sleep Pin/WDT/ Each Instruction/ by Multiple Exception Deep Sleep Hardware Module H'0000 H'0000 H'0000 H'0000 H'0040 Retained Retained Retained Retained Retained * H'0000*1 H'0000*1 H'0000*1 H'0000*1 H'0040*1
Register Name A/D conversion data register A A/D conversion data register B A/D conversion data register C A/D conversion data register D
Abbrev. ADDRA ADDRB ADDRC ADDRD
A/D conversion control/status register ADCSR
Notes: *
After exiting hardware standby mode, this LSI enters the power-on reset state by the RESET pin. *1. Before entering module standby or software standby mode, check that A/D conversion is not in progress. If standby mode is entered while A/D conversion is in progress, correct register values are not guaranteed. *2. Only 0 can be written to bit 15 for clearing the flag.
Rev. 1.0, 02/03, page 1016 of 1294
29.3.1
A/D Conversion Data Registers A to D (ADDRA to ADDRD)
ADDR are 16-bit read-only registers that store the results of A/D conversion, comprising 4 registers from A to D. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D conversion data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte (bits 15 to 8) of the A/D conversion data register. The lower 2 bits are stored in the lower byte (bits 7 and 6). Bits 5 to 0 of an A/D conversion data register are always read as 0. Table 29.3 indicates the pairings of analog input channels and data registers ADDRA to ADDRD.
Bit: Initial value: R/W: 15
AD9
14
AD8
13
AD7
12
AD6
11
AD5
10
AD4
9
AD3
8
AD2
7
AD1
6
AD0
5 0 R
4 0 R
3 0 R
2 0 R
1 0 R
0 0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
Bit 15 to 6 5 to 0
Bit Name AD9 to AD0 --
Initial Value All 0 All 0
R/W R R
Description Bit Data (10 bits) Reserved These bits are always read as 0, and the write value should always be 0.
Table 29.3 Analog Input Channels and Corresponding A/D Conversion Data Registers
Analog Input Channel AN0 AN1 AN2 AN3 A/D Conversion Data Register ADDRA ADDRB ADDRC ADDRD
Rev. 1.0, 02/03, page 1017 of 1294
29.3.2
A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that controls A/D conversion operations and displays the A/D conversion status.
Bit: 15
ADF
14
ADIE
13
12
11
10
9 0 R
8 0 R
7
6
5
4
MDS0
3 0 R
2 0 R
1
CH1
0
CH0
ADST DMASL TRGE1 TRGE0
CKSL1 CKSL0 MDS1
Initial value: 0 0 R/W: R/(W)* R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15
Bit Name ADF
Initial Value 0
R/W R/(W)*
Description A/D End Flag A status flag that indicates the end of A/D conversion. [Clearing conditions] * * When 0 is written after reading ADF = 1 with ADF = 1 When ADDR is read with DMASL = 1 (DMA transfer)
Note: If 1 is written, the previous value is retained. [Setting conditions] * * Single mode: A/D conversion ends Multi mode: A/D conversion has cycled through the selected channels (A/D conversion cycles through the selected channels) Scan mode: A/D conversion has cycled through the selected channels (A/D conversion is continuously repeated for the selected channels)
*
When operation is stopped during conversion in multi mode or scan mode, the ADF bit is not set. 14 ADIE 0 R/W A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Do not change the ADIE bit setting during A/D conversion. 0: A/D conversion end interrupt (ADI) request is disabled 1: A/D conversion end interrupt (ADI) request is enabled
Rev. 1.0, 02/03, page 1018 of 1294
Bit 13
Bit Name ADST
Initial Value 0
R/W R/W
Description A/D Start Starts or stops A/D conversion. This bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input (ADTRG) pin. 0: A/D conversion is stopped 1: * Single mode: A/D conversion starts. This bit is cleared to 0 automatically when conversion on the specified channel ends. Even when the ADST bit is cleared to 0 (by software), A/D conversion does not stop (0 cannot be written to this bit during A/D conversion). Multi mode: A/D conversion starts. This bit is cleared to 0 automatically when conversion on the specified channels has been performed for one cycle. When the ADST bit is cleared to 0 (by software), A/D conversion stops when the currently executed channel ends. Scan mode: A/D conversion starts. A/D conversion continues without a break until the ADST bit is cleared to 0 by software or until all registers are initialized by a power-on or manual reset or in hardware standby, module standby, or software standby mode. For the standby modes, refer to section 29.7.4, Notes on Standby Modes.
*
*
12
DMASL
0
R/W
DMAC Select Selects an interrupt or activation of the DMAC due to the end of A/D conversion. Do not change the DMASL bit setting during A/D conversion. 0: An interrupt by the end of A/D conversion is selected 1: Activation of the DMAC by the end of A/D conversion is selected
Rev. 1.0, 02/03, page 1019 of 1294
Bit 11 10
Bit Name TRGE1 TRGE0
Initial Value 0 0
R/W R/W R/W
Description Trigger Enable External trigger input permits or prohibits A/D conversion. These bits must be set while conversion is stopped. 00: When an external trigger is input, A/D conversion does not start 01: Setting prohibited 10: Setting prohibited 11: A/D conversion starts at the falling edge of an input signal from the external trigger input pin (ADTRG) Note: Clear bits TRGE1 and TRGE0 to 0 before switching the trigger signal.
9, 8
All 0
R
Reserved These bits are always read as 0, and the write value should always be 0.
7 6
CKSL1 CKSL0
0 1
R/W R/W
Clock Select These bits select the A/D conversion clock division ratio. 00: Pck/4 01: Pck/8 10: Pck/16 11: Pck/32 Note: For the Pck and clock division ratio settings, refer to section 29.7.3, Pck and Clock Division Ratio Settings.
5 4
MDS1 MDS0
0 0
R/W R/W
Conversion Mode Select These bits select single mode, multi mode, or scan mode. For details on modes, see section 29.4, Operation. The combination of MDS1 = 0 and MDS0 = 1 should not be selected. 00: Single mode 01: Setting prohibited 10: Multi mode 11: Scan mode
3, 2
All 0
R
Reserved These bits are always read as 0, and the write value should always be 0.
Rev. 1.0, 02/03, page 1020 of 1294
Bit 1 0
Bit Name CH1 CH0
Initial Value 0 0
R/W R/W R/W
Description Channel Select These bits select the analog input channels together with the MDS1 bits. Select the input channels after clearing the ADST bit to 0. Single Mode (MDS1 = 0): 00: AN0 01: AN1 10: AN2 11: AN3 Multi Mode or Scan Mode (MDS1 = 1): 00: AN0 01: AN0 and AN1 10: AN0 to AN2 11: AN0 to AN3
Note:
*
Only 0 can be written for clearing the flag.
29.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three operating modes: single mode, multi mode, and scan mode. To avoid malfunction, switch operating modes while the ADST bit of ADCSR is 0. Changing operating modes and channels and setting the ADST bit can be performed simultaneously. 29.4.1 Single Mode
In single mode, an analog input for the specified channel is converted once as shown below. 1. A/D conversion of the selected channel starts when the ADST bit of ADCSR is set to 1 by software or an external trigger input. The ADST bit holds 1 during A/D conversion and is automatically cleared to 0 when the A/D conversion ends. 2. When A/D conversion ends, the conversion results are transmitted to the A/D conversion data register that corresponds to the channel. 3. When A/D conversion ends, the ADF bit of ADCSR is set to 1. If the ADIE bit in ADCSR is also set to 1, an ADI interrupt is requested at this time. 4. Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit.
Rev. 1.0, 02/03, page 1021 of 1294
Typical operations when channel 1 (AN1) is selected in single mode are described below. Figure 29.2 shows a timing diagram for this example. 1. Select single mode as the operating mode (MDS1 = 0 and MDS0 = 0), AN1 as the input channel (CH1 = 0 and CH0 = 1), and enable A/D interrupt requests (ADIE = 1). Then start A/D conversion (ADST = 1). 2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At the same time, the ADF bit is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1, ADIE = 1, and DMASL = 0, an ADI interrupt is generated. 4. The A/D interrupt processing routine starts. 5. The A/D interrupt processing routine reads and processes the A/D conversion result (ADDRB). 6. After reading ADF = 1, write 0 in the ADF bit. 7. Execution of the A/D interrupt processing routine ends. After this, when the ADST bit is set to 1, A/D conversion starts and steps 2 to 7 are repeated.
A/D conversion Set* starts ADST Clear* ADF ADI Channel 0 (AN0) Channel 1 (AN1) Channel 2 (AN2) Channel 3 (AN3) ADDRA Read result ADDRB ADDRC ADDRD Note: * Vertical arrows ( ) indicate instruction execution by software. A/D conversion result (1) Read result A/D conversion result (2) Idle
A/D conversion (1)
Set*
Clear*
Interrupt occurs Idle Idle Idle Idle
A/D conversion (2)
Idle
Figure 29.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Rev. 1.0, 02/03, page 1022 of 1294
29.4.2
Multi Mode
In multi mode, analog inputs for the specified channels (one or more) are converted once each as shown below. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts with the first channel (AN0). 2. When multiple channels are selected, the input signal for the second channel is converted after the A/D conversion for the first channel ends. 3. When conversion of each channel ends, the conversion results are transmitted to the A/D conversion data register that corresponds to the channel. 4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. 5. When A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter becomes idle. When the ADST bit is cleared to 0 during A/D conversion, the conversion is halted and the A/D converter becomes idle. Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit. Typical operations when three channels (AN0 to AN2) are selected in multi mode are described below. Figure 29.3 shows a timing diagram for this example. 1. Select multi mode as the operating mode (MDS1 = 1 and MDS0 = 0) and AN0 to AN2 as the analog input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When the conversion ends, the result is transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 3. Conversion proceeds in the same way up to the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) ends, the ADF bit is set to 1 and the ADST bit is cleared to 0 to stop A/D conversion. If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is generated after A/D conversion ends.
Rev. 1.0, 02/03, page 1023 of 1294
A/D conversion execution Set*
ADST
Clear*
Clear*
ADF ADI
Interrupt occurs Channel 0 (AN0) Channel 1 (AN1) Channel 2 (AN2) Idle
A/D conversion (1)
Idle
Idle
A/D conversion (2)
Idle
Idle
A/D conversion (3)
Idle
Channel 3 (AN3)
Idle
ADDRA
A/D conversion result (1)
ADDRB
A/D conversion result (2)
ADDRC
A/D conversion result (3)
ADDRD
Note: * Vertical arrows ( ) indicate instruction execution by software.
Figure 29.3 Example of A/D Converter Operation (Multi Mode, Three Channels AN0 to AN2 Selected)
Rev. 1.0, 02/03, page 1024 of 1294
29.4.3
Scan Mode
In scan mode, analog inputs for a maximum of four specified channels are converted in succession as shown below. 1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D conversion starts with the first channel (AN0). 2. A/D conversion for the first channel starts. When multiple channels are selected, the input signal for the second channel (AN1) is converted after the A/D conversion for the first channel ends. 3. When conversion of each channel ends, the conversion results are transmitted to the ADDRA to ADDRD data register that corresponds to the channel. 4. When conversion of all selected channel ends, the ADF bit of ADCSR is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is generated at this time. 5. While the ADST bit is set to 1, it is not automatically cleared, but steps 2 to 4 above are repeated. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter becomes idle.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described below. Figure 29.4 shows a timing diagram for this example. 1. Select scan mode as the operating mode (MDS1 = 1 and MDS0 = 1) and AN0 to AN2 as the input channels (CH1 = 1 and CH0 = 0). Then start A/D conversion (ADST = 1). 2. A/D conversion of the first channel (AN0) starts. When the A/D conversion ends, the result is transferred into ADDRA. Next, the second channel (AN1) is selected automatically and A/D conversion starts. 3. Conversion proceeds in the same way up to the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF bit is set to 1, the first channel (AN0) is selected again, and A/D conversion is consecutively performed. (In multi mode, A/D conversion ends when the selected channels have been cycled through. However, in scan mode, after the selected channels have been cycled through, A/D conversion starts again from the first channel and is consecutively repeated.) If the DMASL bit is cleared to 0 and the ADIE bit is set to 1 at this time, an ADI interrupt is generated after A/D conversion ends. 5. While the ADST bit is set to 1, steps 2 to 4 above are repeated. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0).
Rev. 1.0, 02/03, page 1025 of 1294
Consecutive A/D conversion execution Set*1 ADST Clear*1 ADF ADI Interrupt occurs Channel 0 (AN0) Channel 1 (AN1) Channel 2 (AN2) Channel 3 (AN3) ADDRA ADDRB ADDRC ADDRD Notes: *1. Vertical arrows ( ) indicate instruction execution by software.
*2. Data being converted is ignored.
Clear*1
Idle
A/D conversion (1)
Idle
A/D conversion (2)
A/D conversion (4)
Idle
A/D conversion (5) *2
Idle Idle
Idle
A/D conversion (3)
Idle
Idle
Idle A/D conversion result (1) A/D conversion result (4)
A/D conversion result (5)
A/D conversion result (2) A/D conversion result (3)
Figure 29.4 Example of A/D Converter Operation (Scan Mode, Three Channels AN0 to AN2 Selected)
Rev. 1.0, 02/03, page 1026 of 1294
* Scan Mode Operation: After A/D conversion is performed, the interval for storing the result in the corresponding data register is fixed at 256 cycles when Pck/8 is selected as the clock division ratio. Therefore, data is stored in the data registers every 256 cycles. After an interrupt occurs, data should be read within 256 cycles. After this read, data should be read at the specified intervals.
Pck ADDRA write enable signal ADDRB write enable signal ADDRC write enable signal ADDRD write enable signal ADDRA
A/D conversion 1 A/D conversion 1'
256 clocks ADDRB
A/D conversion 2
256 clocks
A/D conversion 2'
256 clocks ADDRC
A/D conversion 3 A/D conversion 3'
256 clocks ADDRD
A/D conversion 4 A/D conversion 4'
256 clocks Read signal (read interval) Read at intervals of 256 clocks Read of A/D conversion 1 ADF Cycles through all selected channels (AN0 to AN3) Read of A/D conversion 2 Read of A/D conversion 3 Read of A/D conversion 4 Read of A/D conversion 1'
Interrupt signal ADI Interrupt occurs
Figure 29.5 Timing for Data Write when Four Channels are Selected in Multi Mode
Rev. 1.0, 02/03, page 1027 of 1294
29.4.4
A/D Conversion Time
Table 29.4 indicates the A/D conversion time. Table 29.4 A/D Conversion Time
Pck/4 Conversion Time Type A/D conversion time for the first conversion A/D conversion time for the second and subsequent conversions (multi mode or scan mode) Min 131 -- Max 134 128 Min 259 -- Pck/8 Max 266 256 Pck/16 Min 515 -- Max 530 512 Pck/32 Min 1027 -- Max 1058 1024
Notes: 1. To change the channel during A/D conversion in multi mode or scan mode, clear the ADST bit to 0 to stop A/D conversion. Wait for the A/D conversion time shown above before changing the channel. 2. Values in the table are the numbers of states (one state is one peripheral clock (Pck) cycle). 3. The conversion time for the second and subsequent conversions is fixed.
Rev. 1.0, 02/03, page 1028 of 1294
29.4.5
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE1 and TRGE0 bits in ADCSR are both set to 1, an external trigger input is enabled at the ADTRG pin. The ADST bit in ADCSR is set to 1 at the falling edge of the ADTRG pin, thus starting A/D conversion. Other operations, regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 29.6 shows this timing.
Pck ADTRG ADTRG shift 1 ADTRG shift 2
ADTRG shift 3
Internal start trigger signal
ADST A/D conversion Note: The minimum pulse width of ADTRG must be at least Pck x 2.
Figure 29.6 External Trigger Input Timing
Rev. 1.0, 02/03, page 1029 of 1294
29.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request is enabled/disabled by specifying the ADIE bit in ADCSR. Either interrupt generation or DMAC activation when A/D conversion ends can be selected by the DMASL bit. Since data for only one channel can be DMA transferred for each interrupt, data for all specified channels can not be DMA transferred when more than one channel is specified in multi or scan mode.
29.6
Definitions of A/D Conversion Accuracy
The A/D converter compares an input for an analog channel to its analog reference voltage and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: 1. Offset error (figure 29.7 (1))
Deviation between analog input voltage and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) B'0000000000 (B'000 in figure 29.7) to B'0000000001 (B'001 in figure 29.7) 2. Full-scale error (figure 29.7 (2))
Deviation between analog input voltage and ideal A/D conversion characteristics when the digital output value changes from the B'1111111110 (B'110 in figure 29.7) to the maximum B'1111111111 (B'111 in figure 29.7). 3. Quantization error (figure 29.7 (3))
Intrinsic error of the A/D converter and is expressed as 1/2 LSB. 4. Nonlinearity error (figure 29.7 (4))
Deviation between analog input voltage and ideal A/D conversion characteristics between zero voltage and full-scale voltage. Note that it does not include offset, full-scale, and quantization errors.
Rev. 1.0, 02/03, page 1030 of 1294
Digital output Ideal A/D conversion characteristic Digital output (2) Full-scale error
111 110 101 100 011 010 001 000 0
Ideal A/D conversion characteristic
(4) Nonlinearity error (3) Quantization error
Actual A/D convertion characteristic 7/8 FS Analog input voltage FS Analog input voltage
1/8
2/8
3/8
4/8
5/8
6/8
(1) Offset error
FS: Full-scale voltage
Figure 29.7 Definitions of A/D Conversion Accuracy
29.7
Usage Notes
When using the A/D converter, note the points listed below. 29.7.1 Setting Analog Input Voltage
1. Analog input voltage range During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS_ADC ANn AVCC_ADC (n = 0 to 3). 2. AVCC_ADC and AVSS_ADC input voltages AVCC_ADC, AVSS_ADC, and VSS should be related as follows: AVCC_ADC = 3.3 V 0.3 V and AVSS_ADC = VSS. (AVCC_ADC = Analog power supply, AVSS_ADC = Analog ground, VSS = Internal digital power supply)
Rev. 1.0, 02/03, page 1031 of 1294
29.7.2
Processing of Analog Input Pins
To prevent damage from abnormal voltage such as voltage surges at the analog input pins (AN0 to AN3), connect a protection circuit like the one shown in figure 29.8. The circuit shown also includes a CR filter to suppress noise. This circuit is shown as an example; the circuit constants should be determined according to actual application conditions. Figure 29.9 shows an equivalent circuit diagram of the analog input pins.
100
*
AVCC_ADC AN0 to AN3 This LSI
Rin
0.1 F AVSS_ADC
Note: * Specify an appropriate Rin value according to the conditions of use and connected circuits. 10 F 0.01 F
Figure 29.8 Example of Analog Input Pin Protection Circuit
1.0 k AN0 to AN3
20 pF
1 M
Figure 29.9 Analog Input Pin Equivalent Circuit
Rev. 1.0, 02/03, page 1032 of 1294
29.7.3
Pck and Clock Division Ratio Settings
Four types of divided clocks can be used as the clock for A/D conversion. Since the internal circuit configuration affects the limits of the interface between the analog and digital sections, be sure to see table 29.5 when setting the input clock and clock division ratio. Table 29.5 Relationship between Clock Division Ratio and Usable Input Clock Frequency
Clock Division Ratio Pck/4 Pck/8 Pck/16 Pck/32 Input Clock 18 MHz or lower 34 MHz or lower 34 MHz or lower 34 MHz or lower
29.7.4
Notes on Standby Modes
Before entering hardware standby, module standby, or software standby modes, check that A/D conversion is not in progress, that is, the ADF bit is 1, or in multi mode or scan mode, clear the ADST bit to 0 to stop A/D conversion. Note that A/D conversion does not stop immediately. If module standby or software standby mode is entered without confirming that A/D conversion is stopped, correct AD converter operation is not guaranteed. In hardware standby, module standby, or software standby mode, all AD converter registers are initialized.
Rev. 1.0, 02/03, page 1033 of 1294
Rev. 1.0, 02/03, page 1034 of 1294
Section 30 LCD Controller (LCDC)
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data for display is stored in system memory. The LCDC module reads data from system memory, uses the palette memory to determine the colors, then puts the display on the LCD panel. It is possible to connect the LCDC to the LCD module of most types other than microcomputer bus interface types and NTSC/PAL types and those that apply the LVDS interface.
30.1
Features
The LCDC has the following features. * Panel interface Serial interface method Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width) * * Supports 4/8/15/16-bpp (bits per pixel) color modes * Supports 1/2/4/6-bpp grayscale modes * Supports LCD-panel sizes from 16 x 1 to 1024 x 1024*
2 1
* 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5) * STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker. * Dedicated display memory is unnecessary using part of the SDRAM connected to area 3 of the CPU as system memory. * The display is stable because of the large 2.4-kbyte line buffer * Supports the inversion of the output signal to suit the LCD panel's signal polarity * Supports the selection of data formats (the endian setting for bytes, backed pixel method) by register settings * A hardware-rotation mode is included to support the use of landscape-format LCD panels as portrait-format LCD panels (the horizontal width of the panel before rotation must be within 320 pixels--see table 30.4). Notes: 1. When connecting the LCDC to a TFT panel with an unwired 18-bit bus, the lower bit lines should be connected to GND or to the lowest bit from which data is output. 2. For details, see section 30.4.1, Size of LCD Modules Which Can Be Displayed with this LCDC.
Rev. 1.0, 02/03, page 1035 of 1294
Figure 30.1 shows a block diagram of LCDC.
LCD_CLK Bck Pck
Clock generator DOTCLK LCD_CL1 LCD_CL2 LCD_FLM LCD_DATA 15-0 LCD_DON VCPWC VEPWC LCD_M_DISP
Bus interface
Register LCDC Pallet RAM
4 bytes x 256 entries
Peripheral bus
Power control
DMABRG interface
Line buffer 2.4 kbytes
DMABRG
Figure 30.1 LCDC Block Diagram
30.2
Input/Output Pins
Table 30.1 summarizes the LCDC's pin configuration. Table 30.1 Pin Configuration
Name LCD_DATA15 to 0 LCD_DON LCD_CL1 LCD_CL2 LCD_M_DISP LCD_FLM VCPWC VEPWC LCD_CLK I/O Output Output Output Output Output Output Output Output Input Function Data for LCD panel Display-on signal (DON) Shift-clock 1 (STN/DSTN)/horizontal sync signal (HSYNC) (TFT) Shift-clock 2 (STN/DSTN)/dot clock (DOTCLK) (TFT) LCD current-alternating signal/DISP signal First line marker/vertical sync signal (VSYNC) (TFT) LCD-module power control (VCC) LCD-module power control (VEE) LCD clock-source input
Note: Check the LCD module specifications carefully in section 30.5, Clock and LCD Data Signal Examples, before deciding on the wiring specifications for the LCD module.
Rev. 1.0, 02/03, page 1036 of 1294
30.3
Register Configuration
The LCDC includes the following registers. For description on the address and processing status of these registers, refer to section 32, List of Registers. Table 30.2 Register Configuration (1)
Register Name LCDC input clock register LCDC module type register LCDC data format register LCDC scan mode register Abbrev. LDICKR LDMTR LDDFR LDSMR R/W R/W R/W R/W R/W R/W R/W R/W P4 Address H'FE30 0C00 H'FE30 0C02 H'FE30 0C04 H'FE30 0C06 H'FE30 0C08 H'FE30 0C0C H'FE30 0C10 H'FE30 0C12 H'FE30 0800 H'FE30 0C14 H'FE30 0C16 H'FE30 0C18 H'FE30 0C1A H'FE30 0C1C H'FE30 0C1E H'FE30 0C20 H'FE30 0C24 H'FE30 0C26 H'FE30 0C28 Area 7 Address Size H'1E30 0C00 H'1E30 0C02 H'1E30 0C04 H'1E30 0C06 H'1E30 0C08 H'1E30 0C0C H'1E30 0C10 H'1E30 0C12 H'1E30 0800 H'1E30 0C14 H'1E30 0C16 H'1E30 0C18 H'1E30 0C1A H'1E30 0C1C H'1E30 0C1E H'1E30 0C20 H'1E30 0C24 H'1E30 0C26 H'1E30 0C28 16 16 16 16 32 32 16 16 32 16 16 16 16 16 16 16 16 16 16 Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
LCDC display start address register - LDSARU upper LCDC display start address register - LDSARL lower LCDC display line address offset register LCDC palette control register Palette data registers 00 to FF LCDC horizontal character number register LCDC horizontal synchronization signal register LCDC vertical display line number register LCDC vertical total line number register LDLAOR
LDPALCR R/W LDPR00 to R/W FF*1 LDHCNR R/W
LDHSYNR R/W LDVDLNR R/W LDVTLNR R/W
LCDC vertical synchronization signal LDVSYNR R/W register LCDC AC modulation signal toggle line number register LCDC interrupt control register LCDC power management mode register LDACLNR R/W LDINTR LDPMMR R/W R/W R/W R/W
LCDC power supply sequence period LDPSPR register LCDC control register LDCNTR
Rev. 1.0, 02/03, page 1037 of 1294
Table 30.2 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ H-UDI H'0101 H'0109 H'000C H'0000 H'0C00 0000 H'0C00 0000 H'0280 Standby Manual Reset by by RESET Sleep Software/ by Sleep Pin/WDT/ Each Multiple Instruction/ by Deep Sleep Hardware Module Exception H'0101 H'0109 H'000C H'0000 H'0C00 0000 H'0C00 0000 H'0280 H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained * Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Register Name LCDC input clock register LCDC module type register LCDC data format register LCDC scan mode register LCDC display start address register upper LCDC display start address register lower LCDC display line address offset register LCDC palette control register Palette data registers 00 to FF LCDC horizontal character number register LCDC horizontal synchronization signal register LCDC vertical display line number register LCDC vertical total line number register LCDC vertical synchronization signal register
Abbrev. LDICKR LDMTR LDDFR LDSMR LDSARU LDSARL LDLAOR
LDPALCR H'0000
LDPR00 to Undefined Undefined FF*1 LDHCNR H'4F52 H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000
LDHSYNR H'0050 LDVDLNR H'01DF LDVTLNR H'01DF LDVSYNR H'01DF
LCDC AC modulation signal toggle line LDACLNR H'000C number register LCDC interrupt control register LCDC power management mode register LDINTR H'0000
LDPMMR H'0010 H'F60F H'0000
LCDC power supply sequence period LDPSPR register LCDC control register LDCNTR
Note:
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. *1. There are 256 registers: LDPR00, LDPR01, ......, LDPRFF. These registers are allocated to H'FE30 0800, H'FE30 0804, ......, H'FE30 0BFC. *
Rev. 1.0, 02/03, page 1038 of 1294
30.3.1
LCDC Input Clock Register (LDICKR)
This LCDC can select bus clock, the peripheral clock, or the external clock as its operation clock source. It is also possible to include a divider of 1/1 to 1/16 in the selected clock and use the division as the LCDC operating clock (DOTCLK). The clock output from the LCDC is used to generate the synchronous clock output (LCD_CL2) for the LCD panel from the operating clock selected in this register. The frequency of the output clock is LCD_CL2 = DOTCLK for a TFT panel, and LCD_CL2 = (DOTCLK/width of data bus output to LCD panel) for an STN or DSTN panel. The LDICKR must be set so that the clock input to the LCDC is 50 MHz or less regardless of the LCD_CL2.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13
ICK SEL1
12
ICK SEL0
11 0 R
10 0 R
9 0 R
8 1 R
7 0 R
6 0 R
5 0 R
4
3
2
1
0
DCDR4 DCDR3 DCDR2DCDR1DCDR0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
Bit 15, 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Input Clock Select Set the clock source for DOTCLK. 00: Bus clock is selected (Bck) 01: Peripheral clock is selected (Pck) 10: External clock is selected (LCD_CLK) 11: Setting prohibited
13 12
ICKSEL1 ICKSEL0
0 0
R/W R/W
11 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Reserved This bit is always read as 1. The write value should always be 1. Reserved These bits are always read as 0. The write value should always be 0. Clock Division Ratio Set the input clock division ratio. For details on the setting, refer to table 30.3.
8
1
R
7 to 5
All 0
R
4 3 2 1 0
DCDR4 DCDR3 DCDR2 DCDR1 DCDR0
0 0 0 0 1
R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 1039 of 1294
Table 30.3 I/O Clock Frequency and Clock Division Ratio
Clock Division Ratio 1/1 1/2 1/4 1/8 1/16 I/O Clock Frequency (MHz) 50.000 50.000 25.000 12.500 6.250 3.125 60.000 60.000 30.000 15.000 7.500 3.750 66.000 66.000 33.000 16.500 8.250 4.125
DCDR[4:0] 00001 00010 00100 01000 10000
Note: Any setting other than above is handled as a clock division ratio of 1/1 (initial value).
30.3.2
LCDC Module Type Register (LDMTR)
LDMTR sets the control signals output from this LCDC and the polarity of the data signals, according to the polarity of the signals for the LCD module connected to the LCDC.
Bit: 15
FLM POL
14
CL1 POL
13
DISP POL
12
DPOL
11 0 R
10
MCNT
9
CL1 CNT
8
CL2 CNT
7 0 R
6 0 R
5
MIF TYP5
4
MIF TYP4
3
MIF TYP3
2
MIF TYP2
1
MIF TYP1
0
MIF TYP0
Initial value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
Bit 15
Bit Name FLMPOL
Initial Value 0
R/W R/W
Description FLM (Vertical Sync Signal) Polarity Select Selects the polarity of the LCD_FLM (vertical sync signal, first line marker) for the LCD module. 0: LCD_FLM pulse is high active 1: LCD_FLM pulse is low active
14
CL1POL
0
R/W
CL1 (Horizontal Sync Signal) Polarity Select Selects the polarity of the LCD_CL1 (horizontal sync signal) for the LCD module. 0: LCD_CL1 pulse is high active 1: LCD_CL1 pulse is low active
13
DISPPOL
0
R/W
DISP (Display Enable) Polarity Select Selects the polarity of the LCD_M_DISP (display enable) for the LCD module. 0: LCD_M_DISP is high active 1: LCD_M_DISP is low active
Rev. 1.0, 02/03, page 1040 of 1294
Bit 12
Bit Name DPOL
Initial Value 0
R/W R/W
Description Display Data Polarity Select Selects the polarity of the LCD_DATA (display data) for the LCD module. This bit supports reflection of the LCD module. 0: LCD_DATA is high active, transparent-type LCD panel 1: LCD_DATA is low active, reflective-type LCD panel
11
0
R
Reserved This bit is always read as 0. The write value should always be 0. M Signal Control Sets whether or not to output the LCD's currentalternating signal of the LCD module. 0: M (AC line modulation) signal is output 1: M signal is not output
10
MCNT
0
R/W
9
CL1CNT
0
R/W
CL1 (Horizontal Sync Signal) Control Sets whether or not to enable LCD_CL1 output during the vertical retrace period. 0: LCD_CL1 is output during vertical retrace period 1: LCD_CL1 is not output during vertical retrace period
8
CL2CNT
1
R/W
LCD_CL2 (Dot Clock of LCD Module) Control Sets whether or not to enable CL2 output during the vertical retrace period. 0: LCD_CL2 is output during vertical retrace period 1: LCD_CL2 is not output during vertical retrace period
7, 6
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 1041 of 1294
Bit 5 4 3 2 1 0
Bit Name MIFTYP5 MIFTYP4 MIFTYP3 MIFTYP2 MIFTYP1 MIFTYP0
Initial Value 0 0 1 0 0 1
R/W R/W R/W R/W R/W R/W R/W
Description Module Interface Type Select Set the LCD panel type and data bus width to be output to the LCD panel. There are three LCD panel types: STN, DSTN, and TFT. There are four data bus widths for output to the LCD panel: 4, 8, 12, and 16 bits. When the required data bus width for a TFT panel is 16 bits or more, connect the LCDC and LCD panel according to the data bus size of the LCD panel. Unlike in a TFT panel, in an STN or DSTN panel, the data bus width setting does not have a 1:1 correspondence with the number of display colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus can be used for 4 bpp. This is because the number of display colors in an STN or DSTN panel is determined by how data is placed on the bus, and not by the number of bits. For data specifications for an STN or DSTN panel, see the specifications of the LCD panel used. The output data bus width should be set according to the mechanical interface specifications of the LCD panel. If an STN or DSTN panel is selected, display control is performed using a 24-bit space-modulation FRC consisting of the 8-bit R, G, and B included in the LCDC, regardless of the color and gradation settings. Accordingly, the color and gradation specified by DSPCOLOR is selected from 16 million colors in an STN or DSTN panel. If a palette is used, the color specified in the palette is displayed. 000000: STN monochrome 4-bit data bus module 000001: STN monochrome 8-bit data bus module 001000: STN color 4-bit data bus module 001001: STN color 8-bit data bus module 001010: STN color 12-bit data bus module 001011: STN color 16-bit data bus module 010001: DSTN monochrome 8-bit data bus module 010011: DSTN monochrome 16-bit data bus module 011001: DSTN color 8-bit data bus module 011010: DSTN color 12-bit data bus module 011011: DSTN color 16-bit data bus module 101011: TFT color 16-bit data bus module Settings other than above: Setting prohibited
Rev. 1.0, 02/03, page 1042 of 1294
30.3.3
LCDC Data Format Register (LDDFR)
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of colors used for display so as to match the display driver software specifications.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8
PABD
7 0 R
6
5
4
3
2
1
0
DSP DSP DSP DSP DSP DSP DSP COLOR6 COLOR5 COLOR4 COLOR3 COLOR2 COLOR1 COLOR0
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Byte Data Pixel Alignment Sets the pixel data alignment type in one byte of data. The contents of aligned data per pixel are the same regardless of this bit's setting. For example, data H'05 should be expressed as B'0101 which is the normal style handled by a MOV instruction of the this CPU, and should not be selected between B'0101 and B'1010. 0: Big endian for byte data 1: Little endian for byte data
15 to 9
8
PABD
0
R/W
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 1043 of 1294
Bit 6 5 4 3 2 1 0
Bit Name DSPCOLOR6 DSPCOLOR5 DSPCOLOR4 DSPCOLOR3 DSPCOLOR2 DSPCOLOR1 DSPCOLOR0
Initial Value R/W 0 0 0 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W
Description Display Color Select Set the number of display colors for the display (0 is written to upper bits of 4 to 6 bpp). For display colors to which the description (via palette) is added below, the color set by the color palette is actually selected by the display data and displayed. The number of colors that can be selected in rotation mode is restricted by the display resolution. For details, see table 30.4, Display Resolutions when Using Display Rotation. 0000000: Monochrome, 2 grayscales, 1 bpp (via palette) 0000001: Monochrome, 4 grayscales, 2 bpp (via palette) 0000010: Monochrome, 16 grayscales, 4 bpp (via palette) 0000100: Monochrome, 64 grayscales, 6 bpp (via palette) 0001010: Color, 16 colors, 4 bpp (via palette) 0001100: Color, 256 colors, 8 bpp (via palette) 0011101: Color, 32k colors (RGB: 555), 15 bpp 0101101: Color, 64k colors (RGB: 565), 16 bpp Settings other than above: Setting prohibited
Rev. 1.0, 02/03, page 1044 of 1294
30.3.4
LCDC Scan Mode Register (LDSMR)
LDSMR specifies whether or not to enable the hardware rotation function that is used to rotate the LCD panel. The system memory allocated for display (SDRAM in area 3) is always accessed in units of 32 bytes.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 ROT 0 R/W 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Bit 15, 14
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
13
ROT
0
R/W
Rotation Module Select Selects whether or not to rotate the display by hardware. Note that the following restrictions are applied to rotation. * * * An STN or TFT panel must be used. A DSTN panel is not allowed. The maximum horizontal (internal scan direction of the LCD panel) width of the LCD panel is 320. Set a binary exponential that exceeds the display size in LDLAOR. (For example, 256 must be selected when a 320 x 240 panel is rotated to be used as a 240 x 320 panel and the horizontal width of the image is 240 bytes.)
0: Not rotated 1: Rotated 90 degrees rightwards (left side of image is displayed on the upper side of the LCD module) 12 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0.
Rev. 1.0, 02/03, page 1045 of 1294
30.3.5
LCDC Display Start Address Register - Upper (LDSARU)
LDSARU sets the start address from which data is fetched by the LCDC for display of the LCDC panel. When a DSTN panel is used, this register specifies the fetch start address for the upper side of the panel.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 30 0 R 14 29 0 R 13 28 0 R 12 27 1 R 11 26 1 R 10 25 24 23 22 21 20 19 18 17 16
SAU25 SAU24 SAU23 SAU22 SAU21 SAU20 SAU19 SAU18 SAU17 SAU16
0 R/W 9
0 R/W 8
0 R/W 7
0 R/W 6
0 R/W 5
0 R/W 4
0 R/W 3
0 R/W 2
0 R/W 1
0 R/W 0
SAU15 SAU14 SAU13 SAU12 SAU11 SAU10 SAU9 SAU8 SAU7 SAU6 SAU5
SAU4 SAU3 SAU2 SAU1 SAU0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27, 26
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
25 to 0
SAU25 to SAU0
All 0
R/W
Start Address for Upper Display Panel Data Fetch The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3.
Notes: 1.
2.
The minimum alignment unit of LDSARU is 512 bytes when the hardware rotation function is not used. Write 0 to the lower nine bits. When using the hardware rotation function, set the LDSARU value so that the upper-left address of the image is aligned with the 512-byte boundary. When the hardware rotation function is used (ROT = 1), set the lower-left address of the image which can be calculated from the display image size in this register. The equation below shows how to calculate the LDSARU value when the image size is 240 x 340 and LDLAOR = 256. The LDSARU value is obtained not from the panel size but from the memory size of the image to be displayed. Note that LDLAOR must be a binary exponential at least as large as the horizontal width of the image. For the upper left address, calculating backwards using the LDSARU value results in LDSARU - 256 (LDLAOR value) x (320 - 1), so make sure it is set within the 512-byte boundary. LDSARU = (upper-left address of image) + 256 (LDLAOR value) x 319 (line)
Rev. 1.0, 02/03, page 1046 of 1294
3.
The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC handles these values as longword data, the values written to the lower two bits of each register are always treated as 0. The lower two bits of each register are always read as 0. For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15, or 16 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits).
30.3.6
LCDC Display Start Address Register - Lower (LDSARL)
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the panel.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 0 R 15 30 0 R 14 29 0 R 13 28 0 R 12 27 1 R 11 26 1 R 10 25 24 23 22 21 20 19 18 17 16
SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
0 R/W 9
0 R/W 8
SAL8
0 R/W 7
SAL7
0 R/W 6
SAL6
0 R/W 5
SAL5
0 R/W 4
SAL4
0 R/W 3
SAL3
0 R/W 2
SAL2
0 R/W 1
SAL1
0 R/W 0
SAL0
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
31 to 28
27, 26
All 1
R
Reserved These bits are always read as 1. The write value should always be 1.
25 to 0
SAL25 to SAL0
All 0
R/W
Start Address for Lower Panel Display Data Fetch The start address for data fetch of the display data must be set within the synchronous DRAM area of area 3. STN and TFT: Cannot be used DSTN: Start address for fetching display data corresponding to the lower panel
Rev. 1.0, 02/03, page 1047 of 1294
Note: 1. The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC handles these values as longword data, the values written to the lower two bits of each register are always treated as 0. The lower two bits of each register are always read as 0. For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15, or 16 bpp, set the registers so that the start of each line is aligned with the longword boundary (32 bits).
30.3.7
LCDC Display Line Address Offset Register (LDLAOR)
LDLAOR specifies the Y-coordinate increment address width used by the LCDC to read an image recognized by the graphics driver. When the Y-coordinate is increased by 1, this register specifies by how many bytes the address for reading data from memory should be moved, and it needs not conform to the width of the LCD panel. This register corresponds to B when the equation Ax + By + C is used to calculate the memory address of a point (X, Y) in a two dimensional image.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6
LAO6
5
LAO5
4
LAO4
3
LAO3
2
LAO2
1
LAO1
0
LAO0
LAO15 LAO14 LAO13 LAO12 LAO11 LAO10 LAO9
LAO8 LAO7
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit
Bit Name Initial Value
R/W R/W R/W R/W R/W R/W
Description Line Address Offset The minimum alignment unit of LDLAOR is four bytes. Because the LCDC handles these values as longword data, the values written to the lower two bits of the register are always treated as 0. When reading from the register, the lower two bits are always read as 0. In order for VGA (640 x 480 dot) display data to be read continuously without skipping an address between lines, the initial value is set to (x resolution = 640). For details, see table 30.4, Display Resolutions when Using Display Rotation, in section 30.4, Operation. A binary exponential at least as large as the horizontal width of the image is recommended for the LDLAOR value, taking into consideration the software operation speed. When the hardware rotation function is used, the LDLAOR value should not correspond to the width of the LCD panel (320 in a 320 x 240 panel), but should be a binary exponential (in this example, 256) at least as large as the horizontal width of the image (after rotation, 240 in a 240 x 320 panel).
15 to 10 LAO15 to All 0 LAO10 9 8 7 6 to 0 LAO9 LAO8 LAO7 LAO6 to LAO0 1 0 1 All 0
Rev. 1.0, 02/03, page 1048 of 1294
30.3.8
LCDC Palette Control Register (LDPALCR)
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette memory is being used for display operation, display mode should be selected. When the palette memory is being written to, color-palette setting mode should be selected.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4
PALS
3 0 R
2 0 R
1 0 R
0
PALEN
0 R
0 R/W
Bit 15 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits always read as 0. The write value should always be 0.
4
PALS
0
R
Palette State Indicates the access right state of the palette. 0: Display mode: LCDC uses the palette 1: Color-palette setting mode: The host (CPU) uses the palette
3 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
PALEN
0
R/W
Palette Read/Write Enable Requests the access right to the palette. 0: Request for transition to normal display mode 1: Request for transition to color palette setting mode
Rev. 1.0, 02/03, page 1049 of 1294
30.3.9
Palette Data Registers 00 to FF (LDPR00 to LDPRFF)
LDPR registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the memory space. To access the palette memory, access the corresponding register among this register group (LDPR00 to LDPRFF). Each palette register is a 32-bit register including three 8-bit areas for R, G, and B. For details on the color palette specifications, see section 30.4.3, Color Palette Specification.
Bit: 31 Initial value: R/W: Bit: R 30 R 29 R 28 R 27 R 26 R 25 R 24 R 23 22 21 20 19 18 17 16 PALD PALD PALD PALD PALD PALD PALD PALD nn_23 nn_22 nn_21 nn_20 nn_19 nn_18 nn_17 nn_16 R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD PALD nn_15 nn_14 nn_13 nn_12 nn_11 nn_10 nn_9 nn_8 nn_7 nn_6 nn_5 nn_4 nn_3 nn_2 nn_1 nn_0 Initial value: R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value R/W R R/W
Description Reserved Palette Data Bits 18 to 16, 9, 8, and 2 to 0 are reserved within each RGB palette and cannot be set. However, these bits can be used by extension, according to the value of the upper bits.
31 to 24 23 to 0
PALDnn_23 to PALDnn_0
Note: nn = H'00 to H'FF
Rev. 1.0, 02/03, page 1050 of 1294
30.3.10 LCDC Horizontal Character Number Register (LDHCNR) LDHCNR specifies the LCD module's horizontal size (in the scan direction) and the width of the entire scan, including that of the horizontal retrace period.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDCN7 HDCN6 HDCN5 HDCN4 HDCN3 HDCN2 HDCN1 HDCN0 HTCN7 HTCN6 HTCN5 HTCN4 HTCN3 HTCN2 HTCN1 HTCN0
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
0 R/W
1 R/W
0 R/W
0 R/W
1 R/W
0 R/W
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Initial Value R/W HDCN7 HDCN6 HDCN5 HDCN4 HDCN3 HDCN2 HDCN1 HDCN0 HTCN7 HTCN6 HTCN5 HTCN4 HTCN3 HTCN2 HTCN1 HTCN0 0 1 0 0 1 1 1 1 0 1 0 1 0 0 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Horizontal Display Character Number Sets the number of horizontal display characters (unit: character = 8 dots). Specify a value of (number of display characters) -1. Example: For a LCD module with a width of 640 pixels. HDCN = (640/8) -1 = 79 = H'4F Horizontal Total Character Number Sets the number of total horizontal characters (unit: character = 8 dots). Specify a value of (total number of characters) -1. However, the minimum value for the horizontal retrace period is three characters (24 dots). Example: For a LCD module with a width of 640 pixels. HTCN = [(640/8) -1] +3 = 82 = H'52 In this case, the number of total horizontal dots is 664 dots and the number for the horizontal retrace period is 24 dots.
Note: The values set in HDCN and HTCN must satisfy the relationship of HTCN HDCN. Also, the total number of characters of HTCN must be an even number. (The set value will be an odd number, as it is one less than the actual number.)
30.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals for the LCD module.
Rev. 1.0, 02/03, page 1051 of 1294
Bit:
Initial value: R/W:
15 VSY NW3 0 R/W
14 VSY NW2 0 R/W
13 VSY NW1 0 R/W
12 VSY NW0 0 R/W
11 0 R
10 9 VSY VSY NP10 NP9 0 0 R/W R/W
8 VSY NP8 1 R/W
7 VSY NP7 1 R/W
6 VSY NP6 1 R/W
5 VSY NP5 0 R/W
4 VSY NP4 1 R/W
3 VSY NP3 1 R/W
2 VSY NP2 1 R/W
1 VSY NP1 1 R/W
0 VSY NP0 1 R/W
Bit 15 14 13 12
Bit Name HSYNW3 HSYNW2 HSYNW1 HSYNW0
Initial Value R/W 0 0 0 0 R/W R/W R/W R/W
Description Horizontal Sync Signal Width Sets the width of the horizontal sync signals (CL1 and Hsync) (unit: character = 8 dots). Specify a value of (width of horizontal sync signal) -1. Example: For a horizontal sync signal width of 8 dots. HSYNW = (8 dots/8 dots/character) -1 = 0 = H'0
11 to 8
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
7 6 5 4 3 2 1 0
HSYNP7 HSYNP6 HSYNP5 HSYNP4 HSYNP3 HSYNP2 HSYNP1 HSYNP0
0 1 0 1 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Horizontal Sync Signal Output Position Sets the output position of the horizontal sync signals (unit: character = 8 dots). Specify a value of (position of horizontal sync signal output) -1. Example: For a LCD module with a width of 640 pixels. HSYNP = [(640/8)+1] -1 = 80 = H'50 In this case, the horizontal sync signal is active from the 648th through the 655th dot.
Note: The following conditions must be satisfied: HTCN HSYNP+HSYNW+1 HSYNP HDCN+1
Rev. 1.0, 02/03, page 1052 of 1294
30.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) LDVDLNR specifies the LCD module's vertical size (for both scan direction and vertical direction). For a DSTN panel, specify an even number at least as large as the LCD panel's vertical size regardless of the size of the upper and lower panels, e.g. 480 for a 640 x 480 panel.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 9 8 7 6 5 4 3 2 1 0 VDLN VDLN VDLN VDLN VDLN VDLN VDLN VDLN VDLN VDLN VDLN 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 11
10 9 8 7 6 5 4 3 2 1 0
VDLN10 VDLN9 VDLN8 VDLN7 VDLN6 VDLN5 VDLN4 VDLN3 VDLN2 VDLN1 VDLN0
0 0 1 1 1 0 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Vertical Display Line Number Sets the number of vertical display lines (unit: line). Specify a value of (number of display lines) -1. Example: For an 480-line LCD module VDLN = 480-1 = 479 = H'1DF
Rev. 1.0, 02/03, page 1053 of 1294
30.3.13 LCDC Vertical Total Line Number Register (LDVTLNR) LDVTLNR specifies the LCD panel module's entire vertical length, including that of the vertical retrace period.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 9 8 7 6 5 4 3 2 1 0 VTLN VTLN VTLN VTLN VTLN VTLN VTLN VTLN VTLN VTLN VTLN 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 11
10 9 8 7 6 5 4 3 2 1 0
VTLN10 VTLN9 VTLN8 VTLN7 VTLN6 VTLN5 VTLN4 VTLN3 VTLN2 VTLN1 VTLN0
0 0 1 1 1 0 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Vertical Total Line Number Sets the total number of vertical display lines (unit: line). Specify a value of (total number of lines) -1. The minimum for the total number of vertical lines is 2 lines. The following conditions must be satisfied: VTLN>=VDLN, VTLN>=1. Example: For a 480-line LCD module and a vertical retrace period of 0 lines. VTLN = (480+0) -1 = 479 = H'1DF
Rev. 1.0, 02/03, page 1054 of 1294
30.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the LCD module.
Bit: 15 VSY NW3 0 R/W 14 VSY NW2 0 R/W 13 VSY NW1 0 R/W 12 VSY NW0 0 R/W 11 0 R 10 9 VSY VSY NP10 NP9 0 0 R/W R/W 8 VSY NP8 1 R/W 7 VSY NP7 1 R/W 6 VSY NP6 1 R/W 5 VSY NP5 0 R/W 4 VSY NP4 1 R/W 3 VSY NP3 1 R/W 2 VSY NP2 1 R/W 1 VSY NP1 1 R/W 0 VSY NP0 1 R/W
Initial value: R/W:
Bit 15 14 13 12
Bit Name VSYNW3 VSYNW2 VSYNW1 VSYNW0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Vertical Sync Signal Width Sets the width of the vertical sync signals (FLM and Vsync) (unit: line). Specify a value of (width of vertical sync signal) -1. Example: For a vertical sync signal width of 1 line. VSYNW = (1-1) = 0 = H'0
11
0
R
Reserved This bit is always read as 0. The write value should always be 0.
10 9 8 7 6 5 4 3 2 1 0
VSYNP10 VSYNP9 VSYNP8 VSYNP7 VSYNP6 VSYNP5 VSYNP4 VSYNP3 VSYNP2 VSYNP1 VSYNP0
0 0 1 1 1 0 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Vertical Sync Signal Output Position Sets the output position of the vertical sync signals (FLM and Vsync) (unit: line). Specify a value of (position of vertical sync signal output) -2. DSTN should be set to an odd number value. It is handled as (setting value+1)/2. Example: For a 480-line LCD module and a retrace period of 0 lines (in other words, VTLN= 479 and the vertical sync signal is active for the first line): * Single display VSYNP = [(1-1)+VTLN]mod(VTLN+1) = [(1-1)+479]mod(479+1) = 479mod480 = 479 =H'1DF Dual address VSYNP = [(1-1)x2+VTLN]mod(VTLN+1) = [(1-1)x2+479]mod(479+1) = 479mod480 = 479 =H'1DF
*
Rev. 1.0, 02/03, page 1055 of 1294
30.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) LDACLNR specifies the timing to toggle the AC modulation signal (LCD current-alternating signal) of the LCD module.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 3 2 1 0
ACLN4 ACLN3 ACLN2 ACLN1 ACLN0
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
Bit 15 to 5
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
4 3 2 1 0
ACLN4 ACLN3 ACLN2 ACLN1 ACLN0
0 1 1 0 0
R/W R/W R/W R/W R/W
AC Line Number Sets the number of lines where the LCD currentalternating signal of the LCD module is toggled (unit: line). Specify a value of (number of toggled lines) -1. Example: For toggling every 13 lines. ACLN = 13-1 = 12= H'0C
Note: When the total line number of the LCD panel is even, set an even number so that toggling is performed at an odd line.
30.3.16 LCDC Interrupt Control Register (LDINTR) LDINTR regulates the LCD module's Vsync interrupt (LCDCI) activity.
Bit: 15 Initial value: R/W: 0 R 14 0 R 13 0 R 12 VINT SEL 0 R/W 11 0 R 10 0 R 9 0 R 8 VINTE 0 R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 VINTS 0 R/W
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 13
Rev. 1.0, 02/03, page 1056 of 1294
Bit 12
Bit Name VINTSEL
Initial Value 0
R/W R/W
Description Vsync Interrupt Select Sets the starting point of the LCDC's Vsync interrupt. 0: Vsync interrupt occurs at the beginning of access to synchronous DRAM 1: Vsync interrupt occurs at the beginning of the LCD display vertical retrace period
11 to 9
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
8
VINTE
0
R/W
Vsync Interrupt Enable Sets whether or not to generate LCDC's Vsync interrupts. 0: Vsync interrupts are disabled 1: Vsync interrupts are enabled
7 to 1
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
0
VINTS
0
R/W
Vsync Interrupt State Indicates the LCDC's Vsync interrupt handling state. This bit is set to 1 at the time a Vsync interrupt is generated. During the processing routine for Vsync interrupt, clear the register by entering a value of 0. 0: LCDC did not generate a Vsync interrupt or has been informed that the generated Vsync interrupt has completed 1: LCDC has generated a Vsync interrupt and has not yet been informed that the generated Vsync interrupt has completed When Vsync interrupts are enabled, the VINTE bit must be set to 1 before the DON bit is set to 1, and the VINTE bit must not be cleared to 0. When the VINTE bit is set to 0, Vsync interrupts are not generated.
Rev. 1.0, 02/03, page 1057 of 1294
30.3.17 LCDC Power Management Mode Register (LDPMMR) LDPMMR controls the power supply circuit that provides power to the LCD module. The usage of two types of power-supply control pins, VCPWC and VEPWC, and turning on or off the power supply function are selected.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 0 R 6 5 4 3 0 R 2 0 R 1 0
ONC3 ONC2 ONC1
ONC0 OFFD3 OFFD2 OFFD1 OFFD0
VCPE VEPE DONE 0 R/W 0 R/W 1 R/W
LPS1 LPS0 0 R 0 R
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Bit 15 14 13 12
Bit Name ONC3 ONC2 ONC1 ONC0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description LCDC Power-On Sequence Period Sets the period from VEPWC assertion to LCD_DON assertion in the power-on sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (c) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module. For details on setting this register, see table 30.5, Available Power-Supply ControlSequence Periods at Typical Frame Rates. (The setting method is common for ONA, ONB, OFFD, OFFE, and OFFF.)
11 10 9 8
OFFD3 OFFD2 OFFD1 OFFD0
0 0 0 0
R/W R/W R/W R/W
LCDC Power-Off Sequence Period Sets the period from LCD_DON negation to VEPWC negation in the power-off sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (d) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module.
7
0
R
Reserved This bit is always read as 0. The write value should always be 0.
6
VCPE
0
R/W
VCPWC Pin Enable Sets whether or not to enable a power-supply control sequence using the VCPWC pin. 0: Disabled: VCPWC pin output is masked and fixed low 1: Enabled: VCPWC pin output is asserted and negated according to the power-on or power-off sequence
Rev. 1.0, 02/03, page 1058 of 1294
Bit 5
Bit Name VEPE
Initial Value 0
R/W R/W
Description VEPWC Pin Enable Sets whether or not to enable a power-supply control sequence using the VEPWC pin. 0: Disabled: VEPWC pin output is masked and fixed low 1: Enabled: VEPWC pin output is asserted and negated according to the power-on or poweroff sequence
4
DONE
1
R/W
LCD_DON Pin Enable Sets whether or not to enable a power-supply control sequence using the LCD_DON pin. 0: Disabled: VEPWC pin output is masked and fixed low 1: Enabled: LCD_DON pin output is asserted and negated according to the power-on or power-off sequence
3, 2
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
1 0
LPS1 LPS0
0 0
R R
LCD Module Power-Supply Input State Indicates the power-supply input state of the LCD module when using the power-supply control function. 0: LCD module power off 1: LCD module power on
Rev. 1.0, 02/03, page 1059 of 1294
30.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) LDPSPR controls the power supply circuit that provides power to the LCD module. It sets the timing for beginning output to the VEPWC and VCPWC pins and for the timing signals which accompany them.
Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONA3 ONA2 ONA1
ONA0 ONB3 ONB2
ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
1 R/W
1 R/W
1 R/W
1 R/W
0 R/W
1 R/W
1 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Bit 15 14 13 12
Bit Name ONA3 ONA2 ONA1 ONA0
Initial Value 1 1 1 1
R/W R/W R/W R/W R/W
Description LCDC Power-On Sequence Period Sets the period from VCPWC assertion to starting output of the display data (LCD_DATA) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) in the power-on sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (a) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module.
11 10 9 8
ONB3 ONB2 ONB1 ONB0
0 1 1 0
R/W R/W R/W R/W
LCDC Power-On Sequence Period Sets the period from starting output of the display data (LCD_DATA) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) to the VEPWC assertion in the power-on sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (b) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module.
Rev. 1.0, 02/03, page 1060 of 1294
Bit 7 6 5 4
Bit Name OFFE3 OFFE2 OFFE1 OFFE0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description LCDC Power-Off Sequence Period Sets the period from VEPWC negation to stopping output of the display data (LCD_DATA) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) in the power-off sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (e) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module.
3 2 1 0
OFFF3 OFFF2 OFFF1 OFFF0
1 1 1 1
R/W R/W R/W R/W
LCDC Power-Off Sequence Period Sets the period from stopping output of the display data (LCD_DATA) and timing signals (LCD_FLM, LCD_CL1, LCD_CL2, and LCD_M_DISP) to VCPWC negation in the power-off sequence of the LCD module in frame units. Specify a value of (the period) -1. This period is the (f) period in figures 30.4 to 30.7, Power-Supply Control Sequence and States of the LCD Module.
30.3.19 LCDC Control Register (LDCNTR) LDCNTR specifies start and stop of display by the LCDC. The LCDC begins display when a value of 1 is input to both the DON2 bit and the DON bit. Power is then supplied to the LCD module in accordance with the sequence set by the LDPMM and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'00 to B'11. Do not make any action to the DON bit until the sequence ends. The LCDC stops display when a value of 0 is input to the DON bit. Power to the LCD module is cut off in accordance with the sequence set by the LDPMMR and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'11 to B'00. Do not make any action to the DON bit until the sequence ends.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 DON2 0 R/W 3 0 R 2 0 R 1 0 R 0 DON 0 R/W
Rev. 1.0, 02/03, page 1061 of 1294
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
15 to 5
4
DON2
0
R/W
Display On 2 Specifies the start of the LCDC display operation. 0: LCDC is being operated or stopped 1: LCDC starts operation This bit is always read as 0. Input 1 only when starting display. If 1 is input at any time other than when starting display, it is not certain to function. The 1 that is input automatically reverts to 0, so it is unnecessary to clear it by inputting 0.
3 to 1
All 0
R
Reserved. These bits are always read as 0. The write value should always be 0.
0
DON
0
R/W
Display On Specifies the start and stop of the LCDC display operation. The control sequence state can be checked by referencing the LPS[1:0] of LDPMMR. 0: Display-off mode: LCDC is stopped 1: Display-on mode: LCDC operates
Note:
1. Write H'0011 to LDCNTR when starting display and H'0000 when completing display. Data other than H'0011 and H'0000 must not be written to. 2. Setting bit DON2 to 1 makes the contents of the palette RAM undefined. Before writing to the palette RAM, set bit DON2 to 1.
Rev. 1.0, 02/03, page 1062 of 1294
30.4
30.4.1
Operation
Size of LCD Modules Which Can Be Displayed with this LCDC
This LCDC is capable of controlling displays with up to 1024 x 1024 dots and 16 bpp (bits per pixel). The image data for display is stored in system memory, which is shared with the CPU. This LCDC should read the data from system memory before display. This LSI has a maximum 32-byte burst memory read operation and a 2.4-kbyte line buffer, so display failure is unlikely. However, there may be some display problems with certain configurations. A recommended size at the frame rate of 60 Hz is 320 x 240 dots in 16 bpp or 640 x 480 dots in 8-bpp. Figure 30.2 shows the valid display and the retrace period.
Hsync Signal H total Time
Right Border Hsync Time Front Porch Back Porch Left Border Vsync Signal
H AddressableVideo
Vsync Time Back Porch Top Border V Addressable Video Bottom Border Front Porch Active Video =Top/Left Border + Addressable Video + Bottom/Right Border Total H Blank = Hsync Time + Back Porch + Front Porch Total V Blank = Vsync Time + Back Porch + Front Porch HTCN = H Total Time HDCN = H Addressable Video HSYNP = H Addressable Video + Right Border + Front Porch HSYNW = Hsync Time VTLN = V Total Time CDLN = V Addressable Video VSYNP = V Addressable Video + Bottom Border + Front porch VSYNW = Vsync Time
V Total Time
Figure 30.2 Valid Display and the Retrace Period
Rev. 1.0, 02/03, page 1063 of 1294
30.4.2
Limits on the Resolution of Rotated Displays
Table 30.4 Display Resolutions when Using Display Rotation
Image for Display in Memory (X-Resolution x Y-Resolution) 240 x 320 LCD Module (X-Resolution x Y-Resolution) 320 x 240 Number of Colors for Display Monochrome 4 bpp 6 bpp Color 8 bpp 16 bpp 234 x 320 320 x 234 Monochrome Color 80 x 160 160 x 80 Monochrome 6 bpp 16 bpp 2 bpp 4 bpp 6 bpp Color 4 bpp 8 bpp 16 bpp 64 x 128 128 x 64 Monochrome 1 bpp 2 bpp 4 bpp 6 bpp Color 4 bpp 8 bpp
This LCDC is capable of displaying a landscape-format image on a LCD module by rotating a portrait format image for display by 90 degrees. For each resolution, only the number of colors indicated in the table is supported. A monochromatic LCD module is necessary for the display of images in the above monochromatic formats. A color LCD module is necessary for the display of images in the above color formats. 30.4.3 Color Palette Specification
(1) Color Palette Register: This LCDC has a color palette which outputs 24 bits of data per entry and is able to simultaneously hold 256 entries. The color palette thus allows the simultaneous display of 256 colors chosen from among 16-M colors.
Rev. 1.0, 02/03, page 1064 of 1294
It is also possible for the user to set the color palette when necessary, according to the procedure below. 1. The PALEN bit in the LDPALCR is 0 (initial value); normal display operation 2. Access LDPALCR and set the PALEN bit to 1; enter color-palette setting mode after three cycles of peripheral clock. 3. Access LDPALCR and confirm that the PALS bit is 1. 4. Access LDPR00 to LDPRFF and write the required values to the PALD00 to PALDFF bits. 5. Access LDPALCR and clear the PALEN bit to 0; return to normal display mode after a cycle of peripheral clock. While the PALS bit in LPDALCR is set to 1, the display data for the LCDC (LCD_DATA) will output a value of 0.
31 23 15 7 0
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Monochrome
M7 M6 M5 M4 M3 M2 M1 M0
Figure 30.3 Color-Palette Data Format PALDnn color and gradation data should be set as above. For a color display, PALDnn [23:16], PALDnn [15:8], and PALDnn [7:0] respectively hold the R, G, and B data. However, although there are register bits at PALDnn [18:16], PALDnn [9:8], and PALDnn [2:0], there is no corresponding memory for them. PALDnn [18:16], PALDnn [9:8], and PALDnn [2:0] are thus not available for storing palette data. The numbers of valid bits are thus R: 5, G: 6, and B: 5. However, 24-bit (R: 8 bits, G: 8 bits, and B: 8 bits) data should be written to the palette-data registers. When the values for PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3] are not 0, 1 or 0 should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0], respectively. When the values of PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3] are 0, 0 should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0], respectively. Data is thus extended to 24 bits.
Grayscale data for a monochromatic display should be set in PALDnn [7:3]. PALDnn [23:8] are all "don't care". When the value in PALDnn [7:3] is not 0, 1s should be written to PALDnn [2:0]. When the value in PALDnn [7:3] is 0, 0s should be written to PALDnn [2:0]. Data is thus extended to 8 bits.
Rev. 1.0, 02/03, page 1065 of 1294
30.4.4
Data Format
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] MSB LSB Top Left Pixel Address 76 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 ... +00 P00 P01 P02 P03 P04 P05 P06 P07 (Byte0) P10 P11 P12 P13 P14 P15 P16 P17 ... ... (Byte1) +01 P08 ... +02 +03 Display ... ... Pn: Put 1bit data +LAO+00 P10 P11 P12 P13 P14 P15 P16 P17 +LAO+01 P18 ... +LAO+02 LAO: Line Address Offset +LAO+03 ... --Unused bits should be 0 Display Memory 2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] MSB LSB Top Left Pixel Address 76 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 +00 P00 P01 P02 P03 (Byte0) P10 P11 P12 P13 P14 P15 P16 P17 ... +01 P04 P05 P06 P07 (Byte1) ... +02 +03 Display ... ... P10 P11 P12 P13 Pn=Pn[1:0]: Put 2bit data +LAO+00 P14 P15 P16 P17 +LAO+01 ... +LAO+02 +LAO+03 ... Display Memory LAO: Line Address Offset --Unused bits should be 0
... ...
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format] Top Left Pixel MSB LSB Address 76 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 ... (Byte0) +00 P00 P01 P10 P11 P12 P13 P14 P15 P16 P17 ... ... (Byte1) +01 P02 P03 ... (Byte2) +02 P04 P05 +03 Display ... ... Pn=Pn[3:0]: Put 4bit data P00 P01 +LAO+00 P02 P03 +LAO+01 P04 P05 +LAO+02 ... LAO: Line Address Offset +LAO+03 ... --Unused bits should be 0 Display Memory 4. Packed 1bpp (Pixel Alignment in Byte is Little Endian) MSB LSB Address 76 5 4 3 2 1 0 [Bit] +00 P07 P06 P05 P04 P03 P02 P01 P00 (Byte0) +01 P08 (Byte1) +02 +03 ... ... +LAO+00 P17 P16 P15 P14 P13 P12 P11 P10 P18 +LAO+01 ... +LAO+02 +LAO+03 ... Display Memory Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn: Put 1bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
Rev. 1.0, 02/03, page 1066 of 1294
5. Packed 2bpp (Pixel Alignment in Byte is Little Endian) MSB LSB Address 7 654321 0 [Bit] +00 P03 P02 P01 P00 (Byte0) +01 P07 P06 P05 P04 (Byte1) +02 +03 ... ... P13 P12 P11 P10 +LAO+00 P17 P16 P15 P14 +LAO+01 ... +LAO+02 +LAO+03 ... Display Memory 6. Packed 4bpp (Pixel Alignment in Byte is Little Endian) MSB LSB Address 7 654321 0 [Bit] (Byte0) +00 P01 P00 (Byte1) +01 P04 P03 (Byte2) +02 P06 P05 +03 ... ... P11 P10 +LAO+00 P13 P12 +LAO+01 P15 P14 +LAO+02 ... +LAO+03 ... Display Memory 7. Unpacked 4bpp [Windows CE Recommended Format] MSB LSB Address 7 654321 0 [Bit] (Byte0) +00 P00 (Byte1) +01 P01 (Byte2) +02 P02 +03 ... ... P10 +LAO+00 P11 +LAO+01 P12 +LAO+02 ... +LAO+03 ... Display Memory 8. Unpacked 5bpp [Windows CE Recommended Format] MSB LSB Address 7 654321 0 [Bit] (Byte0) +00 P00 (Byte1) +01 P01 (Byte2) +02 P02 +03 ... ... P10 +LAO+00 P11 +LAO+01 P12 +LAO+02 ... +LAO+03 ... Display Memory
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[1:0]: Put 2bit data
... ...
LAO: Line Address Offset --Unused bits should be 0 Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[3:0]: Put 4bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[3:0]: Put 4bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[4:0]: Put 5bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
Rev. 1.0, 02/03, page 1067 of 1294
9. Unpacked 6bpp [Windows CE Recommended Format] MSB LSB Address 7 6 5 4 3 2 1 0 [Bit] (Byte0) +00 P00 (Byte1) +01 P01 (Byte2) +02 P02 +03 ... ... P10 +LAO+00 P11 +LAO+01 P12 +LAO+02 +LAO+03 ... Display Memory ... 10. Packed 8bpp [Windows CE Recommended Format] MSB LSB Address 7 6 5 4 3 2 1 0 [Bit] (Byte0) +00 P00 (Byte1) +01 P01 (Byte2) +02 P02 +03 ... ... P10 +LAO+00 P11 +LAO+01 P12 +LAO+02 ... +LAO+03 Display Memory ...
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[5:0]: Put 6bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
Top Left Pixel P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 ... ... Display Pn = Pn[7:0]: Put 8bit data
... ...
LAO: Line Address Offset --Unused bits should be 0
11. Unpacked color 15bpp (RGB 555) [Windows CE Recommended Format] Top Left Pixel MSB LSB Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 ... (Word0) P10 P11 P12 P13 P14 P15 P16 P17 ... +00 P00R P00G P00B ... (Word2) +02 P01R P01G P01B Display (Word4) +04 P02R P02G P02B +06 ... Pr = (PrR, PrG, PrB). Pr 15bit data ... PrR = PrR[4.0]. Pr 5bit RED data P10R P10G P10B +LAO PrG = PrG[4.0]. Pr 5bit GREEN data P11R P11G P11B +LAO+02 PrB = PrB[4.0]. Pr 5bit BLUE data P12R P12G P12B +LAO+04 ... LAO: Line Address Offset +LAO+06 --Unused bits should be 0 Display Memory ... 12. Packed color 16bpp (RGB 565) [Windows CE Recommended Format] Top Left Pixel MSB LSB Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 [Bit] P00 P01 P02 P03 P04 P05 P06 P07 ... (Word0) P10 P11 P12 P13 P14 P15 P16 P17 ... +00 P00R P00G P00B ... (Word2) +02 P01R P01G P01B Display (Word4) +04 P02R P02G P02B +06 ... Pr = (PrR, PrG, PrB). Pr 16bit data ... PrR = PrR[4.0]. Pr 5bit RED data P10R P10G P10B +LAO PrG = PrG[5.0]. Pr 6bit GREEN data P11R P11G P11B +LAO+02 PrB = PrB[4.0]. Pr 5bit BLUE data P12R P12G P12B +LAO+04 ... LAO: Line Address Offset +LAO+06 --Unused bits should be 0 Display Memory ...
Rev. 1.0, 02/03, page 1068 of 1294
30.4.5
Setting the Display Resolution
The display resolution is set with the LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and LDVSYNR. The LCD current-alternating period for STN or DSTN display is set by using the LDACLNR. The initial values in these registers are set to VGA (640 x 480 dots), a typical resolution for STN or DSTN display. The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the display interval of one screen (as specified by a size-related register) + retrace line interval (nondisplay interval), and by the frequency of the clock used. This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the display). This function is set up by using the LDINTR. 30.4.6 Power Supply Control Sequence Processing
The LCD module normally requires processing of a specific sequence for cutting off of the input power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD power-supply control pins (VCPWC, VEPWC, and LCD_DON), are used to provide processing of power-supply control sequences that suits the requirements of the LCD module. Figures 30.4 to 30.7 are summary timing charts for power-supply control sequences and table 30.5 is a summary of available power-supply control sequence periods.
Rev. 1.0, 02/03, page 1069 of 1294
(1) Power-Supply Control for STN/DSTN Panels
(in) DON register Start power supply (out) VCPWC pin (out) Display data, timing signal Start power cutoff VCPE = ON
Undefined
Arbitrary
Undefined
(out) VEPWC pin
VEPE = ON
(out) DON pin Register control sequence (out) LPS register
DONE = ON
(a)= 0fr
(b)=1fr
(c)=1fr
(d)=1fr
(e)=1fr
(f)= 0fr
00b LCD module stopped
00b, 11b
11b LCD module active
00b, 11b
00b LCD module stopped
Figure 30.4 Power-Supply Control Sequence and States of the LCD Module
(2) Power-Supply Control for LCD Panels other than STN or DSTN (in) DON register Start power supply (out) VCPWC pin Start power cutoff (Internal signal) VCPE = OFF
(out) Display data, timing signal (out) VEPWC pin
Undefined
Arbitrary (Internal signal)
Undefined
VEPE = OFF
(out) DON pin
DONE = ON
Register control sequence (out) LPS register
(a)= 0 fr (b)= 0 fr 00b LCD module stopped
(c)= 1 fr
(d)= 1 fr
(f)= 0 fr (e)= 0 fr 00b LCD module stopped
00b, 11b
11b LCD module active
00b, 11b
Figure 30.5 Power-Supply Control Sequence and States of the LCD Module
Rev. 1.0, 02/03, page 1070 of 1294
(3) Power-Supply Control for TFT Panels (in) DON register Start power supply (out) VCPWC pin (out) Display data, timing signal Start power cutoff VCPE = ON
Undefined
Arbitrary
Undefined
(out) VEPWC pin (Internal signal) (out) DON pin
VEPE = ON
DONE = OFF
Register control sequence (out) LPS register 00b LCD module stopped
(a)=1fr
(b)= 6 fr
(c)=0 fr
(d)=0 fr
(e)= 1 fr
(f)=1 fr
00b, 11b
11b LCD module active
00b, 11b
00b LCD module stopped
Figure 30.6 Power-Supply Control Sequence and States of the LCD Module
(4) Power Supply Control for LCD panels other than TFT (in) DON register Start power supply (out) VCPWC pin (out) Display data, timing signal (out) VEPWC pin (Internal signal) (out) DON pin Register control sequence (a)= 0 fr (b)= 0 fr (c)= 0 fr 00b LCD module stopped 11b LCD module active (f)= 0 fr (e)= 0 fr (d)= 0 fr 00b LCD module stopped DONE = OFF (Internal signal) Start power cutoff VCPE = OFF
Undefined
Arbitrary (Internal signal)
Undefined
VEPE = OFF
(out) LPS register
Figure 30.7 Power-Supply Control Sequence and States of the LCD Module
Rev. 1.0, 02/03, page 1071 of 1294
Table 30.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates
ONX, OFFX Register Value H'F H'0 H'1 H'2 H'3 H'4 H'5 H'6 H'7 H'8 H'9 H'A H'B H'C H'D H'E Frame Rate 120 Hz (-1+1)/120 = 0.00 (ms) (0+1)/120 = 8.33 (ms) (1+1)/120 = 16.67 (ms) (2+1)/120 = 25.00 (ms) (3+1)/120 = 33.33 (ms) (4+1)/120 = 41.67 (ms) (5+1)/120 = 50.00 (ms) (6+1)/120 = 58.33 (ms) (7+1)/120 = 66.67 (ms) (8+1)/120 = 75.00 (ms) (9+1)/120 = 83.33 (ms) (10+1)/120 = 91.67 (ms) (11+1)/120 = 100.00 (ms) (12+1)/120 = 108.33 (ms) (13+1)/120 = 116.67 (ms) (14+1)/120 = 125.00 (ms) 60 Hz (-1+1)/60 = 0.00 (ms) (0+1)/60 = 16.67 (ms) (1+1)/60 = 33.33 (ms) (2+1)/60 = 50.00 (ms) (3+1)/60 = 66.67 (ms) (4+1)/60 = 83.33 (ms) (5+1)/60 = 100.00 (ms) (6+1)/60 = 116.67 (ms) (7+1)/60 = 133.33 (ms) (8+1)/60 = 150.00 (ms) (9+1)/60 = 166.67 (ms) (10+1)/60 = 183.33 (ms) (11+1)/60 = 200.00 (ms) (12+1)/60 = 216.67 (ms) (13+1)/60 = 233.33 (ms) (14+1)/60 = 250.00 (ms)
Each of the ONA, ONB, ONC, OFFD, OFFE, and OFFF registers can be used to set the powersupply control-sequence periods, in units of frames, from 0 to 15. The register setting is one less than the value for that register, so the settings for H'0 through H'E correspond to 1 through 15 frames, with H'F set as 0 frames. Actual sequence periods depend on the register values and the frame frequency of the display. The following table gives power-supply control-sequence periods for display frame frequencies used by typical LCD modules. * When ONB is set to H'6 and display's frame frequency is 120 Hz The display's frame frequency is 120 Hz. 1 frame period is thus 8.33 (ms) = 1/120 (sec). The power-supply input sequence period is 7 frames because ONB setting is subtracted by 1. As a result, the sequence period is 58.33 (ms) = 8.33 (ms) x 7.
Rev. 1.0, 02/03, page 1072 of 1294
Table 30.6 LCDC Operating Modes
Mode Display on (LCDC active) Register setting: DON = 1 Function Timing signals and display data according to the prescribed resolution and number of colors are output to the LCD module. Register access is enabled. Timing signals and display data according to the prescribed resolution and number of colors are not output to the LCD module.
Display off (LCDC stopped)
Register setting: DON = 0
Table 30.7 LCD Module Power-Supply States (STN/DSTN module)
Power Supply for Logic VCPWC Display Data, Timing Signal LCD_CL2, LCD_CL1, LCD_FLM, LCD_M_DISP, LCD_DATA Supply Supply Supply Power Supply for High-Voltage Systems DON Signal VEPWC LCD_DON
State Control Pin
Operating State (Transitional State)
Supply Supply Supply Supply
Supply Supply
Supply
Stopped State
Rev. 1.0, 02/03, page 1073 of 1294
(TFT module)
State Control Pin Power Supply for Logic VCPWC Display Data, Timing Signal LCD_CL2, LCD_CL1, LCD_FLM, LCD_M_DISP, LCD_DATA Supply Supply Power Supply for High-Voltage Systems VEPWC
Operating State (Transitional State) Stopped State
Supply Supply Supply
Supply
The table above shows the states of the power supply, display data, and timing signals for the typical LCD module in its active and stopped states. Some of the supply voltages described may not be necessary, because some modules internally generate the power supply required for highvoltage systems from the logic-level power-supply voltage. Warning regarding display-off mode (LCDC stopped): When LCD module power-supply control-sequence processing is in use by the LCDC and the supply of power is cut off while the LCDC is in its display-on mode, the LCDC may not function properly. In the worst case, the connected LCD module may be damaged. 30.4.7 Operation for Hardware Rotation
Operation in hardware-rotation mode is described below. Hardware-rotation mode can be thought of as using a landscape-format LCD panel instead of a portrait-format LCD panel by placing the landscape-format LCD panel as if it were a portrait-format panel. Whether the panel is intended for use in landscape or portrait format is thus no problem. The panel must, however, be within 320 pixels wide. When conducting hardware rotation, the following five changes must be made from the settings for no hardware rotation. (The following example is for a display at 8 bpp. At 16 bpp, the amount of memory per dot will be doubled. The image size and register values used for rotation will thus be different.) 1. The image data must be prepared for display in the rotated panel. (If 240 x 320 pixels will be required after rotation, 240 x 320 pixel image data must be prepared.) 2. The register settings for the address of the image data must be changed (LDSARU and LDLAOR).
Rev. 1.0, 02/03, page 1074 of 1294
3. LDLAOR should be power of 2 (when the horizontal width after rotation is 240 pixels, LDLAOR should be set to 256). 4. Graphics software should also be set as in number 3. 5. LDSARU should be changed to represent the address of the data for the lower-left pixel of the image rather than that of the data for the upper-left pixel of the image.
1) Normal mode LDSARU (Origin) Image LDSARU + LDLAOR - 1
Image
Scanning origin is LDSARU. Scanning is done in X direction, from left to right.
LDSARU + LDLAOR x LDVDLNR - 1(Destination) Origin LCD panel
Image
Destination
For example, the registers have been set up for the display of image data in landscape format (320 x 240), which starts from LDSARU = 0x0c001000, on a 320 x 240 LCD panel. The graphics driver software is complete. Some changes are required to apply hardware rotation and use the panel as a 240 x 320 display. If LDLAOR is 512, the graphics driver software uses this power of 2 as the offset for the calculation of the addresses of Y coordinates in the image data. Before setting ROT to 1, the image data must be redrawn to suit the 240 x 320 LCD panel. LDLAOR will then be 256 because the size has changed and the graphics driver software must be altered accordingly. The point that corresponds to LDSARU moves from the upper left to the lower left of the display, so LDSARU should be changed to 0x0c001000 + 256 * 319. Note: Hardware rotation is a function which allows the use of an LCD panel that has been rotated by 90 degrees, and the settings for the LCD panel itself must correspond to those of the LCD panel before rotation. Rotation is possible regardless of the drawing process
Rev. 1.0, 02/03, page 1075 of 1294
carried out by the graphics driver software, but the image size and address offset values for the image managed by the graphics driver software must correspond to those of the actual image.
2) Rotation mode LDSARU - LDLAOR x (HDCN x 8 - 2) - 1(Destination) Image
Scanning origin is LDSARU. Scanning is done in Y direction, from bottom to top. LDSARU (Origin) Origin LCD panel
Destination
Rev. 1.0, 02/03, page 1076 of 1294
30.5
Clock and LCD Data Signal Examples
1) STN monochrome 4-bit data bus module
DOTCLK LCD_CL2 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 LCD_DATA4 to 15 Low B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
Figure 30.8 Clock and LCD Data Signal Example
2) STN monochrome 8-bit data bus module
DOTCLK LCD_CL2 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
LCD_DATA8 to 15 Low
Figure 30.9 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1077 of 1294
3) STN color 4-bit data bus module
DOTCLK LCD_CL2 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G13 G12 B13 B12 R14 R13 G14 B14 R15 G15 B15
LCD_DATA4 to 15 Low
Figure 30.10 Clock and LCD Data Signal Example
4) STN color 8-bit data bus module
DOTCLK LCD_CL2 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
LCD_DATA8 to 15 Low
Figure 30.11 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1078 of 1294
5) STN color 12-bit data bus module
DOTCLK LCD_CL2 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 LCD_DATA12 to 15 Low R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
Figure 30.12 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1079 of 1294
6) STN color 16-bit data bus module
DOTCLK LCD_CL2 LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 B10 R11 G11 B11 R12 G12 B12 R13 G13 B13 R14 G14 B14 R15 G15 B15
Figure 30.13 Clock and LCD Data Signal Example
7) DSTN monochrome 8-bit data bus module
DOTCLK LCD_CL2 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 UB0 UB1 UB2 UB3 LB0 LB1 LB2 LB3 UB4 UB5 UB6 UB7 LB4 LB5 LB6 LB7
LCD_DATA8 to 15 Low
Figure 30.14 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1080 of 1294
8) DSTN monochrome 16-bit data bus module DOTCLK LCD_CL2 LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 UB0 UB1 UB2 UB3 UB4 UB5 UB6 UB7 LB0 LB1 LB2 LB3 LB4 LB5 LB6 LB7
Figure 30.15 Clock and LCD Data Signal Example
9) DSTN color 8-bit data bus module
DOTCLK LCD_CL2 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 UR0 UG0 UB0 UR1 LR0 LG0 LB0 LR1 UG1 UB1 UR2 UG2 LG1 LB1 LR2 LG2 UB2 UR3 UG3 UB3 LB2 LR3 LG3 LB3 UR4 UG4 UB4 UR5 LR4 LG4 LB4 LR5 UG5 UB5 UR6 UG6 LG5 LB5 LR6 LG6 UB6 UR7 UG7 UB7 LB6 LR7 LG7 LB7
LCD_DATA8 to 15 Low
Figure 30.16 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1081 of 1294
10) DSTN color 12-bit data bus module DOTCLK LCD_CL2 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 UR0 UG0 UB0 UR1 UG1 UB1 LR0 LG0 LB0 LR1 LG1 LB1 UR2 UG2 UB2 UR3 UG3 UB3 LR2 LG2 LB2 LR3 LG3 LB3 UR4 UG4 UB4 UR5 UG5 UB5 LR4 LG4 LB4 LR5 LG5 LB5 UR6 UG6 UB6 UR7 UG7 UB7 LR6 LG6 LB6 LR7 LG7 LB7
LCD_DATA12 to 15 Low
Figure 30.17 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1082 of 1294
11) DSTN color 16-bit data bus module DOTCLK LCD_CL2 LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 UR0 UG0 UB0 UR1 UG1 UB1 UR2 UG2 LR0 LG0 LB0 LR1 LG1 LB1 LR2 LG2 UB2 UR3 UG3 UB3 UR4 UG4 UB4 UR5 LB2 LR3 LG3 LB3 LR4 LG4 LB4 LR5 UG5 UB5 UR6 UG6 UB6 UR7 UG7 UB7 LG5 LB5 LR6 LG6 LB6 LR7 LG7 LB7
Figure 30.18 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1083 of 1294
12) TFT color 12-bit data bus module
DOTCLK LCD_CL2 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 LCD_DATA12 to 15 Low R03 R02 R01 R00 G03 G02 G01 G00 B03 B02 B01 B00 R13 R12 R11 R10 G13 G12 G11 G10 B13 B12 B11 B10 R23 R22 R21 R20 G23 G22 G21 G20 B23 B22 B21 B20 R33 R32 R31 R30 G33 G32 G31 G30 B33 B33 B32 B31
Figure 30.19 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1084 of 1294
13) TFT color 16-bit data bus module
DOTCLK LCD_CL2 LCD_DATA15 LCD_DATA14 LCD_DATA13 LCD_DATA12 LCD_DATA11 LCD_DATA10 LCD_DATA9 LCD_DATA8 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 R05 R04 R03 R02 R01 G05 G04 G03 G02 G01 G00 B05 B04 B03 B02 B01 R15 R14 R13 R12 R11 G15 G14 G13 G12 G11 G10 B15 B14 B13 B12 B11 R25 R24 R23 R22 R21 G25 G24 G23 G22 G21 G20 B25 B24 B23 B22 B21 R35 R34 R33 R32 R31 G35 G34 G33 G32 G31 G30 B35 B34 B33 B32 B31
Figure 30.20 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1085 of 1294
14) 8-bit interface color 640 x 480 STN-LCD Horizontal wave DOTCLK LCD_CL2 LCD_DATA7 LCD_DATA6 LCD_DATA5 LCD_DATA4 LCD_DATA3 LCD_DATA2 LCD_DATA1 LCD_DATA0 LCD_DATA8 to 15 LCD_CL1 One horizontal display time (640 x DCLK) Horizontal synchronization position Horizontal retrace time Horizontal synchronization width R0 B2 G0 R3 B0 G3 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 R9 G9 B9 R10 G10 G637 B637 R638 G638 B638 R639 G639 B639 R0 G0 B0 R1 G1 B1 R2 G2
R1 B3 G1 R4 B1 G4
R2 B4 G2 R5 Low
One horizontal time ( ex. 640 + 8 x 3 (:3 character) = 664 DCLK) No vertical retrace LCD_CL2 LCD_CL1 LCD_DATA LCD_FLM 1st line data One horizontal time One vertical retrace LCD_CL2 LCD_CL1 LCD_DATA LCD_FLM 1st line data One horizontal time One frame time (481 x CL1) 2nd line data 480th line data Vertical retrace time (One horizontal time) 1st line data 2nd line data Valid Valid Valid Valid Valid 2nd line data 480th line data 1st line data 2nd line data Valid Valid Valid Valid Valid Valid
One frame time (480 x CL1)
Next frame time (480 x CL1)
Next frame time (480 x CL1)
Figure 30.21 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1086 of 1294
15) 16-bit I/F color 640 x 480 TFT-LCD Horizontal wave DOTCLK LCD_CL2 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 B0, 3 B1, 3 B0, 4 B1, 4 B0, 5 B1, 5 B0, 6 B1, 6 B0, 7 B1, 7 G0, 2 G1, 2 G0, 3 G1, 3 G0, 4 G1, 4 G0, 5 G1, 5 G0, 6 G1, 6 G0, 7 G1, 7 R0, 3 R1, 3 R0, 4 R1, 4 R0, 5 R1, 5 R0, 6 R1, 6 R0, 7 R1, 7 B639,3 B639,4 B639,5 B639,6 B639,7 G639,2 G639,3 G639,4 G639,5 G639,6 G639,7 R639,3 R639,4 R639,5 R639,6 R639,7
8DCLK
8DCLK
8DCLK
B0, 3 B0, 4 B0, 5 B0, 6 B0, 7 G0, 2 G0, 3 G0, 4 G0, 5 G0, 6 G0, 7 R0, 3 R0, 4 R0, 5 R0, 6 R0, 7
LCD_CL1 LCD_M_DISP One horizontal display time (640 x DCLK) Horizontal synchronization position Horizontal retrace time Horizontal synchronization width
One horizontal time ( ex. 640 + 8 x 3 (:3 character) = 664 DCLK) No vertical retrace LCD_CL2 LCD_CL1 LCD_DATA LCD_M_DISP LCD_FLM 1st line data 2nd line data One frame time (480 x CL1) 480th line data 1st line data 2nd line data Valid Valid Valid Valid Valid Valid
One horizontal time Next frame time (480 x CL1)
Figure 30.22 Clock and LCD Data Signal Example
Rev. 1.0, 02/03, page 1087 of 1294
Rev. 1.0, 02/03, page 1088 of 1294
Section 31 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. When break conditions are set in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU. This function makes it easy to design an effective selfmonitoring debugger, enabling programs to be debugged with the chip alone, without using an incircuit emulator.
31.1
Features
The UBC has the following features. * Two break channels (A and B) User break interrupts can be generated on independent conditions for channels A and B or on sequential conditions (sequential break setting: channel A channel B). * The following break compare conditions can be set: Address (selection of 32-bit virtual address and ASID for comparison): Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits masked/lower 20 bits masked/all bits masked ASID: All bits compared/all bits masked Data (channel B only, 32-bit mask capability) Bus cycle: Instruction access/operand access Read/write Operand size: Byte/word/longword/quadword * An instruction access cycle break can be effected before or after the instruction is executed.
Rev. 1.0, 02/03, page 1089 of 1294
Figure 31.1 shows a block diagram of the UBC.
Access control Address bus Channel A Access comparator BBRA Data bus
BARA Address comparator
BASRA BAMRA
Channel B Access comparator BBRB
BARB Address comparator
BASRB BAMRB
Data comparator [Legend] BBRA: BARA: BASRA: BAMRA: BBRB: BARB: BASRB: BAMRB: BDRB: BDMRB: BRCR: Break bus cycle register A Break address register A Break ASID register A Break address mask register A Break bus cycle register B Break address register B Break ASID register B Break address mask register B Break data register B Break data mask register B Break control register
BDRB BDMRB
Control
BRCR
User break trap request
Figure 31.1 Block Diagram of UBC
Rev. 1.0, 02/03, page 1090 of 1294
31.2
Register Descriptions
The UBC has the following registers. Refer to section 32, List of Registers, for the addresses of the registers and the state of each register in each processor state. Table 31.1 Register Configuration (1)
Register Name Break address register A Break ASID register A Break address mask register A Break bus cycle register A Break address register B Break ASID register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register Abbreviation BARA BASRA BAMRA BBRA BARB BASRB BAMRB BBRB BDRB BDMRB BRCR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P4 Address HFF20 0000 HFF00 0014 HFF20 0004 HFF20 0008 HFF20 000C HFF00 0018 HFF20 0010 HFF20 0014 HFF20 0018 HFF20 001C HFF20 0020 Sync Area 7 Address Size Clock H1F20 0000 HFF00 0014 H1F20 0004 H1F20 0008 H1F20 000C H1F00 0018 H1F20 0010 H1F20 0014 H1F20 0018 H1F20 001C H1F20 0020 32 8 8 16 32 8 8 16 32 32 16 Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick
Rev. 1.0, 02/03, page 1091 of 1294
Table 31.1 Register Configuration (2)
Power-on Reset by RESET Pin/WDT/ Register Name Abbrev. H-UDI Manual Reset by RESET Pin/WDT/ Multiple Exception Sleep by Sleep Instruction/ Deep Sleep by Software/ by Hardware Each Module Standby
Break address register A Break ASID register A
BARA BASRA
Undefined Undefined Undefined H0000 Undefined Undefined Undefined H0000 Undefined Undefined H0000*
1
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
*
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Break address mask register A BAMRA Break bus cycle register A Break address register B Break ASID register B BBRA BARB BASRB
Break address mask register B BAMRB Break bus cycle register B Break data register B Break data mask register B Break control register BBRB BDRB BDMRB BRCR
Note:
After exiting hardware standby mode, this LSI enters the power-on reset state caused by the RESET pin. *1 This value includes an undefined bit value. Refer to the register description. *
The access size must be the same as the control register size. If the access size is different from the register size, no data will be written to the register and an undefined value will be read. UBC control register contents cannot be transferred to a floating-point register using a floatingpoint memory data transfer instruction. When a UBC control register is updated, use either of the following methods to make the updated value valid: 1. Execute an RTE instruction after the memory store instruction that updated the register. The updated value will be valid from the RTE instruction destination onward. 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. This LSI executes two instructions in parallel and a minimum of 0.5 states are required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward.
Rev. 1.0, 02/03, page 1092 of 1294
31.2.1
Break Address Register A, B (BARA, BARB)
BARA and BARB are 32-bit readable/writable registers that specify the virtual addresses used in the channel A and channel B break conditions. * BARA
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R/W 15 R/W 30 R/W 14 R/W 29 R/W 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16
BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0
Bit 31 to 0
Bit Name BAA31 to BAA0
Initial Value
R/W R/W
Description Break Address A31 to A0 Stores the virtual addresses used in the channel A break condition.
*
BARB
Bit: 31 R/W 15 R/W 30 R/W 14 R/W 29 R/W 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16
Initial value: R/W: Bit: Initial value: R/W:
BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0
Bit 31 to 0
Bit Name BAB31 to BAB0
Initial Value
R/W R/W
Description Break Address B31 to B0 Stores the virtual addresses used in the channel B break condition.
Rev. 1.0, 02/03, page 1093 of 1294
31.2.2
Break ASID Register A, B (BASRA, BASRB)
BASRA and BASRB are 8-bit readable/writable registers that specify the ASID used in the channel A and channel B break conditions. * BASRA
Bit: Initial value: R/W: 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W
BASA7 BASA6 BASA5 BASA4 BASA3 BASA2 BASA1 BASA0
Bit 7 to 0
Bit Name BASA7 to BASA0
Initial Value
R/W R/W
Description Break ASID A7 to A0 Stores the ASID (bits 7 to 0) used in the channel A break condition.
*
BASRB
Bit: Initial value: R/W: 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W
BASB7 BASB6 BASB5 BASB4 BASB3 BASB2 BASB1 BASB0
Bit 7 to 0
Bit Name BASB7 to BASB0
Initial Value
R/W R/W
Description Break ASID B7 to B0 Stores the ASID (bits 7 to 0) used in the channel B break condition.
Rev. 1.0, 02/03, page 1094 of 1294
31.2.3
Break Address Mask Register A (BAMRA)
BAMRA is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARA.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 R/W 2 R/W 1 R/W 0 R/W
BAMA2 BASMA BAMA1 BAMA0
Bit 7 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Break ASID Mask A Specifies whether all bits of the channel A break ASID (BASA7 to BASA0) set in BASRA are to be masked. 0: All BASRA bits are included in break conditions 1: No BASRA bits are included in break conditions
2
BASMA
--
R/W
3 1 0
BAMA2 BAMA1 BAMA0
-- -- --
R/W R/W R/W
Break Address Mask A2 to A0 These bits specify which bits of the channel A break address (BAA31 to BAA0) set in BARA are to be masked. 000: All BARA bits are included in break conditions 001: Lower 10 bits of BARA are masked, and not included in break conditions 010: Lower 12 bits of BARA are masked, and not included in break conditions 011: All BARA bits are masked, and not included in break conditions 100: Lower 16 bits of BARA are masked, and not included in break conditions 101: Lower 20 bits of BARA are masked, and not included in break conditions 11x: Setting prohibited
Note: x: Don't care
Rev. 1.0, 02/03, page 1095 of 1294
31.2.4
Break Address Mask Register B (BAMRB)
BAMRB is an 8-bit readable/writable register that specifies which bits are to be masked in the break ASID set in BASRA and the break address set in BARB.
Bit: Initial value: R/W: 7 0 R 6 0 R 5 0 R 4 0 R 3 R/W 2 R/W 1 R/W 0 R/W
BAMB2 BASMB BAMB1 BAMB0
Bit 7 to 4
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Break ASID Mask B Specifies whether all bits of the channel B break ASID (BASB7 to BASB0) set in BASRB are to be masked. 0: All BASRB bits are included in break conditions 1: No BASRB bits are included in break conditions
2
BASMB
--
R/W
3 1 0
BAMB2 BAMB1 BAMB0
-- -- --
R/W R/W R/W
Break Address Mask B2 to B0 These bits specify which bits of the channel B break address (BAB31 to BAB0) set in BARB are to be masked. 000: All BARB bits are included in break conditions 001: Lower 10 bits of BARB are masked, and not included in break conditions 010: Lower 12 bits of BARB are masked, and not included in break conditions 011: All BARB bits are masked, and not included in break conditions 100: Lower 16 bits of BARB are masked, and not included in break conditions 101: Lower 20 bits of BARB are masked, and not included in break conditions 11x: Setting prohibited
Note: x: Don't care
Rev. 1.0, 02/03, page 1096 of 1294
31.2.5
Break Bus Cycle Register A (BBRA)
BBRA is a 16-bit readable/writable register that specifies three conditions from among the channel A break conditions: instruction access/operand access, read/write, and operand size.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 5 4 3 2 1 0
SZA2 IDA1 0 R/W 0 R/W
IDA0 RWA1 RWA0 SZA1 SZA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 15 to 7
Bit Name --
Initial Value R/W All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Access/Operand Access Select A These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel A break conditions. 00: Condition comparison is not performed 01: Instruction access cycle is used as break condition 10: Operand access cycle is used as break condition 11: Instruction access cycle or operand access cycle is used as break condition
5 4
IDA1 IDA0
0 0
R/W R/W
3 2
RWA1 RWA0
0 0
R/W R/W
Read/Write Select A These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel A break conditions. 00: Condition comparison is not performed 01: Read cycle is used as break condition 10: Write cycle is used as break condition 11: Read cycle or write cycle is used as break condition
6 1 0
SZA2 SZA1 SZA0
0 0 0
R/W R/W R/W
Operand Size Select A These bits select the operand size of the bus cycle used as a channel A break conditions. 000: Operand size is not included in break conditions 001: Byte access is used as break condition 010: Word access is used as break condition 011: Longword access is used as break condition 100: Quadword access is used as break condition 101: Setting prohibited 11x: Setting prohibited
Note: x: Don't care
Rev. 1.0, 02/03, page 1097 of 1294
31.2.6
Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register that specifies three conditions from among the channel B break conditions: instruction access/operand access, read/write, and operand size.
Bit: Initial value: R/W: 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 5 4 3 2 1 0
SZB2 IDB1 0 R/W 0 R/W
IDB0 RWB1 RWB0 SZB1 SZB0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Bit 15 to 7
Bit Name Initial Value R/W -- All 0 R
Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Access/Operand Access Select B These bits specify whether an instruction access cycle or an operand access cycle is used as the bus cycle in the channel B break conditions. 00: Condition comparison is not performed 01: Instruction access cycle is used as break condition 10: Operand access cycle is used as break condition 11: Instruction access cycle or operand access cycle is used as break condition
5 4
IDB1 IDB0
0 0
R/W R/W
3 2
RWB1 RWB0
0 0
R/W R/W
Read/Write Select B These bits specify whether a read cycle or write cycle is used as the bus cycle in the channel B break conditions. 00: Condition comparison is not performed 01: Read cycle is used as break condition 10: Write cycle is used as break condition 11: Read cycle or write cycle is used as break condition
6 1 0
SZB2 SZB1 SZB0
0 0 0
R/W R/W R/W
Operand Size Select B These bits select the operand size of the bus cycle used as a channel B break conditions. 000: Operand size is not included in break conditions 001: Byte access is used as break condition 010: Word access is used as break condition 011: Longword access is used as break condition 100: Quadword access is used as break condition 101: Setting prohibited 11x: Setting prohibited
Note: x: Don't care
Rev. 1.0, 02/03, page 1098 of 1294
31.2.7
Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register that specifies the data (bits 31 to 0) to be used in the channel B break conditions.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R/W 15 R/W 30 R/W 14 R/W 29 R/W 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8 R/W 23 R/W 7 R/W 22 R/W 6 R/W 21 R/W 5 R/W 20 R/W 4 R/W 19 R/W 3 R/W 18 R/W 2 R/W 17 R/W 1 R/W 16 R/W 0 R/W
BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16
BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8
BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0
Bit 31 to 0
Bit Name BDB31 to BDB0
Initial Value --
R/W R/W
Description Break Data B These bits store the data (bits 31 to 0) to be used in the channel B break conditions.
31.2.8
Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register that specifies which bits of the break data set in BDRB are to be masked. When the value of the data bus is included in the break conditions, its operand size should be specified. When the byte size is specified as an operand size, the same data should be specified to bits 15 to 8 and bits 7 to 0 in both BDRB and BDMRB.
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 R/W 15 R/W 30 R/W 14 R/W 29 R/W 13 R/W 28 R/W 12 R/W 27 R/W 11 R/W 26 R/W 10 R/W 25 R/W 9 R/W 24 R/W 8
BDMB8
23 R/W 7
BDMB7
22 R/W 6
BDMB6
21 R/W 5
BDMB5
20 R/W 4
BDMB4
19 R/W 3
BDMB3
18 R/W 2
BDMB2
17 R/W 1
BDMB1
16 R/W 0
BDMB0
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 1.0, 02/03, page 1099 of 1294
Bit 31 to 0
Bit Name BDMB31 to BDMB0
Initial Value --
R/W R/W
Description Break Data Mask B These bits specify whether the corresponding bit of the channel B break data Bn set in BDRB is to be masked. 0: Channel B break data Bn is included in break conditions 1: Channel B break data Bn is masked, and not included in break conditions
Note: n = 31 to 0
31.2.9
Break Control Register (BRCR)
BRCR is a 16-bit readable/writable register that specifies (1) whether channels A and B are to be used as two independent channels or in a sequential condition, (2) whether the break is to be effected before or after instruction execution, (3) whether the BDRB register is to be included in the channel B break conditions, and (4) whether the user break debug function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The PCBA, DBEB, PCBB, and SEQ bits are undefined after a power-on reset or manual reset, so these bits should be initialized by software as necessary.
Bit: Initial value: R/W: 15 14 13 0 R 12 0 R 11 0 R 10 PCBA R/W 9 0 R 8 0 R 7 6 5 0 R 4 0 R 3 SEQ R/W 2 0 R 1 0 R 0 UBDE 0 R/W
CMFA CMFB 0 R/W 0 R/W
DBEB PCBB R/W R/W
Bit 15
Bit Name CMFA
Initial Value 0
R/W R/W
Description Condition Match Flag A Set to 1 when a break condition set for channel A is satisfied. This flag is not cleared to 0. To confirm that the flag is set again after once being set, it should be cleared with a write. 0: Channel A break condition does not matched 1: Channel A break condition has matched
14
CMFB
0
R/W
Condition Match Flag B Set to 1 when a break condition set for channel B is satisfied. This flag is not cleared to 0. To confirm that the flag is set again after once being set, it should be cleared with a write. 0: Channel B break condition is not matched 1: Channel B break condition match has occurred
Rev. 1.0, 02/03, page 1100 of 1294
Bit
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Instruction Access Break Select A Specifies whether a channel A instruction access cycle break is to be effected before or after the instruction is executed. 0: Channel A PC break is effected before instruction execution 1: Channel A PC break is effected after instruction execution
13 to 11 --
10
PCBA
--
R/W
9 ,8
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Data Break Enable B Specifies whether the data bus condition is to be included in the channel B break conditions. When the data bus is included in the break conditions, bits IDB1 to IDB0 in BBRB should be set to B'10 or B'11. 0: Data bus condition is not included in channel B break conditions 1: Data bus condition is included in channel B break conditions
7
DBEB
--
R/W
6
PCBB
--
R/W
PC Break Select B Specifies whether a channel B instruction access cycle break is to be effected before or after the instruction is executed. 0: Channel B PC break is effected before instruction execution 1: Channel B PC break is effected after instruction execution
5, 4
--
All 0
R
Reserved These bits are always read as 0. The write value should always be 0. Sequence Condition Select Specifies whether the conditions for channels A and B are to be independent or sequential. 0: Channel A and B comparisons are performed as independent conditions 1: Channel A and B comparisons are performed as sequential conditions (channel A channel B)
3
SEQ
--
R/W
Rev. 1.0, 02/03, page 1101 of 1294
Bit 2, 1
Bit Name --
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. User Break Debug Enable Specifies whether the user break debug function is used or not. 0: User break debug function is not used 1: User break debug function is used
0
UBDE
0
R/W
31.3
31.3.1
Operation
Explanation of Terms Relating to Access
An instruction access is an access that obtains an instruction. For example, fetching an instruction from the branch destination when a branch instruction is executed is an instruction access. An operand access is any memory access for the purpose of instruction execution. For example, the access to address (PC+dispx2+4) in the instruction MOV.W@(disp,PC), Rn is an operand access. As the term "data" is used to distinguish data from an address, the term "operand access" is used in this section. All operand accesses are treated as either read accesses or write accesses. The following instructions require special attention: PREF, OCBP, and OCBWB instructions: Treated as read accesses. MOVCA.L and OCBI instructions: Treated as write accesses. TAS.B instruction: Treated as one read access and one write access. The operand accesses for the PREF, OCBP, OCBWB, and OCBI instructions are accesses with no access data. This LSI handles all operand accesses as having a data size. The data size can be byte, word, longword, or quadword. The operand data size for the PREF, OCBP, OCBWB, MOVCA.L, and OCBI instructions is treated as longword.
Rev. 1.0, 02/03, page 1102 of 1294
31.3.2
Explanation of Terms Instruction Intervals
In this section, "1 (2, 3 ...) instruction(s) after...", as a measure of the distance between two instructions, is defined as follows. A branch is counted as an interval of two instructions. (1) Example of sequence of instructions with no branch: 100 102 104 106 Instruction A (0 instructions after instruction A) Instruction B (1 instruction after instruction A) Instruction C (2 instructions after instruction A) Instruction D (3 instructions after instruction A)
(2) Example of sequence of instructions with a branch (however, the example of a sequence of instructions with no branch should be applied when the branch destination of a delayed branch instruction is the instruction itself + 4): 100 Instruction A: BT/S L200 (0 instructions after instruction A) 102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B) L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B) 202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B) 31.3.3 User Break Operation Sequence
The sequence of operations from setting of break conditions to user break exception handling is described below. 1. Specify pre- or post-execution break in the case of an instruction access, inclusion or exclusion of the data bus value in the break conditions in the case of an operand access, and use of independent or sequential channel A and B break conditions in BRCR. Set the break addresses in BARA and BARB, set the ASIDs corresponding to the break space in BASRA and BASRB, and set the address and ASID masking methods in BAMRA and BAMRB. If the data bus value is to be included in the break conditions, also set the break data in BDRB and the data mask in BDMRB. 2. Set the break bus conditions in BBRA and BBRB. If even one of the BBRA/BBRB instruction access/operand access select (the ID bit) and read/write select groups (the RW bit) is set to B'00, a user break interrupt will not be generated on the corresponding channel. Make the BBRA and BBRB settings after all other break-related register settings have been completed. If breaks are enabled with BBRA/BBRB while the break address, data, mask register, or the break control register is in the initial state after a reset, a break may be generated inadvertently. 3. The operation when a break condition is satisfied depends on the BL bit in SR of the CPU. When the BL bit is 0, exception handling is started and the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is
Rev. 1.0, 02/03, page 1103 of 1294
1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched condition but exception handling is not started. The condition match flags (CMFA, CMFB) are set by a break condition match, but are not automatically reset. Therefore, a memory store instruction should be used on BRCR to clear the flags to 0. For details of the exact setting conditions for the condition match flags, see section 31.3.6, Condition Match Flag Setting. 4. When sequential condition mode has been selected and the channel B condition is matched after the channel A condition has been matched, a break is effected at the instruction at which the channel B condition was matched. For details of the operation when the channel A condition match and channel B condition match occur close together, see section 31.3.8, Contiguous A and B Settings for Sequential Conditions. With sequential conditions, only the channel B condition match flag is set. To clear the channel A match when the channel A condition has been matched but the channel B condition has not yet been matched in sequential condition mode, B'0 should be written to the SEQ bit in BRCR. 31.3.4 Instruction Access Cycle Break
1. When an instruction access/read/word setting is made in BBRA/BBRB, an instruction access cycle can be used as a break condition. In this case, breaking before or after execution of the relevant instruction can be selected with the PCBA/PCBB bit in BRCR. When an instruction access cycle is used as a break condition, clear the LSB of BARA/BARB to 0. A break will not be generated if this bit is set to 1. 2. When a pre-execution break is specified, the break is effected when it is confirmed that the instruction is to be fetched and executed. Therefore, an overrun-fetched instruction (an instruction that is fetched but not executed when a branch or exception occurs) cannot be used in a break. However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch of an instruction subject to a break, the break exception handling is carried out first. The instruction TLB exception handling is performed when the instruction is re-executed (see section 8.2, Exception Types and Priorities). Also, since a delayed branch instruction and the delay slot instruction are executed as a single instruction, if a pre-execution break is specified for a delay slot instruction, the break will be effected before execution of the delayed branch instruction. However, a pre-execution break cannot be specified for the delay slot instruction for an RTE instruction. 3. With a post-execution break, the instruction set as a break condition is executed, then a break interrupt is generated before the next instruction is executed. When a post-execution break is set for a delayed branch instruction, the delay slot is executed and the break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made).
Rev. 1.0, 02/03, page 1104 of 1294
4. When an instruction access cycle is set for channel B, BDRB is ignored in determining whether there is an instruction access match. Therefore, a break condition specified by the DBEB bit in BRCR is not executed. 31.3.5 Operand Access Cycle Break
1. In the case of an operand access cycle break, the bits included in address bus comparison vary as shown below according to the data size specification in BBRA and BBRB.
Data Size Quadword Longword Word Byte Not included in condition Address Bits Compared Address bits A31 to A3 Address bits A31 to A2 Address bits A31 to A1 Address bits A31 to A0 In quadword access, address bits A31 to A3 In longword access, address bits A31 to A2 In word access, address bits A31 to A1 In byte access, address bits A31 to A0
2. When a data value is included in break conditions in channel B When a data value is included in the break conditions, set the DBEB bit in BRCR to 1. In this case, BDRB and BDMRB settings are necessary in addition to the address condition. A user break interrupt is generated when all three conditions, address, ASID, and data, are matched. When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32bit data units satisfies the data match condition. Set the IDB1 to IDB0 bits in BBRB to B'10 or B'11. When byte data is specified, the same data should be set to bits 15 to 8 and bits 7 to 0 in BDRB and BDMRB. When word or byte is set, bits 31 to 16 in BDRB and BDMRB are ignored. 3. When the DBEB bit in BRCR is set to 1, a break is not generated by an operand access with no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction).
Rev. 1.0, 02/03, page 1105 of 1294
31.3.6
Condition Match Flag Setting
1. Instruction access with post-execution condition, or operand access The flag is set when execution of the instruction that causes the break is completed. As an exception to this, however, in the case of an instruction with more than one operand access the flag may be set on detection of the match condition alone, without waiting for execution of the instruction to be completed. A. Example 1: 100 BT L200 (branch performed) 102 Instruction (operand access break on channel A) flag not set B. Example 2: 110 FADD (FPU exception) 112 Instruction (operand access break on channel A) flag not set 2. Instruction access with pre-execution condition The flag is set when the break match condition is detected. A. Example 1: 110 Instruction (pre-execution break on channel A) flag set 112 Instruction (pre-execution break on channel B) flag not set B. Example 2: 110 Instruction (pre-execution break on channel B, instruction access TLB miss) flag set 31.3.7 Program Counter (PC) Value Saved
1. When instruction access (pre-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction at which the break condition match occurred. In this case, a user break interrupt is generated and the fetched instruction is not executed. 2. When instruction access (post-execution) is set as a break condition, the program counter (PC) value saved to SPC in user break interrupt handling is the address of the instruction to be executed after the instruction at which the break condition match occurred. In this case, the fetched instruction is executed, and a user break interrupt is generated before execution of the next instruction. 3. When an instruction access (post-execution) break condition is set for a delayed branch instruction, the delay slot instruction is executed and a user break is effected before execution of the instruction at the branch destination (when the branch is made) or the instruction two instructions ahead of the branch instruction (when the branch is not made). In this case, the PC
Rev. 1.0, 02/03, page 1106 of 1294
value saved to SPC is the address of the branch destination (when the branch is made) or the instruction following the delay slot instruction (when the branch is not made). 4. When operand access (address only) is set as a break condition, the address of the instruction to be executed after the instruction at which the condition match occurred is saved to SPC. 5. When operand access (address + data) is set as a break condition, execution of the instruction at which the condition match occurred is completed. A user break interrupt is generated before execution of instructions from one instruction later to four instructions later. It is not possible to specify at which instruction, from one later to four later, the interrupt will be generated. The start address of the instruction after the instruction for which execution is completed at the point at which user break interrupt handling is started is saved to SPC. If an instruction between one instruction later and four instructions later causes another exception, control is performed as follows. Designating the exception caused by the break as exception 1, and the exception caused by an instruction between one instruction later and four instructions later as exception 2, memory updates and register updates that can not be performed by exception 2 are guaranteed irrespective of the existence of exception 1. The PC value saved is the address of the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source which is not synchronized with an instruction (external interrupt or peripheral module interrupt), exception 1 is used for the exception jump destination and the value written to the exception register (EXPEVT/INTEVT). 31.3.8 Contiguous A and B Settings for Sequential Conditions
When channel A match and channel B match timings are close together, a sequential break may not be guaranteed. Rules relating to the guaranteed range are given below. 1. Instruction access matches on both channel A and channel B
Instruction B is 0 instructions after instruction A Instruction B is 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Equivalent to setting the same address. This setting is prohibited. Sequential operation is not guaranteed. Sequential operation is guaranteed.
2. Instruction access match on channel A, operand access match on channel B
Instruction B is 0 or 1 instruction after instruction A Instruction B is 2 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed.
Rev. 1.0, 02/03, page 1107 of 1294
3. Operand access match on channel A, instruction access match on channel B
Instruction B is 0 to 3 instructions after instruction A Instruction B is 4 or more instructions after instruction A Sequential operation is not guaranteed. Sequential operation is guaranteed.
4. Operand access matches on both channel A and channel B Do not make a setting such that a single operand access will match the break conditions of both channel A and channel B. There are no other restrictions. For example, sequential operation is guaranteed even if two accesses within a single instruction match channel A and channel B conditions in turn.
31.4
Usage Notes
1. Do not execute a post-execution instruction access break for the SLEEP instruction. 2. Do not make an operand access break setting between 1 and 3 instructions before a SLEEP instruction. 3. The value of the BL bit referenced in a user break exception depends on the break setting, as follows. * Pre-execution instruction access break: The BL bit value before the executed instruction is referenced. * Post-execution instruction access break: The OR of the BL bit values before and after the executed instruction is referenced. * Operand access break (address/data): The BL bit value after the executed instruction is referenced. * In the case of an instruction that modifies the BL bit
BL bit 00 10 01 11 A: Accepted M: Masked
PreExecution Instruction Access A M A M
PostExecution Instruction Access A M M M
PreExecution Instruction Access A M A M
PostExecution Instruction Access A M M M
Operand Access (Address/Data) A A M M
Rev. 1.0, 02/03, page 1108 of 1294
* In the case of an RTE delay slot The BL bit value before execution of a delay slot instruction is the same as the BL bit value before execution of an RTE instruction. The BL bit value after execution of a delay slot instruction is the same as the first BL bit value for the first instruction executed on returning by means of an RTE instruction (the same as the value of the BL bit in SSR before execution of the RTE instruction). * If an interrupt or exception is accepted with the BL bit cleared to 0, the value of the BL bit before execution of the first instruction of the exception handling routine is 1. 4. If channels A and B both match independently at virtually the same time, and, as a result, the SPC value is the same for both user break interrupts, only one user break interrupt is generated, but both the CMFA bit and the CMFB bit are set. For example: 110 Instruction (post-execution instruction break on channel A) SPC = 112, CMFA = 1 112 Instruction (pre-execution instruction break on channel B) SPC = 112, CMFB = 1 5. The PCBA or PCBB bit in BRCR is valid for an instruction access break setting. 6. When the SEQ bit in BRCR is 1, the internal sequential break state is initialized by a channel B condition match. For example: A A B (user break generated) B (no break generated) 7. In the event of conflict between a re-execution type exception and a post-execution break in a multistep instruction, the re-executing-type exception is generated. In this case, the CMF bit may or may not be set to 1 when the break condition occurs. 8. A post-execution break is classified as a completed-type exception. Consequently, in the event of conflict between a completed-type exception and a post-execution break, the post-execution break is suppressed in accordance with the priorities of the two events. For example, in the case of conflict between a TRAPA instruction and a post-execution break, the user break is suppressed. However, in this case, the CMF bit is set by the occurrence of the break condition.
31.5
User Break Debug Support Function
The user break debug support function enables the processing used in the event of a user break exception to be changed. When a user break exception occurs, if the UBDE bit in BRCR is set to 1, the DBR value will be used as the branch destination address instead of [VBR + offset]. The value of R15 is saved in SGR regardless of the value of the UBDE bit in BRCR or the type of exception event. A flowchart of the user break debug support function is shown in figure 31.2.
Rev. 1.0, 02/03, page 1109 of 1294
Exception/interrupt generation
Hardware operation
SPC PC SSR SR SR.BL B'1 SR.MD B'1 SR.RB B'1 Exception Exception/ interrupt/trap? Interrupt Trap
EXPEVT exception code
INTEVT interrupt code
EXPEVT H'160 TRA TRAPA (imm)
SGR R15
No
Reset exception?
Yes
Yes
(BRCR.UBDE == 1) && (user break exception)?
No
PC DBR
PC VBR + vector offset
PC H'A000 0000
Debug program R15 SGR (STC instruction)
Exception handler
Execute RTE instruction PC SPC SR SSR End of exception operations
Figure 31.2 User Break Debug Support Function Flowchart
Rev. 1.0, 02/03, page 1110 of 1294
31.6
Examples of Use
(1) Instruction Access Cycle Break Condition Settings 1. Register settings: BASRA = H'80 / BARA = H'0000 0404 / BAMRA = H'00 / BBRA = H'0014 / BASRB = H'70 / BARB = H'0000 8010 / BAMRB = H'01 / BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0400 * Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'0000 0404 / address mask: H'00 Bus cycle: instruction access (post-instruction-execution), read (operand size not included in conditions) Channel B: ASID: H'70 / address: H'0000 8010 / address mask: H'01 Data: H'0000 0000 / data mask: H'0000 0000 Bus cycle: instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break is generated after execution of the instruction at address H'0000 0404 with ASID = H'80, or before execution of an instruction at addresses H'0000 8000 to H'0000 83FE with ASID = H'70. 2. Register settings: BASRA = H'80 / BARA = H'0003 7226 / BAMRA = H'00 / BBRA = H'0016 / BASRB = H'70 / BARB = H'0003 722E / BAMRB = H'00 / BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008 * Conditions set: Channel A channel B sequential mode Channel A: ASID: H'80 / address: H'0003 7226 / address mask: H'00 Bus cycle: instruction access (pre-instruction-execution), read, word Channel B: ASID: H'70 / address: H'0003 722E / address mask: H'00 Data: H'0000 0000 / data mask: H'0000 0000 Bus cycle: instruction access (pre-instruction-execution), read, word The instruction at address H'0003 7266 with ASID = H'80 is executed, then a user break is generated before execution of the instruction at address H'0003 722E with ASID = H'70. 3. Register settings: BASRA = H'80 / BARA = H'0002 7128 / BAMRA = H'00 / BBRA = H'001A / BASRB = H'70 / BARB = H'0003 1415 / BAMRB = H'00 / BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0000 * Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'0002 7128 / address mask: H'00 Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
Rev. 1.0, 02/03, page 1111 of 1294
Channel B: ASID: H'70 / address: H'0003 1415 / address mask: H'00 Data: H'0000 0000 / data mask: H'0000 0000 Bus cycle: CPU, instruction access (pre-instruction-execution), read (operand size not included in conditions) A user break interrupt is not generated on channel A since the instruction access is not a write cycle. A user break interrupt is not generated on channel B since instruction access is performed on an even address. (2) Operand Access Cycle Break Condition Settings 1. Register settings: BASRA = H'80 / BARA = H'0012 3456 / BAMRA = H'00 / BBRA = H'0024 / BASRB = H'70/ BARB = H'000A BCDE / BAMRB = H'02 / BBRB = H'002A / BDRB = H'0000 A512 / BDMRB = H'0000 0000 / BRCR = H'0080 * Conditions set: Independent channel A/channel B mode Channel A: ASID: H'80 / address: H'0012 3456 / address mask: H'00 Bus cycle: operand access, read (operand size not included in conditions) Channel B: ASID: H'70 / address: H'000A BCDE / address mask: H'02 Data: H'0000 A512 / data mask: H'0000 0000 Bus cycle: operand access, write, word Data break enabled On channel A, a user break interrupt is generated in the event of a longword read at address H'0012 3454, a word read at address H'0012 3456, or a byte read at address H'0012 3456, with ASID = H'80. On channel B, a user break interrupt is generated when H'A512 is written by word access to any address from H'000A B000 to H'000A BFFE with ASID = H'70.
Rev. 1.0, 02/03, page 1112 of 1294
31.7
User Break Controller Stop Function
In this LSI, this function stops the clock supplied to the user break controller and is used to minimize power consumption when the chip is operating. Note that, if you use this function, you cannot use the user break controller. 31.7.1 Transition to User Break Controller Stopped State
Setting bit MSTP5 of the STBCR2 (inside the CPG) to 1 stops the clock supply and causes the user break controller to enter the stopped state. Follow steps 1 to 5 below to set bit MSTP5 to 1 and enter the stopped state. 1. Initialize BBRA and BBRB to 0; 2. Initialize BRCR to 0; 3. Make a dummy read of BRCR; 4. Read STBCR2, then set bit MSTP5 in the read data to 1 and write the modified data back. 5. Make two dummy reads of STBCR2. Make sure that, if an exception or interrupt occurs while performing steps 1 to 5, you do not change the values of these registers in the exception handling routine. Do not read from or write to BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, and BRCR registers while the UBC clock is stopped. If the registers are read from or written to, the value cannot be guaranteed. 31.7.2 Cancelling the User Break Controller Stopped State
The clock supply can be restarted by setting bit MSTP5 of STBCR2 (inside the CPG) to 0. The user break controller can then be operated again. Follow steps 1 and 2 below to clear bit MSTP5 to 0 to cancel the stopped state. 1. Read STBCR2, then clear bit MSTP5 in the read data to 0 and write the modified data back; 2. Make two dummy reads of STBGR2. As with the transition to the stopped state, if an exception or interrupt occurs while processing steps 1 and 2, make sure that the values in these registers are not changed in the exception handling routine.
Rev. 1.0, 02/03, page 1113 of 1294
31.7.3
Examples of Stopping and Restarting the User Break Controller
The following are example programs:
; Transition to user break controller stopped state ; (1) Initialize BBRA and BBRB to 0. mov mov.l mov.w mov.l mov.w #0, R0 #BBRA, R1 R0, @R1 #BBRB, R1 R0, @R1
; (2) Initialize BRCR to 0. mov.l mov.w #BRCR, R1 R0, @R1
; (3) Dummy read BRCR. mov.w @R1, R0
; (4) Read STBCR2, then set bit MSTP5 in the read data to 1 and write it back mov.l mov.b or mov.b #STBCR2, R1 @R1, R0 #H'1, R0 R0, @R1
; (5) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0
; Canceling user break controller stopped state ; (6) Read STBCR2, then clear bit MSTP5 in the read data to 0 and write it back mov.l mov.b and mov.b #STBCR2, R1 @R1, R0 #H'FE, R0 R0, @R1
; (7) Twice dummy read STBCR2. mov.b mov.b @R1, R0 @R1, R0
Rev. 1.0, 02/03, page 1114 of 1294
Section 32 List of Registers
This section gives information on the on-chip I/O registers and is configured as described below. 1. Register Addresses (by functional module, in order of the corresponding section numbers) * Descriptions by functional module, in order of the corresponding section numbers Entries that consist of lines are for separation of the functional modules. * Access to reserved addresses which are not described in this list is prohibited. * When registers consist of 16 or 32 bits, the addresses of the MSBs are given, on the presumption of a big-endian system. 2. Register Bits * Bit configurations of the registers are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * Reserved bits are indicated by in the bit name. * No entry in the bit-name column indicates that the whole register is allocated as a counter or for holding data. * When registers consist of 16 or 32 bits, bits are described from the MSB side. The order in which bytes are described is on the presumption of a big-endian system. 3. Register States in Each Operating Mode * Register states are described in the same order as the Register Addresses (by functional module, in order of the corresponding section numbers). * For the initial state of each bit, refer to the description of the register in the corresponding section. * The register states described are for the basic operating modes. If there is a specific reset for an on-chip module, refer to the section on that on-chip module.
Rev. 1.0, 02/03, page 1115 of 1294
32.1
Register Addresses
(by functional module, in order of the corresponding section numbers)
Entries under Access size indicates numbers of bits. Note: Access to undefined or reserved addresses is prohibited. Since operation or continued operation is not guaranteed when these registers are accessed, do not attempt such access.
P4 Module
MMU
Area 7 Address
H'1F00 0000 H'1F00 0004 H'1F00 0034 H'1F00 0008 H'1F00 000C H'1F00 0010 H'1F00 001C H'1F00 0038 H'1F00 003C H'1F00 0020 H'1F00 0024 H'1F00 0028 H'1FD0 0000 H'1FD0 0004 H'1FD0 0008 H'1FD0 000C H'1FD0 0010 H'1E08 0000 H'1E08 0004 H'1E08 0008 H'1E08 000C H'1E08 0020 H'1E08 0024 H'1E08 0040
Sync Size
32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 32 32 32 32 32 32 32
Register Name
Page table entry high register Page table entry low register Page table entry assistance register Translation table base register TLB exception address register MMU control register
Abbrev.
PTEH PTEL PTEA TTB TEA MMUCR CCR QACR0 QACR1 TRA EXPEVT INTEVT ICR IPRA IPRB IPRC IPRD INTPRI00 INTPRI04 INTPRI08 INTPRI0C INTREQ00 INTREQ04 INTMSK00
Address
H'FF00 0000 H'FF00 0004 H'FF00 0034 H'FF00 0008 H'FF00 000C H'FF00 0010 H'FF00 001C H'FF00 0038 H'FF00 003C H'FF00 0020 H'FF00 0024 H'FF00 0028 H'FFD0 0000 H'FFD0 0004 H'FFD0 0008 H'FFD0 000C H'FFD0 0010 H'FE08 0000 H'FE08 0004 H'FE08 0008 H'FE08 000C H'FE08 0020 H'FE08 0024 H'FE08 0040
Clock
Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Cache
Cache control register Queue address control register 0 Queue address control register 1
Exception TRAPA exception register handling Exception event register Interrupt event register INTC Interrupt control register Interrupt priority level setting register A Interrupt priority level setting register B Interrupt priority level setting register C Interrupt priority level setting register D Interrupt priority level setting register 00 Interrupt priority level setting register 04 Interrupt priority level setting register 08 Interrupt priority level setting register 0C Interrupt source register 00 Interrupt source register 04 Interrupt mask register 00
Rev. 1.0, 02/03, page 1116 of 1294
P4 Module
INTC
Area 7 Address
H'1E08 0044 H'1E08 0060 H'1E08 0064 H'1F80 0000 H'1F80 0004 H'1F80 0050 H'1E0A 00F0 H'1F80 0008 H'1F80 000C H'1F80 0010 H'1E0A 0028 H'1F80 0014 H'1F80 0018 H'1F80 001C H'1F80 0020 H'1F80 0024 H'1F80 0028
1
Sync Size
32 32 32 32 16 16 32 32 32 32 32 32 16 16 16 16 16 8 8 32 32 32 32 32 32 32 32 32 32 32 32
Register Name
Interrupt mask register 04 Interrupt mask clear register 00 Interrupt mask clear register 04
Abbrev.
INTMSK04 INTMSKCLR00 INTMSKCLR04 BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 WCR4 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR2 SDMR3 SAR0 DAR0 DMATCR0 CHCR0 SAR1 DAR1 DMATCR1 CHCR1 SAR2 DAR2 DMATCR2 CHCR2
Address
H'FE08 0044 H'FE08 0060 H'FE08 0064 H'FF80 0000 H'FF80 0004 H'FF80 0050 H'FE0A 00F0 H'FF80 0008 H'FF80 000C H'FF80 0010 H'FE0A 0028 H'FF80 0014 H'FF80 0018 H'FF80 001C H'FF80 0020 H'FF80 0024 H'FF80 0028 H'FF90 xxxx*
Clock
Pck Pck Pck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck
BSC
Bus control register 1 Bus control register 2 Bus control register 3 Bus control register 4 Wait control register 1 Wait control register 2 Wait control register 3 Wait control register 4 Memory control register PCMCIA control register Refresh timer control/status register Refresh timer counter Refresh time constant register Refresh count register Synchronous DRAM mode register (for Area 2) Synchronous DRAM mode register (for Area 3)
H'1F90 xxxx H'1F94 xxxx H'1FA0 0000 H'1FA0 0004 H'1FA0 0008 H'1FA0 000C H'1FA0 0010 H'1FA0 0014 H'1FA0 0018 H'1FA0 001C H'1FA0 0020 H'1FA0 0024 H'1FA0 0028 H'1FA0 002C
H'FF94 xxxx* H'FFA0 0000 H'FFA0 0004 H'FFA0 0008
1
DMAC Channel 0
DMA source address register 0 DMA destination address register 0 DMA transfer count register 0 DMA channel control register 0
H'FFA0 000C H'FFA0 0010 H'FFA0 0014 H'FFA0 0018 H'FFA0 001C H'FFA0 0020 H'FFA0 0024 H'FFA0 0028 H'FFA0 002C
DMAC Channel 1
DMA source address register 1 DMA destination address register 1 DMA transfer count register 1 DMA channel control register 1
DMAC Channel 2
DMA source address register 2 DMA destination address register 2 DMA transfer count register 2 DMA channel control register 2
Rev. 1.0, 02/03, page 1117 of 1294
P4 Module
DMAC Channel 3
Area 7 Address
H'1FA0 0030 H'1FA0 0034 H'1FA0 0038 H'1FA0 003C H'1FA0 0050 H'1FA0 0054 H'1FA0 0058 H'1FA0 005C H'1FA0 0060 H'1FA0 0064 H'1FA0 0068 H'1FA0 006C H'1FA0 0070 H'1FA0 0074 H'1FA0 0078 H'1FA0 007C H'1FA0 0080 H'1FA0 0084 H'1FA0 0088 H'1FA0 008C H'1FA0 0040 H'1E09 0000 H'1E09 0004 H'1E09 0008 H'1E3C 0000 H'1E3C 0040 H'1E3C 0044
Sync Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Register Name
DMA source address register 3 DMA destination address register 3 DMA transfer count register 3 DMA channel control register 3
Abbrev.
SAR3 DAR3 DMATCR3 CHCR3 SAR4 DAR4 DMATCR4 CHCR4 SAR5 DAR5 DMATCR5 CHCR5 SAR6 DAR6 DMATCR6 CHCR6 SAR7 DAR7 DMATCR7 CHCR7 DMAOR DMARSRA DMARSRB DMARCR DMABRGCR DMAATXSAR0 DMAARXDAR0
Address
H'FFA0 0030 H'FFA0 0034 H'FFA0 0038 H'FFA0 003C H'FFA0 0050 H'FFA0 0054 H'FFA0 0058 H'FFA0 005C H'FFA0 0060 H'FFA0 0064 H'FFA0 0068 H'FFA0 006C H'FFA0 0070 H'FFA0 0074 H'FFA0 0078 H'FFA0 007C H'FFA0 0080 H'FFA0 0084 H'FFA0 0088 H'FFA0 008C H'FFA0 0040 H'FE09 0000 H'FE09 0004 H'FE09 0008 H'FE3C 0000 H'FE3C 0040 H'FE3C 0044
Clock
Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Bck Pck Pck Pck Pck Pck Pck
DMAC Channel 4
DMA source address register 4 DMA destination address register 4 DMA transfer count register 4 DMA channel control register 4
DMAC Channel 5
DMA source address register 5 DMA destination address register 5 DMA transfer count register 5 DMA channel control register 5
DMAC Channel 6
DMA source address register 6 DMA destination address register 6 DMA transfer count register 6 DMA channel control register 6
DMAC Channel 7
DMA source address register 7 DMA destination address register 7 DMA transfer count register 7 DMA channel control register 7
DMAC common
DMA operation register DMA request resource selection register A DMA request resource selection register B
DMAC DMABRG
DMA request control register DMA BRG control register DMA audio source address register 0 DMA audio destination address register 0
DMA audio transmit transfer count register 0 DMAATXTCR0 H'FE3C 0048 DMA audio receive transfer count register 0 DMA audio control register 0 DMAARXTCR0 H'FE3C 004C DMAACR0 H'FE3C 0050
H'1E3C 0048 H'1E3C 004C H'1E3C 0050 H'1E3C 0054 H'1E3C 0058
32 32 32 32 32
Pck Pck Pck Pck Pck
DMA audio transmit transfer count register 0 DMAATXTCNT0 H'FE3C 0054 DMA audio receive transfer count register 0 DMAARXTCNT0 H'FE3C 0058
Rev. 1.0, 02/03, page 1118 of 1294
P4 Module DMAC DMABRG Register Name DMA audio source address register 1 DMA audio destination address register 1 Abbrev. Address
Area 7 Address H'1E3C 0060 H'1E3C 0064 H'1E3C 0068 H'1E3C 006C H'1E3C 0070 H'1E3C 0074 H'1E3C 0078 H'1E3C 0080 H'1E3C 0084 H'1E3C 0088 H'1E3C 008C H'1FC0 0000 H'1E0A 0020 H'1E0A 0024 H'1FC0 0008 H'1FC0 000C H'1FC0 0004 H'1FC0 0010 H'1E0A 0000 H'1E0A 0010 H'1FD8 0004 Size 32 32 32 32 32 32 32 32 32 32 32 16 32 32 8/16* 8/16* 8 8 32 32 8
2
Sync Clock Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
DMAATXSAR1 H'FE3C 0060 DMAARXDAR1 H'FE3C 0064 H'FE3C 0068
DMA audio transmit transfer count register 1 DMAATXTCR1
DMA audio receive transfer count register 1 DMAARXTCR1 H'FE3C 006C DMA audio control register 1 DMAACR1 H'FE3C 0070
DMA audio transmit transfer count register 1 DMAATXTCNT1 H'FE3C 0074 DMA audio receive transfer count register 1 DMAARXTCNT1 H'FE3C 0078 DAM USB source address register DMA USB destination address register DMA USB R/W size register DMA USB control register CPG Frequency control register Clock division register Module clock control register WDT Watchdog timer counter Watchdog timer control/status register Power-down Standby control register Standby control register 2 Clock stop register 00 Clock stop clear register 00 TMU common TMU Channel 0 Timer constant register 0 Timer counter 0 Timer control register 0 TMU Channel 1 Timer constant register 1 Timer counter 1 Timer control register 1 TMU Channel 2 Timer constant register 2 Timer counter 2 Timer control register 2 Input capture register 2 TCOR0 TCNT0 TCR0 TCOR1 TCNT1 TCR1 TCOR2 TCNT2 TCR2 TCPR2 H'FFD8 0008 H'FFD8 000C H'FFD8 0010 H'FFD8 0014 H'FFD8 0018 H'FFD8 001C H'FFD8 0020 H'FFD8 0024 H'FFD8 0028 H'FFD8 002C Timer start register DMAUSAR DMAUDAR DMAURWSZ DMAUCR FRQCR DCKDR MCKCR WTCNT WTCSR STBCR STBCR2 CLKSTP00 H'FE3C 0080 H'FE3C 0084 H'FE3C 0088 H'FE3C 008C H'FFC0 0000 H'FE0A 0020 H'FE0A 0024 H'FFC0 0008 H'FFC0 000C H'FFC0 0004 H'FFC0 0010 H'FE0A 0000
2
CLKSTPCLR00 H'FE0A 0010 TSTR H'FFD8 0004
H'1FD8 0008 H'1FD8 000C H'1FD8 0010 H'1FD8 0014 H'1FD8 0018 H'1FD8 001C H'1FD8 0020 H'1FD8 0024 H'1FD8 0028 H'1FD8 002C
32 32 16 32 32 16 32 32 16 32
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1119 of 1294
P4 Module
CMT common
Area 7 Address
H'1E1C 0000 H'1E1C 0004 H'1E1C 0008 H'1E1C 000C H'1E1C 0010 H'1E1C 0020 H'1E1C 0030 H'1E1C 0014 H'1E1C 0024 H'1E1C 0034 H'1E1C 0018 H'1E1C 0028 H'1E1C 0038 H'1E1C 001C H'1E1C 002C H'1E1C 003C H'1E60 0000 H'1E60 0004 H'1E60 0008 H'1E60 000C H'1E60 0010 H'1E60 0014 H'1E60 0018 H'1E60 001C H'1E60 0020 H'1E60 0024 H'1E60 0028 H'1E60 002C H'1E61 0000 H'1E61 0004 H'1E61 0008 H'1E61 000C
Sync Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 8 16 8 16 8 16 16 16 16 16 16 16 8 16 8
Register Name
Configuration register Free-running timer Control register IRQ status register
Abbrev.
CMTCFG CMTFRT CMTCTL CMTIRQS CMTCH0T CMTCH0ST CMTCH0C CMTCH1T CMTCH1ST CMTCH1C CMTCH2T CMTCH2ST CMTCH2C CMTCH3T CMTCH3ST CMTCH3C SCSMR0 SCBRR0 SCSCR0 SCFTDR0 SCFSR0 SCFRDR0 SCFCR0 SCTFDR0 SCRFDR0 SCSPTR0 SCLSR0 SCRER0 SCSMR1 SCBRR1 SCSCR1 SCFTDR1
Address
H'FE1C 0000 H'FE1C 0004 H'FE1C 0008 H'FE1C 000C H'FE1C 0010 H'FE1C 0020 H'FE1C 0030 H'FE1C 0014 H'FE1C 0024 H'FE1C 0034 H'FE1C 0018 H'FE1C 0028 H'FE1C 0038 H'FE1C 001C H'FE1C 002C H'FE1C 003C H'FE60 0000 H'FE60 0004 H'FE60 0008 H'FE60 000C H'FE60 0010 H'FE60 0014 H'FE60 0018 H'FE60 001C H'FE60 0020 H'FE60 0024 H'FE60 0028 H'FE60 002C H'FE61 0000 H'FE61 0004 H'FE61 0008 H'FE61 000C
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
CMT Channel 0
Channel 0 time register Channel 0 stop time register Channel 0 timer/counter
CMT Channel 1
Channel 1 time register Channel 1 stop time register Channel 1 timer/counter
CMT Channel 2
Channel 2 time register Channel 2 stop time register Channel 2 timer/counter
CMT Channel 3
Channel 3 time register Channel 3 stop time register Channel 3 timer/counter
SCIF Channel 0
Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit FIFO data register 0 Serial status register 0 Receive FIFO data register 0 FIFO control register 0 Transmit FIFO data count register 0 Receive FIFO data count register 0 Serial port register 0 Line status register 0 Serial error register 0
SCIF Channel 1
Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit FIFO data register 1
Rev. 1.0, 02/03, page 1120 of 1294
P4 Module
SCIF Channel 1
Area 7 Address
H'1E61 0010 H'1E61 0014 H'1E61 0018 H'1E61 001C H'1E61 0020 H'1E61 0024 H'1E61 0028 H'1E61 002C H'1E62 0000 H'1E62 0004 H'1E62 0008 H'1E62 000C H'1E62 0010 H'1E62 0014 H'1E62 0018 H'1E62 001C H'1E62 0020 H'1E62 0024 H'1E62 0028 H'1E62 002C H'1E48 0000 H'1E48 0002 H'1E48 0004 H'1E48 0006 H'1E48 0008 H'1E48 000A H'1E48 000C H'1E48 000E H'1E48 0010 H'1E48 0012 H'1E48 0014
Sync Size
16 8 16 16 16 16 16 16 16 8 16 8 16 8 16 16 16 16 16 16 8 8 8 8 8 8 8 8 16 8 16
Register Name
Serial status register 1 Receive FIFO data register 1 FIFO control register 1 Transmit FIFO data count register 1 Receive FIFO data count register 1 Serial port register 1 Line status register 1 Serial error register 1
Abbrev.
SCFSR1 SCFRDR1 SCFCR1 SCTFDR1 SCRFDR1 SCSPTR1 SCLSR1 SCRER1 SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCFSR2 SCFRDR2 SCFCR2 SCTFDR2 SCRFDR2 SCSPTR2 SCLSR2 SCRER2 SISMR SIBRR SISCR SITDR SISSR SIRDR SISCMR SISC2R SIWAIT SIGRD SISMPL
Address
H'FE61 0010 H'FE61 0014 H'FE61 0018 H'FE61 001C H'FE61 0020 H'FE61 0024 H'FE61 0028 H'FE61 002C H'FE62 0000 H'FE62 0004 H'FE62 0008 H'FE62 000C H'FE62 0010 H'FE62 0014 H'FE62 0018 H'FE62 001C H'FE62 0020 H'FE62 0024 H'FE62 0028 H'FE62 002C H'FE48 0000 H'FE48 0002 H'FE48 0004 H'FE48 0006 H'FE48 0008 H'FE48 000A H'FE48 000C H'FE48 000E H'FE48 0010 H'FE48 0012 H'FE48 0014
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
SCIF Channel.2
Serial mode register 2 Bit rate register 2 Serial control register 2 Transmit FIFO data register 2 Serial status register 2 Receive FIFO data register 2 FIFO control register 2 Transmit FIFO data count register 2 Receive FIFO data count register 2 Serial port register 2 Line status register 2 Serial error register 2
SIM
Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Serial control 2 register Wait time register Guard extension register Sampling register
Rev. 1.0, 02/03, page 1121 of 1294
P4 Module
IC Channel 0
2
Area 7 Address
H'1E14 0000 H'1E14 0004 H'1E14 0008 H'1E14 000C H'1E14 0010 H'1E14 0014 H'1E14 0018 H'1E14 001C H'1E14 0020 H'1E14 0024 H'1E14 0024 H'1E14 0028 H'1E14 002C H'1E14 0030 H'1E14 0034 H'1E14 0038 H'1E15 0000 H'1E15 0004 H'1E15 0008 H'1E15 000C H'1E15 0010 H'1E15 0014 H'1E15 0018 H'1E15 001C H'1E15 0020 H'1E15 0024 H'1E15 0024 H'1E15 0028 H'1E15 002C H'1E15 0030 H'1E15 0034 H'1E15 0038
Sync Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Register Name
Slave control register 0 Master control register 0 Slave status register 0 Master status register 0 Slave interrupt enable register 0 Master interrupt enable register 0 Clock control register 0 Slave address enable register 0 Master address enable register 0 Receive data register 0 Transmit data register 0 FIFO control register 0 FIFO status register 0 FIFO interrupt enable register 0 Receive FIFO data count register 0 Transmit FIFO data count register 0
Abbrev.
ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 ICMIER0 ICCCR0 ICSAR0 ICMAR0 ICRXD0 ICTXD0 ICFCR0 ICFSR0 ICFIER0 ICRFDR0 ICTFDR0 ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1 ICMIER1 ICCCR1 ICSAR1 ICMAR1 ICRXD1 ICTXD1 ICFCR1 ICFSR1 ICFIER1 ICRFDR1 ICTFDR1
Address
H'FE14 0000 H'FE14 0004 H'FE14 0008 H'FE14 000C H'FE14 0010 H'FE14 0014 H'FE14 0018 H'FE14 001C H'FE14 0020 H'FE14 0024 H'FE14 0024 H'FE14 0028 H'FE14 002C H'FE14 0030 H'FE14 0034 H'FE14 0038 H'FE15 0000 H'FE15 0004 H'FE15 0008 H'FE15 000C H'FE15 0010 H'FE15 0014 H'FE15 0018 H'FE15 001C H'FE15 0020 H'FE15 0024 H'FE15 0024 H'FE15 0028 H'FE15 002C H'FE15 0030 H'FE15 0034 H'FE15 0038
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
IC Channel 1
2
Slave control register 1 Master control register 1 Slave status register 1 Master status register 1 Slave interrupt enable register 1 Master interrupt enable register 1 Clock control register 1 Slave address enable register 1 Master address enable register 1 Receive data register 1 Transmit data register 1 FIFO control register 1 FIFO status register 1 FIFO interrupt enable register 1 Receive FIFO data count register 1 Transmit FIFO data count register 1
Rev. 1.0, 02/03, page 1122 of 1294
P4 Module
SSI Channel 0
Area 7 Address
H'1E68 0000 H'1E68 0004 H'1E68 0008 H'1E68 000C H'1E69 0000 H'1E69 0004 H'1E69 0008 H'1E69 000C H'1E34 0000 H'1E34 0004 H'1E34 0008 H'1E34 000C H'1E34 0010 H'1E34 0014 H'1E34 0018
Sync Size
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Register Name
Control register 0 Status register 0 Transmit data register 0 Receive data register 0
Abbrev.
SSICR0 SSISR0 SSITDR0 SSIRDR0 SSICR1 SSISR1 SSITDR1 SSIRDR1 HcRevision HcControl
Address
H'FE68 0000 H'FE68 0004 H'FE68 0008 H'FE68 000C H'FE69 0000 H'FE69 0004 H'FE69 0008 H'FE69 000C H'FE34 0000 H'FE34 0004
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
SSI Channel 1
Control register 1 Status register 1 Transmit data register 1 Receive data register 1
USB
Host controller interface revision register Control register Command status register Interrupt status register Interrupt enable register Interrupt disable register Host controller communication area pointer register Period current ED pointer register Control head ED pointer register Control current ED pointer register Bulk head ED pointer register Bulk current ED pointer register Done queue head pointer register Frame interval register Frame remaining register Frame number register Periodic start register Low speed threshold register Root hub descriptor A register Root hub descriptor B register Root hub status register Root hub port status 1 register
HcCommandStatus H'FE34 0008 HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA H'FE34 000C H'FE34 0010 H'FE34 0014 H'FE34 0018
HcPeriodCurrentED H'FE34 001C HcControlHeadED H'FE34 0020
H'1E34 001C H'1E34 0020 H'1E34 0024 H'1E34 0028 H'1E34 002C H'1E34 0030 H'1E34 0034 H'1E34 0038 H'1E34 003C H'1E34 0040 H'1E34 0044 H'1E34 0048 H'1E34 004C H'1E34 0050 H'1E34 0054
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
HcControlCurrentED H'FE34 0024 HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 H'FE34 0028 H'FE34 002C H'FE34 0030 H'FE34 0034 H'FE34 0038 H'FE34 003C H'FE34 0040 H'FE34 0044 H'FE34 0048 H'FE34 004C H'FE34 0050 H'FE34 0054
Rev. 1.0, 02/03, page 1123 of 1294
P4 Module
USB
Area 7 Address
H'1E34 1000
Sync Size
32
Register Name
Abbrev.
Shared memory area Start Shared memory area End
Address
H'FE34 1000
Clock
Pck
H'FE34 2FFF
H'1E34 2FFF
32
Pck
HCAN2 Channel 0
Master control register General status register Bit configuration register 1 Bit configuration register 0 Interrupt request register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0 Receive data frame pending register 1 Receive data frame pending register 0 Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register Timer control register Timer compare match register
CAN0MCR CAN0GSR CAN0BCR1 CAN0BCR0 CAN0IRR CAN0IMR CAN0TECREC CAN0TXPR1 CAN0TXPR0 CAN0TXCR1 CAN0TXCR0 CAN0TXACK1 CAN0TXACK0 CAN0ABACK1 CAN0ABACK0 CAN0RXPR1 CAN0RXPR0 CAN0RFPR1 CAN0RFPR0 CAN0MBIMR1 CAN0MBIMR0 CAN0UMSR1 CAN0UMSR0 CAN0TCNTR CAN0TCR CAN0TCMR
H'FE38 0000 H'FE38 0002 H'FE38 0004 H'FE38 0006 H'FE38 0008 H'FE38 000A H'FE38 000C H'FE38 0020 H'FE38 0022 H'FE38 0028 H'FE38 002A H'FE38 0030 H'FE38 0032 H'FE38 0038 H'FE38 003A H'FE38 0040 H'FE38 0042 H'FE38 0048 H'FE38 004A H'FE38 0050 H'FE38 0052 H'FE38 0058 H'FE38 005A H'FE38 0080 H'FE38 0082 H'FE38 0090
H'1E38 0000 H'1E38 0002 H'1E38 0004 H'1E38 0006 H'1E38 0008 H'1E38 000A H'1E38 000C H'1E38 0020 H'1E38 0022 H'1E38 0028 H'1E38 002A H'1E38 0030 H'1E38 0032 H'1E38 0038 H'1E38 003A H'1E38 0040 H'1E38 0042 H'1E38 0048 H'1E38 004A H'1E38 0050 H'1E38 0052 H'1E38 0058 H'1E38 005A H'1E38 0080 H'1E38 0082 H'1E38 0090
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1124 of 1294
P4 Module
HCAN2 Channel 0
Area 7 Address
H'1E38 0100 H'1E38 0120 H'1E38 0140 H'1E38 0160 H'1E38 0180 H'1E38 01A0 H'1E38 01C0 H'1E38 01E0 H'1E38 0200 H'1E38 0220 H'1E38 0240 H'1E38 0260 H'1E38 0280 H'1E38 02A0 H'1E38 02C0 H'1E38 02E0 H'1E38 0300 H'1E38 0320 H'1E38 0340 H'1E38 0360 H'1E38 0380 H'1E38 03A0 H'1E38 03C0 H'1E38 03E0 H'1E38 0400 H'1E38 0420 H'1E38 0440 H'1E38 0460 H'1E38 0480 H'1E38 04A0 H'1E38 04C0 H'1E38 04E0
Sync Size
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Register Name
Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5 Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 12 Mailbox 13 Mailbox 14 Mailbox 15 Mailbox 16 Mailbox 17 Mailbox 18 Mailbox 19 Mailbox 20 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31
Abbrev.
CAN0MB0 CAN0MB1 CAN0MB2 CAN0MB3 CAN0MB4 CAN0MB5 CAN0MB6 CAN0MB7 CAN0MB8 CAN0MB9 CAN0MB10 CAN0MB11 CAN0MB12 CAN0MB13 CAN0MB14 CAN0MB15 CAN0MB16 CAN0MB17 CAN0MB18 CAN0MB19 CAN0MB20 CAN0MB21 CAN0MB22 CAN0MB23 CAN0MB24 CAN0MB25 CAN0MB26 CAN0MB27 CAN0MB28 CAN0MB29 CAN0MB30 CAN0MB31
Address
H'FE38 0100 H'FE38 0120 H'FE38 0140 H'FE38 0160 H'FE38 0180 H'FE38 01A0 H'FE38 01C0 H'FE38 01E0 H'FE38 0200 H'FE38 0220 H'FE38 0240 H'FE38 0260 H'FE38 0280 H'FE38 02A0 H'FE38 02C0 H'FE38 02E0 H'FE38 0300 H'FE38 0320 H'FE38 0340 H'FE38 0360 H'FE38 0380 H'FE38 03A0 H'FE38 03C0 H'FE38 03E0 H'FE38 0400 H'FE38 0420 H'FE38 0440 H'FE38 0460 H'FE38 0480 H'FE38 04A0 H'FE38 04C0 H'FE38 04E0
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1125 of 1294
P4 Module
HCAN2 Channel 1
Area 7 Address
H'1E39 0000 H'1E39 0002 H'1E39 0004 H'1E39 0006 H'1E39 0008 H'1E39 000A H'1E39 000C H'1E39 0020 H'1E39 0022 H'1E39 0028 H'1E39 002A H'1E39 0030 H'1E39 0032 H'1E39 0038 H'1E39 003A H'1E39 0040 H'1E39 0042 H'1E39 0048 H'1E39 004A H'1E39 0050 H'1E39 0052 H'1E39 0058 H'1E39 005A H'1E39 0080 H'1E39 0082 H'1E39 0090 H'1E39 0100 H'1E39 0120 H'1E39 0140 H'1E39 0160 H'1E39 0180 H'1E39 01A0
Sync Size
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Register Name
Master control register General status register Bit configuration register 1 Bit configuration register 0 Interrupt request register Interrupt mask register Error counter Transmit pending request register 1 Transmit pending request register 0 Transmit cancel register 1 Transmit cancel register 0 Transmit acknowledge register 1 Transmit acknowledge register 0 Abort acknowledge register 1 Abort acknowledge register 0 Receive data frame pending register 1 Receive data frame pending register 0 Remote frame request pending register 1 Remote frame request pending register 0 Mailbox interrupt mask register 1 Mailbox interrupt mask register 0 Unread message status register 1 Unread message status register 0 Timer counter register Timer control register Timer compare match register Mailbox 0 Mailbox 1 Mailbox 2 Mailbox 3 Mailbox 4 Mailbox 5
Abbrev.
CAN1MCR CAN1GSR CAN1BCR1 CAN1BCR0 CAN1IRR CAN1IMR CAN1TECREC CAN1TXPR1 CAN1TXPR0 CAN1TXCR1 CAN1TXCR0 CAN1TXACK1 CAN1TXACK0 CAN1ABACK1 CAN1ABACK0 CAN1RXPR1 CAN1RXPR0 CAN1RFPR1 CAN1RFPR0 CAN1MBIMR1 CAN1MBIMR0 CAN1UMSR1 CAN1UMSR0 CAN1TCNTR CAN1TCR CAN1TCMR CAN1MB0 CAN1MB1 CAN1MB2 CAN1MB3 CAN1MB4 CAN1MB5
Address
H'FE39 0000 H'FE39 0002 H'FE39 0004 H'FE39 0006 H'FE39 0008 H'FE39 000A H'FE39 000C H'FE39 0020 H'FE39 0022 H'FE39 0028 H'FE39 002A H'FE39 0030 H'FE39 0032 H'FE39 0038 H'FE39 003A H'FE39 0040 H'FE39 0042 H'FE39 0048 H'FE39 004A H'FE39 0050 H'FE39 0052 H'FE39 0058 H'FE39 005A H'FE39 0080 H'FE39 0082 H'FE39 0090 H'FE39 0100 H'FE39 0120 H'FE39 0140 H'FE39 0160 H'FE39 0180 H'FE39 01A0
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1126 of 1294
P4 Module
HCAN2 Channel 1
Area 7 Address
H'1E39 01C0 H'1E39 01E0 H'1E39 0200 H'1E39 0220 H'1E39 0240 H'1E39 0260 H'1E39 0280 H'1E39 02A0 H'1E39 02C0 H'1E39 02E0 H'1E39 0300 H'1E39 0320 H'1E39 0340 H'1E39 0360 H'1E39 0380 H'1E39 03A0 H'1E39 03C0 H'1E39 03E0 H'1E39 0400 H'1E39 0420 H'1E39 0440 H'1E39 0460 H'1E39 0480 H'1E39 04A0 H'1E39 04C0 H'1E39 04E0
Sync Size
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Register Name
Mailbox 6 Mailbox 7 Mailbox 8 Mailbox 9 Mailbox 10 Mailbox 11 Mailbox 12 Mailbox 13 Mailbox 14 Mailbox 15 Mailbox 16 Mailbox 17 Mailbox 18 Mailbox 19 Mailbox 20 Mailbox 21 Mailbox 22 Mailbox 23 Mailbox 24 Mailbox 25 Mailbox 26 Mailbox 27 Mailbox 28 Mailbox 29 Mailbox 30 Mailbox 31
Abbrev.
CAN1MB6 CAN1MB7 CAN1MB8 CAN1MB9 CAN1MB10 CAN1MB11 CAN1MB12 CAN1MB13 CAN1MB14 CAN1MB15 CAN1MB16 CAN1MB17 CAN1MB18 CAN1MB19 CAN1MB20 CAN1MB21 CAN1MB22 CAN1MB23 CAN1MB24 CAN1MB25 CAN1MB26 CAN1MB27 CAN1MB28 CAN1MB29 CAN1MB30 CAN1MB31
Address
H'FE39 01C0 H'FE39 01E0 H'FE39 0200 H'FE39 0220 H'FE39 0240 H'FE39 0260 H'FE39 0280 H'FE39 02A0 H'FE39 02C0 H'FE39 02E0 H'FE39 0300 H'FE39 0320 H'FE39 0340 H'FE39 0360 H'FE39 0380 H'FE39 03A0 H'FE39 03C0 H'FE39 03E0 H'FE39 0400 H'FE39 0420 H'FE39 0440 H'FE39 0460 H'FE39 0480 H'FE39 04A0 H'FE39 04C0 H'FE39 04E0
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1127 of 1294
P4 Module
HSPI
Area 7 Address
H'1E18 0000 H'1E18 0004 H'1E18 0008 H'1E18 000C H'1E18 0010 H'1E40 0028 H'1E40 002C H'1E40 0030 H'1E40 0034 H'1E40 0080 H'1E40 0084 H'1E40 0088 H'1E40 008C H'1E40 0090 H'1E40 0094 H'1E40 0098 H'1E40 009C H'1E40 00A0 H'1E40 00A4 H'1E40 00A8 H'1E40 00AC
Sync Size
32 32 32 32 32 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8
Register Name
Control register Status register System control register Transmit buffer register Receive buffer register
Abbrev.
SPCR SPSR SPSCR SPTBR SPRBR INPUPA DMAPCR SCIHZR IPSELR PAPUPR PBPUPR PCPUPR PDPUPR PEPUPR PFPUPR PGPUPR PHPUPR PJPUPR PKPUPR MDPUPR MODSELR
Address
H'FE18 0000 H'FE18 0004 H'FE18 0008 H'FE18 000C H'FE18 0010 H'FE40 0028 H'FE40 002C H'FE40 0030 H'FE40 0034 H'FE40 0080 H'FE40 0084 H'FE40 0088 H'FE40 008C H'FE40 0090 H'FE40 0094 H'FE40 0098 H'FE40 009C H'FE40 00A0 H'FE40 00A4 H'FE40 00A8 H'FE40 00AC
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
PFC
Input pin pull-up control register DMA pin control register SCIF Hi-Z control register Peripheral module select register Port A pull-up control register Port B pull-up control register Port C pull-up control register Port D pull-up control register Port E pull-up control register Port F pull-up control register Port G pull-up control register Port H pull-up control register Port J pull-up control register Port K pull-up control register Mode pin pull-up control register Mode select register
Port A control register Port B control register Port C control register Port D control register Port E control register Port F control register Port G control register Port H control register Port J control register Port K control register
PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR
H'FE40 0000 H'FE40 0004 H'FE40 0008 H'FE40 000C H'FE40 0010 H'FE40 0014 H'FE40 0018 H'FE40 001C H'FE40 0020 H'FE40 0024
H'1E40 0000 H'1E40 0004 H'1E40 0008 H'1E40 000C H'1E40 0010 H'1E40 0014 H'1E40 0018 H'1E40 001C H'1E40 0020 H'1E40 0024
16 16 16 16 16 16 16 16 16 16
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1128 of 1294
Module
PFC
Register Name
Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port G data register Port H data register Port J data register Port K data register GPIO interrupt control register
Abbrev.
PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR GPIOIC
P4 Address
H'FE40 0040 H'FE40 0044 H'FE40 0048 H'FE40 004C H'FE40 0050 H'FE40 0054 H'FE40 0058 H'FE40 005C H'FE40 0060 H'FE40 0064 H'FF80 0048
Area 7 Address Size
H'1E40 0040 H'1E40 0044 H'1E40 0048 H'1E40 004C H'1E40 0050 H'1E40 0054 H'1E40 0058 H'1E40 005C H'1E40 0060 H'1E40 0064 H'1F80 0048 8 8 8 8 8 8 8 8 8 8 16
Sync Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Bck
HAC Channel 0
Control and status register 0 Command/status address register 0 Command/status data register 0 PCM left channel register 0 PCM right channel register 0 TX interrupt enable register 0 TX status register 0
HACCR0 HACCSAR0
H'FE24 0008 H'FE24 0020
H'1E24 0008 H'1E24 0020
32 32
Pck Pck
HACCSDR0
H'FE24 0024
H'1E24 0024
32
Pck
HACPCML0 HACPCMR0 HACTIER0 HACTSR0
H'FE24 0028 H'FE24 002C H'FE24 0050 H'FE24 0054 H'FE24 0058 H'FE24 005C H'FE24 0060 H'FE25 0008 H'FE25 0020
H'1E24 0028 H'1E24 002C H'1E24 0050 H'1E24 0054 H'1E24 0058 H'1E24 005C H'1E24 0060 H'1E25 0008 H'1E25 0020
32 32 32 32 32 32 32 32 32
Pck Pck Pck Pck Pck Pck Pck Pck Pck
RX interrupt enable register 0 HACRIER0 RX status register 0 HAC control register 0 HAC Channel 1 Control and status register 1 Command/status address register 1 Command/status data register 1 HACCSDR1 PCM left channel register 1 PCM right channel register 1 TX interrupt enable register 1 TX status register 1 HACPCML1 HACPCMR1 HACTIER1 HACTSR1 HACRSR0 HACACR0 HACCR1 HACCSAR1
H'FE25 0024 H'FE25 0028 H'FE25 002C H'FE25 0050 H'FE25 0054 H'FE25 0058 H'FE25 005C H'FE25 0060
H'1E25 0024 H'1E25 0028 H'1E25 002C H'1E25 0050 H'1E25 0054 H'1E25 0058 H'1E25 005C H'1E25 0060
32 32 32 32 32 32 32 32
Pck Pck Pck Pck Pck Pck Pck Pck
RX interrupt enable register 1 HACRIER1 RX status register 1 HAC control register 1 HACRSR1 HACACR1
Rev. 1.0, 02/03, page 1129 of 1294
P4 Module
MMCIF
Area 7 Address
H'1E50 0000 H'1E50 0001 H'1E50 0002 H'1E50 0003 H'1E50 0004 H'1E50 0005 H'1E50 0006 H'1E50 000A H'1E50 000B H'1E50 000C H'1E50 000D H'1E50 000E H'1E50 000F H'1E50 0010 H'1E50 0011 H'1E50 0014 H'1E50 0016 H'1E50 0018 H'1E50 0019 H'1E50 0020 H'1E50 0021 H'1E50 0022 H'1E50 0023 H'1E50 0024 H'1E50 0025 H'1E50 0026 H'1E50 0027 H'1E50 0028 H'1E50 0029 H'1E50 002A H'1E50 002B H'1E50 002C H'1E50 002D
Sync Size
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Register Name
Command register 0 Command register 1 Command register 2 Command register 3 Command register 4 Command register 5 Command start register Operation control register Card status register Interrupt control register 0 Interrupt control register 1 Interrupt status register 0 Interrupt status register 1 Transfer clock control register Command timeout control register Transfer byte number count register Mode register Command type register Response type register Response register 0 Response register 1 Response register 2 Response register 3 Response register 4 Response register 5 Response register 6 Response register 7 Response register 8 Response register 9 Response register 10 Response register 11 Response register 12 Response register 13
Abbrev.
CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR TBCR MODER CMDTYR RSPTYR RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13
Address
H'FE50 0000 H'FE50 0001 H'FE50 0002 H'FE50 0003 H'FE50 0004 H'FE50 0005 H'FE50 0006 H'FE50 000A H'FE50 000B H'FE50 000C H'FE50 000D H'FE50 000E H'FE50 000F H'FE50 0010 H'FE50 0011 H'FE50 0014 H'FE50 0016 H'FE50 0018 H'FE50 0019 H'FE50 0020 H'FE50 0021 H'FE50 0022 H'FE50 0023 H'FE50 0024 H'FE50 0025 H'FE50 0026 H'FE50 0027 H'FE50 0028 H'FE50 0029 H'FE50 002A H'FE50 002B H'FE50 002C H'FE50 002D
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
Rev. 1.0, 02/03, page 1130 of 1294
P4 Module
MMCIF
Area 7 Address
H'1E50 002E H'1E50 002F H'1E50 0030 H'1E50 0032 H'1E50 0040 H'1E50 0042 H'1E50 0044 H'1E50 0046 H'1E50 0048 H'1E50 004A H'1E2C 0000 H'1E2C 0004 H'1E2C 0008 H'1E2C 000C H'1E2C 0010 H'1E2C 0014 H'1E2C 0018 H'1E2C 001C H'1E2E 0000 H'1E2E 07FF H'1FF0 0000 H'1FF0 0008 H'1FF0 000A H'1FF0 0014 H'1E28 0000 H'1E28 0002 H'1E28 0004 H'1E28 0006 H'1E28 0008 H'1E30 0C00 H'1E30 0C02
Sync Size
8 8 8 16 16 8 8 8 8 8 32 32 32 32 32 32 32 32 32 32 16 32/16 16 16 16 16 16 16 16 16 16
Register Name
Response register 14 Response register 15 Response register 16 Data timeout register Data register FIFO pointer clear register DMA control register Interrupt control register 2 Interrupt status register 2 Receive data timing select register
Abbrev.
RSPR14 RSPR15 RSPR16 DTOUTR DR FIFOCLR DMACR INTCR2 INTSTR2 RDTIMSEL MFIIDX MFIGSR MFISCR MFIMCR MFIIICR MFIEICR MFIADR MFIDATA MFRAM Start MFRAM End
Address
H'FE50 002E H'FE50 002F H'FE50 0030 H'FE50 0032 H'FE50 0040 H'FE50 0042 H'FE50 0044 H'FE50 0046 H'FE50 0048 H'FE50 004A H'FE2C 0000 H'FE2C 0004 H'FE2C 0008 H'FE2C 000C H'FE2C 0010 H'FE2C 0014 H'FE2C 0018 H'FE2C 001C H'FE2E 0000 H'FE2E 07FF H'FFF0 0000 H'FFF0 0008 H'FFF0 000A H'FFF0 0014 H'FE28 0000 H'FE28 0002 H'FE28 0004 H'FE28 0006 H'FE28 0008 H'FE30 0C00 H'FE30 0C02
Clock
Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck Pck
MFI
MFI index register MFI general status register MFI status/control register MFI memory control register MFI internal interrupt control register MFI external interrupt control register MFI address register MFI data register
H-UDI
Instruction register Data register H Data register L Interrupt source register Bypass register Boundary scan register
SDIR SDDR/SDDRH SDDRL SDINT SDBPR SDBSR ADDRA ADDRB ADDRC ADDRD ADCSR LDICKR LDMTR
ADC
A/D data register A A/D data register B A/D data register C A/D data register D A/D control/status register
LCDC
LCDC input clock register LCDC module type register
Rev. 1.0, 02/03, page 1131 of 1294
P4 Module
LCDC
Area 7 Address
H'1E30 0C04 H'1E30 0C06 H'1E30 0C08
Sync Size
16 16 32
Register Name
LCDC data format register LCDC scan mode register
Abbrev.
LDDFR LDSMR
Address
H'FE30 0C04 H'FE30 0C06 H'FE30 0C08
Clock
Pck Pck Pck
LCDC data fetch start address register for upper LDSARU display panel LCDC data fetch start address register for lower LDSARL display panel LCDC fetch data line address offset register for display panel LCDC palette control register LCDC palette data register 00 to FF LCDC horizontal character number register LCDC horizontal synchronization signal register LCDC vertical displayed line number register LCDC vertical total line number register LCDC vertical synchronization signal register LCDC AC modulation signal toggle line number register LCDC interrupt control register LCDC power management mode register LCDC power supply sequence period register LCDC control register UBC Break address register A Break ASID register A Break address mask register A Break bus cycle register A Break address register B Break ASID register B Break address mask register B Break bus cycle register B Break data register B Break data mask register B Break control register LDINTR LDPMMR LDPSPR LDCNTR BARA BASRA BAMRA BBRA BARB BASRB BAMRB BBRB BDRB BDMRB BRCR LDPALCR LDPR00 to FF* LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR
3
H'FE30 0C0C
H'1E30 0C0C
32
Pck
LDLAOR
H'FE30 0C10
H'1E30 0C10
16
Pck
H'FE30 0C12 H'FE30 0800 H'FE30 0C14 H'FE30 0C16 H'FE30 0C18 H'FE30 0C1A H'FE30 0C1C H'FE30 0C1E
H'1E30 0C12 H'1E30 0800 H'1E30 0C14 H'1E30 0C16 H'1E30 0C18 H'1E30 0C1A H'1E30 0C1C H'1E30 0C1E
16 32 16 16 16 16 16 16
Pck Pck Pck Pck Pck Pck Pck Pck
H'FE30 0C20 H'FE30 0C24 H'FE30 0C26 H'FE30 0C28 H'FF20 0000 H'FF00 0014 H'FF20 0004 H'FF20 0008 H'FF20 000C H'FF00 0018 H'FF20 0010 H'FF20 0014 H'FF20 0018 H'FF20 001C H'FF20 0020
H'1E30 0C20 H'1E30 0C24 H'1E30 0C26 H'1E30 0C28 H'1F20 0000 H'1F00 0014 H'1F20 0004 H'1F20 0008 H'1F20 000C H'1F00 0018 H'1F20 0010 H'1F20 0014 H'1F20 0018 H'1F20 001C H'1F20 0020
16 16 16 16 32 8 8 16 32 8 8 16 32 32 16
Pck Pck Pck Pck Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick Ick
Note:
1. For details, refer to the description of SDMR2 and SDMR3. 2. Read: Byte access, Write: Word access 3. There are 256 LDPRxx: LDPR00, LDPR01, ..., LDPRFF. The addresses for LDPRxx are H'FE30 0800, H'FE30 0804, ..., H'FE30 0BFC.
Rev. 1.0, 02/03, page 1132 of 1294
32.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Bit 31/ 23/15/7
VPN VPN VPN ASID PTEL PPN PPN SZ1 TTB TTB TTB TTB TTB TEA
Abbrev.
PTEH
Bit 30/ 22/14/6
VPN VPN VPN ASID PPN PPN PR1 TTB TTB TTB TTB
Bit 29/ 21/13/5
VPN VPN VPN ASID PPN PPN PR0 TTB TTB TTB TTB
Bit 28/ 20/12/4
VPN VPN VPN ASID PPN PPN PPN SZ0 TTB TTB TTB TTB
Bit 27/ 19/11/3
VPN VPN VPN ASID PPN PPN PPN C TTB TTB TTB TTB
Bit 26/ 18/10/2
VPN VPN VPN ASID PPN PPN PPN D TTB TTB TTB TTB
Bit 25/ 17/9/ 1
VPN VPN ASID PPN PPN SH TTB TTB TTB TTB
Bit 24/ 16/8/0
VPN VPN ASID PPN PPN V WT TTB TTB TTB TTB
Module
MMU
Virtual address at which MMU exception or address error occurred Virtual address at which MMU exception or address error occurred Virtual address at which MMU exception or address error occurred Virtual address at which MMU exception or address error occurred
MMUCR
LRUI URB URC
LRUI LRB URC
LRUI LRB URC
LRUI LRB URC
LRUI LRB URC TC
LRUI LRB URC TI SA2
SQMD SA1
SV AT SA0
PTEA

Rev. 1.0, 02/03, page 1133 of 1294
Abbrev.
CCR
Bit 31/ 23/15/7
EMODE IIX OIX
Bit 30/ 22/14/6
imm MAI IPR14 IPR6 IPR14 IPR6 IPR14 IPR6 IPR14 IPR6
Bit 29/ 21/13/5
ORA imm IPR13 IPR5 IPR13 IPR5 IPR13 IPR5 IPR13 IPR5
Bit 28/ 20/12/4
AREA0 AREA1 imm IPR12 IPR4 IPR12 IPR4 IPR12 IPR4 IPR12 IPR4
Bit 27/ 19/11/3
ICI OCI AREA0 AREA1 imm IPR11 IPR3 IPR11 IPR3 IPR11 IPR3 IPR11 IPR3
Bit 26/ 18/10/2
CB AREA0 AREA1 imm IPR10 IPR2 IPR10 IPR2 IPR10 IPR2 IPR10 IPR2
Bit 25/ 17/9/ 1
WT imm NMIB IPR9 IPR1 IPR9 IPR1 IPR9 IPR1 IPR9 IPR1
Bit 24/ 16/8/0
ICE OCE imm NMIE IPR8 IPR0 IPR8 IPR0 IPR8 IPR0 IPR8 IPR0
Module
Cache
QACR0

QACR1

TRA
imm
Exception handling
EXPEVT

INTEVT

ICR
NMIL IRLM
INTC
IPRA
IPR15 IPR7
IPRB
IPR15 IPR7
IPRC
IPR15 IPR7
IPRD
IPR15 IPR7
Rev. 1.0, 02/03, page 1134 of 1294
Abbrev.
INTPRI00
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1

Bit 24/ 16/8/0

Module
INTC
INTPRI04

INTPRI08

INTPRI0C

INTREQ00

INTREQ04

INTMSK00

INTMSK04

Rev. 1.0, 02/03, page 1135 of 1294
Abbrev.
INTMSKCLR00
Bit 31/ 23/15/7

Bit 30/ 22/14/6
HIZCNT A6BST1 A0SZ0 A3SZ0
Bit 29/ 21/13/5
A0MPX A1MBC A0BST2 A6BST0 A6SZ1 A2SZ1 A4MPX ASYNC5 DMAIW1 A5IW1 A3IW1 A1IW1 A6W0 A5B1 A3W0 A0W2 A5H1 A3H1 A1H1
Bit 28/ 20/12/4
A4MBC A0BST1
Bit 27/ 19/11/3
BREQEN A0BST0
Bit 26/ 18/10/2
DPUP A5BST2
Bit 25/ 17/9/ 1

Bit 24/ 16/8/0
OPUP
Module
INTC
INTMSKCLR04

BCR1
ENDIAN HIZMEM A6BST2
BSC
MEMMPX DMABST A5BST1 A5BST0 A56PCM A4SZ0 STBIRLEN SDBL ASYNC0 A6IW0 A4IW0 A2IW0 A0IW0 A5W1 A1W2 A0B0 A6H0 A4H0 A2H0 A0H0
DRAMTP2 DRAMTP1 DRAMTP0 A6SZ0 A2SZ0 ASYNC4 DMAIW0 A5IW0 A3IW0 A1IW0 A6B2 A5B0 A0W1 A5H0 A3H0 A1H0 A5SZ1 A1SZ1 ASYNC3 A6B1 A4W2 A2W2 A0W0 A4RDH A5SZ0 A1SZ0 ASYNC2 A6IW2 A4IW2 A2IW2 A0IW2 A6B0 A4W1 A2W1 A0B2 A6S0 A4S0 A2S0 A0S0 A4SZ1 ASYNC1 A6IW1 A4IW1 A2IW1 A0IW1 A5W2 A4W0 A2W0 A0B1 A6H1 A4H1 A2H1 A0H1
BCR2
A0SZ1 A3SZ1
BCR3
MEMMODE A1MPX
BCR4 WCR1 WCR2 A6W2 A5W0 A3W2 A1W1 WCR3 A1RDH
ASYNC6 DMAIW2 A5IW2 A3IW2 A1IW2 A6W1 A5B2 A3W1 A1W0 A5S0 A3S0 A1S0
Rev. 1.0, 02/03, page 1136 of 1294
Abbrev.
WCR4
Bit 31/ 23/15/7

Bit 30/ 22/14/6
MRSET TRWL1 AMXEXT A5PCW0 A6TED0 CMIE A1RXEE A1RXEF
Bit 29/ 21/13/5
TRC2 TPC2 TRWL0 AMX2 A6PCW1 A5TEH2 CKS2 A1TXHE A1TXHF
Bit 28/ 20/12/4
TRC1 TPC1 TRAS2 AMX1 A6PCW0 A5TEH1 CKS1 A1TXEE A1TXEF
Bit 27/ 19/11/3
TRC0 TPC0 TRAS1 AMX0 A5TED2 A5TEH0 CKS0 A0RXHE A0RXHF
Bit 26/ 18/10/2
TRAS0 RFSH A5TED1 A6TEH2 OVF A0RXEE A0RXEF
Bit 25/ 17/9/ 1
CSH1 RCD1 RMODE A5TED0 A6TEH1 OVIE A0TXHE A0TXHF UAE UAF
Bit 24/ 16/8/0
CSH0 RCD0 SZ1 A6TED2 A6TEH0 LMTS A0TXEE A0TXEF UTE UTF
Module
BSC
MCR
RASD TRWL2 SZ0
PCR
A5PCW1 A6TED1
RTCSR
CMF
RTCNT

RTCOR

RFCR

SDMR2 SDMR3 DMABRGCR
A1RXHE A1RXHF
DMAC
DMAATXSAR0

DMAARXDAR0

Rev. 1.0, 02/03, page 1137 of 1294
Abbrev.
DMAATXTCR0
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2
RAR TAR
Bit 25/ 17/9/ 1
RAM1 RDS TAM1 TDS
Bit 24/ 16/8/0
RAM0 RDE TAM0 TDE
Module
DMAC
DMAARXTCR0

DMAACR0

DMAATXTCNT0 DMAARXTCNT0 DMAATXSAR1 DMAARXDAR1 DMAATXTCR1
Rev. 1.0, 02/03, page 1138 of 1294
Abbrev.
DMAARXTCR1
Bit 31/ 23/15/7

Bit 30/ 22/14/6
SZ6
Bit 29/ 21/13/5
SZ5
Bit 28/ 20/12/4
SZ12 SZ4
Bit 27/ 19/11/3
SZ11 SZ3
Bit 26/ 18/10/2
RAR TAR SZ10 SZ2
Bit 25/ 17/9/ 1
RAM1 RDS TAM1 TDS SZ9 SZ1 CVRT1 START
Bit 24/ 16/8/0
RAM0 RDE TAM0 TDE RW SZ8 SZ0 CVRT0
Module
DMAC
DMAACR1

DMAATXTCNT1 DMAARXTCNT1 DMAUSAR DMAUDAR DMAURWSZ SZ7 DMAUCR
Rev. 1.0, 02/03, page 1139 of 1294
Abbrev.
SAR0
Bit 31/ 23/15/7

Bit 30/ 22/14/6
SSA1 DM0 TS2 SSA1 DM0 TS2
Bit 29/ 21/13/5
SSA0 SM1 TS1 SSA0 SM1 TS1
Bit 28/ 20/12/4
STC SM0 TS0 STC SM0 TS0
Bit 27/ 19/11/3
DSA2 DS RS3 CHSET DSA2 DS RS3 CHSET
Bit 26/ 18/10/2
DSA1 RL RS2 IE DSA1 RL RS2 IE
Bit 25/ 17/9/ 1
DSA0 AM RS1 TE DSA0 AM RS1 TE
Bit 24/ 16/8/0
DTC AL RS0 DE DTC AL RS0 DE
Module
DMAC
DAR0

DMATCR0

CHCR0
SSA2 DM1 TM
SAR1

DAR1

DMATCR1

CHCR1
SSA2 DM1 TM
Rev. 1.0, 02/03, page 1140 of 1294
Abbrev.
SAR2
Bit 31/ 23/15/7

Bit 30/ 22/14/6
SSA1 DM0 TS2 SSA1 DM0 TS2
Bit 29/ 21/13/5
SSA0 SM1 TS1 SSA0 SM1 TS1
Bit 28/ 20/12/4
STC SM0 TS0 STC SM0 TS0
Bit 27/ 19/11/3
DSA2 DS RS3 CHSET DSA2 DS RS3 CHSET
Bit 26/ 18/10/2
DSA1 RL RS2 IE DSA1 RL RS2 IE
Bit 25/ 17/9/ 1
DSA0 AM RS1 TE DSA0 AM RS1 TE
Bit 24/ 16/8/0
DTC AL RS0 DE DTC AL RS0 DE
Module
DMAC
DAR2

DMATCR2

CHCR2
SSA2 DM1 TM
SAR3

DAR3

DMATCR3

CHCR3
SSA2 DM1 TM
Rev. 1.0, 02/03, page 1141 of 1294
Abbrev.
DMAOR
Bit 31/ 23/15/7
DMS1
Bit 30/ 22/14/6
DMS0 SSA1 DM0 TS2
Bit 29/ 21/13/5
SSA0 SM1 TS1
Bit 28/ 20/12/4
STC SM0 TS0
Bit 27/ 19/11/3
DSA2 DS RS3 CHSET
Bit 26/ 18/10/2
AE DSA1 RL RS2 IE
Bit 25/ 17/9/ 1
PR1 NMIF DSA0 AM RS1 TE
Bit 24/ 16/8/0
PR0 DME DTC AL RS0 DE
Module
DMAC
SAR4

DAR4

DMATCR4

CHCR4
SSA2 DM1 TM
SAR5

DAR5

DMATCR5

Rev. 1.0, 02/03, page 1142 of 1294
Abbrev.
CHCR5
Bit 31/ 23/15/7
SSA2 DM1 TM
Bit 30/ 22/14/6
SSA1 DM0 TS2 SSA1 DM0 TS2
Bit 29/ 21/13/5
SSA0 SM1 TS1 SSA0 SM1 TS1
Bit 28/ 20/12/4
STC SM0 TS0 STC SM0 TS0
Bit 27/ 19/11/3
DSA2 DS RS3 CHSET DSA2 DS RS3 CHSET
Bit 26/ 18/10/2
DSA1 RL RS2 IE DSA1 RL RS2 IE
Bit 25/ 17/9/ 1
DSA0 AM RS1 TE DSA0 AM RS1 TE
Bit 24/ 16/8/0
DTC AL RS0 DE DTC AL RS0 DE
Module
DMAC
SAR6

DAR6

DMATCR6

CHCR6
SSA2 DM1 TM
SAR7

DAR7

DMATCR7

Rev. 1.0, 02/03, page 1143 of 1294
Abbrev.
CHCR7
Bit 31/ 23/15/7
SSA2 DM1 TM
Bit 30/ 22/14/6
SSA1 DM0 TS2 CH0RS6 CH1RS6 CH2RS6 CH3RS6 CH4RS6 CH5RS6 CH6RS6 CH7RS6 REX6 R/A2 DS3 DS1 IFC0 WT/IT STHZ CSTP30 CSTP22 CSTP14
Bit 29/ 21/13/5
SSA0 SM1 TS1 CH0RS5 CH1RS5 CH2RS5 CH3RS5 CH4RS5 CH5RS5 CH6RS5 CH7RS5 REX5 RL3 RL1 BFC2 RSTS CSTP29 CSTP13
Bit 28/ 20/12/4
STC SM0 TS0 CH0RS4 CH1RS4 CH2RS4 CH3RS4 CH4RS4 CH5RS4 CH6RS4 CH7RS4 REX4 AL3 AL1 BFC1 MSTP4 WOVF CSTP28 CSTP20 CSTP12
Bit 27/ 19/11/3
DSA2 DS RS3 CHSET CH0RS3 CH1RS3 CH2RS3 CH3RS3 CH4RS3 CH5RS3 CH6RS3 CH7RS3 REX3 CKOEN BFC0 PLL3EN FLMCK3 IOVF CSTP27 CSTP19 CSTP11
Bit 26/ 18/10/2
DSA1 RL RS2 IE CH0RS2 CH1RS2 CH2RS2 CH3RS2 CH4RS2 CH5RS2 CH6RS2 CH7RS2 REX2 DS2 DS0 PLL1EN PFC2 MSTP2 DCKOUT FLMCK2 CKS2 CSTP26 CSTP10
Bit 25/ 17/9/ 1
DSA0 AM RS1 TE CH0RS1 CH1RS1 CH2RS1 CH3RS1 CH4RS1 CH5RS1 CH6RS1 CH7RS1 REX1 RPR1 RL2 RL0 PLL2EN PFC1 DIV1 FLMCK1 CKS1 MSTP6 CSTP25 CSTP17 CSTP9
Bit 24/ 16/8/0
DTC AL RS0 DE CH0RS0 CH1RS0 CH2RS0 CH3RS0 CH4RS0 CH5RS0 CH6RS0 CH7RS0 REX0 RPR0 AL2 AL0 IFC2 PFC0 DIV0 FLMCK0 CKS0 MSTP5 CSTP24 CSTP16 CSTP8 CSTP0
Module
DMAC
DMARSRA
CH0WEN CH1WEN CH2WEN CH3WEN
DMARSRB
CH4WEN CH5WEN CH6WEN CH7WEN
DMARCR
REX7 R/A3
FRQCR
IFC1
CPG
STBCR DCKDR
STBY DCKEN
MCKCR

WTCNT WTCSR STBCR2 CLKSTP00
TME DSLP CSTP31 CSTP23 CSTP15
WDT
Power-down
Rev. 1.0, 02/03, page 1144 of 1294
Abbrev.
CLKSTPCLR00
Bit 31/ 23/15/7
CSTP31 CSTP23 CSTP15
Bit 30/ 22/14/6
CSTP30 CSTP22 CSTP14
Bit 29/ 21/13/5
CSTP29 CSTP13 UNIE UNIE
Bit 28/ 20/12/4
CSTP28 CSTP20 CSTP12 CKEG1 CKEG1
Bit 27/ 19/11/3
CSTP27 CSTP19 CSTP11 CKEG0 CKEG0
Bit 26/ 18/10/2
CSTP26 CSTP10 STR2 TPSC2 TPSC2
Bit 25/ 17/9/ 1
CSTP25 CSTP17 CSTP9 STR1 TPSC1 TPSC1
Bit 24/ 16/8/0
CSTP24 CSTP16 CSTP8 CSTP0 STR0 UNF TPSC0 UNF TPSC0
Module
Power-down
TSTR TCOR0

TMU
TCNT0

TCR0

TCOR1

TCNT1

TCR1

TCOR2

TCNT2

Rev. 1.0, 02/03, page 1145 of 1294
Abbrev.
TCR2
Bit 31/ 23/15/7
ICPE1
Bit 30/ 22/14/6
ICPE0 ED3 FRCM FRT FRT FRT FRT TE2 ICE2 CC3 SI2 IC2
Bit 29/ 21/13/5
UNIE ED2 FRTM FRT FRT FRT FRT TE1 ICE1 CC2 SI1 IC1
Bit 28/ 20/12/4
CKEG1 ED2 T23 FRT FRT FRT FRT TE0 ICE0 CC2 SI0 IC0
Bit 27/ 19/11/3
CKEG0 ED1 T23 FRT FRT FRT FRT IOE3 IEE3 CC1 OP3 IO3 IE3
Bit 26/ 18/10/2
TPSC2 ED1 T23 FRT FRT FRT FRT IOE2 IEE2 CC1 OP2 IO2 IE2
Bit 25/ 17/9/ 1
ICPF TPSC1 ROT2 ED0 T01 FRT FRT FRT FRT IOE1 IEE1 CC0 OP1 IO1 IE1
Bit 24/ 16/8/0
UNF TPSC0 ROT0 ED0 T01 FRT FRT FRT FRT IOE0 IEE0 CC0 OP0 IO0 IE0
Module
TMU
TCPR2

CMTCFG
ED3
CMT
CMTFRT
FRT FRT FRT FRT
CMTCTL
TE3 ICE3 CC3 SI3
CMTIRQS
IC3
CMTCH0T
Channel 0 time 31-24 Channel 0 time 23-16 Channel 0 time 15-8 Channel 0 time 7-0
CMTCH1T
Channel 1 time 31-24 Channel 1 time 23-16 Channel 1 time 15-8 Channel 1 time 7-0
Rev. 1.0, 02/03, page 1146 of 1294
Abbrev.
CMTCH2T
Bit 31/ 23/15/7
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
Bit 27/ 19/11/3
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
Module
CMT
Channel 2 time 31-24 Channel 2 time 23-16 Channel 2 time 15-8 Channel 2 time 7-0
CMTCH3T
Channel 3 time 31-24 Channel 3 time 23-16 Channel 3 time 15-8 Channel 3 time 7-0
CMTCH0ST
Channel 0 stop time 31-24 Channel 0 stop time 23-16 Channel 0 stop time 15-8 Channel 0 stop time 7-0
CMTCH1ST
Channel 1 stop time 31-24 Channel 1 stop time 23-16 Channel 1 stop time 15-8 Channel 1 stop time 7-0
CMTCH2ST
Channel 2 stop time 31-24 Channel 2 stop time 23-16 Channel 2 stop time 15-8 Channel 2 stop time 7-0
CMTCH3ST
Channel 3 stop time 31-24 Channel 3 stop time 23-16 Channel 3 stop time 15-8 Channel 3 stop time 7-0
CMTCH0C

Channel 0 counter 15-8 Channel 0 counter 7-0 CMTCH1C
Channel 1 counter 15-8 Channel 1 counter 7-0
Rev. 1.0, 02/03, page 1147 of 1294
Abbrev.
CMTCH2C
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1

Bit 24/ 16/8/0

Module
CMT
Channel 2 counter 15-8 Channel 2 counter 7-0 CMTCH3C
Channel 3 counter 15-8 Channel 3 counter 7-0 SCSMR0 C/A SCBRR0 SCSCR0 TIE SCFTDR0 SCFSR0 ER SCFRDR0 SCFCR0 RTRG1 SCTFDR0 T7 SCRFDR0 R7 SCSPTR0 SCLSR0 SCRER0 PER7 FER7 SCSMR1 C/A SCBRR1 CHR RIE TEND RTRG0 T6 R6 PER6 FER6 CHR PE TE TDFE TTRG1 T5 R5 PER5 FER5 PE O/E RE BRK TTRG0 T4 R4 PER4 FER4 O/E STOP REIE FER T3 R3 SCKIO PER3 FER3 STOP PER TFRST T2 R2 SCKDT PER2 FER2 CKS1 CKE1 RDF RFRST T1 R1 SPB2IO PER1 FER1 CKS1 CKS0 CKE0 DR LOOP T0 R0 SPB2DT ORER PER0 FER0 CKS0 SCIF(1) SCIF(0)
Rev. 1.0, 02/03, page 1148 of 1294
Abbrev.
SCSCR1
Bit 31/ 23/15/7
TIE
Bit 30/ 22/14/6
RIE TEND RTRG0 T6 R6 RTSDT PER6 FER6 CHR RIE TEND RTRG0 T6 R6
Bit 29/ 21/13/5
TE TDFE TTRG1 T5 R5 CTSIO PER5 FER5 PE TE TDFE TTRG1 T5 R5
Bit 28/ 20/12/4
RE BRK TTRG0 T4 R4 CTSDT PER4 FER4 O/E RE BRK TTRG0 T4 R4
Bit 27/ 19/11/3
REIE FER MCE T3 R3 SCKIO PER3 FER3 STOP REIE FER MCE T3 R3
Bit 26/ 18/10/2
PER RSTRG2 TFRST T2 R2 SCKDT PER2 FER2 PER RSTRG2 TFRST T2 R2
Bit 25/ 17/9/ 1
CKE1 RDF RSTRG1 RFRST T1 R1 SPB2IO PER1 FER1 CKS1 CKE1 RDF RSTRG1 RFRST T1 R1
Bit 24/ 16/8/0
CKE0 DR RSTRG0 LOOP T0 R0 SPB2DT ORER PER0 FER0 CKS0 CKE0 DR RSTRG0 LOOP T0 R0
Module
SCIF(1)
SCFTDR1 SCFSR1
ER
SCFRDR1 SCFCR1
RTRG1
SCTFDR1
T7
SCRFDR1
R7
SCSPTR1
RTSIO
SCLSR1

SCRER1
PER7 FER7
SCSMR2
C/A
SCIF(2)
SCBRR2 SCSCR2
TIE
SCFTDR2 SCFSR2
ER
SCFRDR2 SCFCR2
RTRG1
SCTFDR2
T7
SCRFDR2
R7
Rev. 1.0, 02/03, page 1149 of 1294
Abbrev.
SCSPTR2
Bit 31/ 23/15/7
RTSIO
Bit 30/ 22/14/6
RTSDT PER6 FER6 RIE SITD6 RDRF SIRD6 LCB
Bit 29/ 21/13/5
CTSIO PER5 FER5 PE TE SITD5 ORER SIRD5 PB
Bit 28/ 20/12/4
CTSDT PER4 FER4 O/E RE SITD4 ERS SIRD4
Bit 27/ 19/11/3
SCKIO PER3 FER3 WAIT_IE SITD3 PER SIRD3 SDIR
Bit 26/ 18/10/2
SCKDT PER2 FER2 BRR2 TEIE SITD2 TEND SIRD2 SINV
Bit 25/ 17/9/ 1
SPB2IO PER1 FER1 BRR1 CKE1 SITD1
Bit 24/ 16/8/0
SPB2DT ORER PER0 FER0 BRR0 CKE0 SITD0
Module
SCIF(2)
SCLSR2

SCRER2
PER7 FER7
SISMR SIBRR SISCR SITDR SISSR SIRDR SISCMR SISC2R SIWAIT
TIE SITD7 TDRE SIRD7 EIO
SIM
WAIT_ER SIRD1 RST SIRD0 SMIF SIWAIT8 SIWAIT0 SIGRD0 SISMPL8 SISMPL0 FNA ESG SAR I2C(0)
SIWAIT15 SIWAIT14 SIWAIT13 SIWAIT12 SIWAIT11 SIWAIT10 SIWAIT9 SIWAIT7 SIWAIT6 SIGRD6 SISMPL6 FSCL GCAR SIWAIT5 SIGRD5 SISMPL5 FSDA STM SIWAIT4 SIGRD4 SISMPL4 OBPC SSR SIWAIT3 SIGRD3 SISMPL3 SDBS MIE SDE SIWAIT2 SIGRD2 SIWAIT1 SIGRD1
SIGRD SISMPL
SIGRD7 SISMPL7
SISMPL10 SISMPL9 SISMPL2 SIE TSBE SDT SISMPL1 GCAE FSB SDR
ICSCR0

ICMCR0
MDBS
ICSSR0

Rev. 1.0, 02/03, page 1150 of 1294
Abbrev.
ICMSR0
Bit 31/ 23/15/7

Bit 30/ 22/14/6
MNR MNRE SCGD
Bit 29/ 21/13/5
MAL MALE SCGD
Bit 28/ 20/12/4
MST SSRE MSTE SCGD
Bit 27/ 19/11/3
MDE SDEE MDEE SCGD
Bit 26/ 18/10/2
MDT SDTE MDTE SCGD
Bit 25/ 17/9/ 1
MDR SDRE MDRE CDF
Bit 24/ 16/8/0
MAT SARE MATE CDF
Module
I2C(0)
ICSIER0

ICMIER0

ICCCR0
SCGD
ICSAR0

SADD0_6 SADD0_5 SADD0_4 SADD0_3 SADD0_2 SADD0_1 SADD0_0
ICMAR0

SADD1_6 SADD1_5 SADD1_4 SADD1_3 SADD1_2 SADD1_1 SADD1_0 STM1 ICRXD0 RXD ICTXD0 TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD
Rev. 1.0, 02/03, page 1151 of 1294
Abbrev.
ICFCR0
Bit 31/ 23/15/7
RTRG3
Bit 30/ 22/14/6
RTRG2 FSCL GCAR
Bit 29/ 21/13/5
RTRG1 FSDA STM
Bit 28/ 20/12/4
RTRG0 R4 T4 OBPC SSR
Bit 27/ 19/11/3
TTRG1 R3 T3 SDBS MIE SDE
Bit 26/ 18/10/2
TTRG0 TEND TEIE R2 T2 SIE TSBE SDT
Bit 25/ 17/9/ 1
RFRST RDF RXIE R1 T1 GCAE FSB SDR
Bit 24/ 16/8/0
TFRST TDFE TXIE R0 T0 FNA ESG SAR
Module
I2C(0)
ICFSR0

ICFIER0

ICRFDR0

ICTFDR0

ICSCR1

I2C(1)
ICMCR1
MDBS
ICSSR1

Rev. 1.0, 02/03, page 1152 of 1294
Abbrev.
ICMSR1
Bit 31/ 23/15/7

Bit 30/ 22/14/6
MNR MNRE SCGD
Bit 29/ 21/13/5
MAL MALE SCGD
Bit 28/ 20/12/4
MST SSRE MSTE SCGD
Bit 27/ 19/11/3
MDE SDEE MDEE SCGD
Bit 26/ 18/10/2
MDT SDTE MDTE SCGD
Bit 25/ 17/9/ 1
MDR SDRE MDRE CDF
Bit 24/ 16/8/0
MAT SARE MATE CDF
Module
I2C(1)
ICSIER1

ICMIER1

ICCCR1
SCGD
ICSAR1

SADD0_6 SADD0_5 SADD0_4 SADD0_3 SADD0_2 SADD0_1 SADD0_0
ICMAR1

SADD1_6 SADD1_5 SADD1_4 SADD1_3 SADD1_2 SADD1_1 SADD1_0 STM1 ICRXD1 RXD ICTXD1 TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD RXD TXD
Rev. 1.0, 02/03, page 1153 of 1294
Abbrev.
ICFCR1
Bit 31/ 23/15/7
RTRG3
Bit 30/ 22/14/6
RTRG2 CHNL0 SWSD CKDV
Bit 29/ 21/13/5
RTRG1 DWL2 SCKP CKDV
Bit 28/ 20/12/4
RTRG0 R4 T4 DMEN DWL1 SWSP CKDV DMRQ
Bit 27/ 19/11/3
TTRG1 R3 T3 UIEN DWL0 SPDP MUEN UIRQ CHNO1
Bit 26/ 18/10/2
TTRG0 TEND TEIE R2 T2 OIEN SWL2 SDTA CPEN OIRQ CHNO0
Bit 25/ 17/9/ 1
RFRST RDF RXIE R1 T1 IIEN SWL1 PDTA TRMD IIRQ SWNO
Bit 24/ 16/8/0
TFRST TDFE TXIE R0 T0 DIEN SWL0 DEL EN DIRQ IDST
Module
I2C(1)
ICFSR1

ICFIER1

ICRFDR1

ICTFDR1

SSICR0
CHNL1 SCKD BREN
SSI(0)
SSISR0

SSITDR0

Rev. 1.0, 02/03, page 1154 of 1294
Abbrev.
SSIRDR0
Bit 31/ 23/15/7

Bit 30/ 22/14/6
CHNL0 SWSD CKDV REV HCFS0
Bit 29/ 21/13/5
DWL2 SCKP CKDV REV BLE
Bit 28/ 20/12/4
DMEN DWL1 SWSP CKDV DMRQ REV CLE
Bit 27/ 19/11/3
UIEN DWL0 SPDP MUEN UIRQ CHNO1 REV IE OCR
Bit 26/ 18/10/2
OIEN SWL2 SDTA CPEN OIRQ CHNO0 REV RWE PLE BLF
Bit 25/ 17/9/ 1
IIEN SWL1 PDTA TRMD IIRQ SWNO REV RWC CBSR1 SOC1 CLF
Bit 24/ 16/8/0
DIEN SWL0 DEL EN DIRQ IDST REV IR CBSR0 SOC0 HCR
Module
SSI(0)
SSICR1
CHNL1 SCKD BREN
SSI(1)
SSISR1

SSITDR1

SSIRDR1

HcRevision
REV
USB
HcControl
HCFS1
HcCommand status

Rev. 1.0, 02/03, page 1155 of 1294
Abbrev.
HcInterrupt Status
Bit 31/ 23/15/7

Bit 30/ 22/14/6
OC RHSC OC RHSC OC RHSC HCCA HCCA HCCA PCED PCED PCED PCED CHED CHED CHED CHED CCED CCED CCED CCED BHED BHED BHED BHED
Bit 29/ 21/13/5
FNO FNO FNO HCCA HCCA HCCA PCED PCED PCED PCED CHED CHED CHED CHED CCED CCED CCED CCED BHED BHED BHED BHED
Bit 28/ 20/12/4
UE UE UE HCCA HCCA HCCA PCED PCED PCED PCED CHED CHED CHED CHED CCED CCED CCED CCED BHED BHED BHED BHED
Bit 27/ 19/11/3
RD RD RD HCCA HCCA HCCA PCED PCED PCED CHED CHED CHED CCED CCED CCED BHED BHED BHED
Bit 26/ 18/10/2
SF SF SF HCCA HCCA HCCA PCED PCED PCED CHED CHED CHED CCED CCED CCED BHED BHED BHED
Bit 25/ 17/9/ 1
WDH WDH WDH HCCA HCCA HCCA PCED PCED PCED CHED CHED CHED CCED CCED CCED BHED BHED BHED
Bit 24/ 16/8/0
SO SO SO HCCA HCCA HCCA PCED PCED PCED CHED CHED CHED CCED CCED CCED BHED BHED BHED
Module
USB
HcInterrupt Enable
MIE
HcInterrupt Disable
MIE
HcHCCA
HCCA HCCA HCCA
HcPeriod CurrentED
PCED PCED PCED PCED
HcControl HeadED
CHED CHED CHED CHED
HcControl CurrentED
CCED CCED CCED CCED
HcBulk HeadED
BHED BHED BHED BHED
Rev. 1.0, 02/03, page 1156 of 1294
Abbrev.
HcBulk CurrentED
Bit 31/ 23/15/7
BCED BCED BCED BCED
Bit 30/ 22/14/6
BCED BCED BCED BCED DH DH DH DH FSMPS FSMPS FI FR FN FN PS LST
POTPGT
Bit 29/ 21/13/5
BCED BCED BCED BCED DH DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST
POTPGT
Bit 28/ 20/12/4
BCED BCED BCED BCED DH DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST
POTPGT
Bit 27/ 19/11/3
BCED BCED BCED DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST LST
POTPGT
Bit 26/ 18/10/2
BCED BCED BCED DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST LST
POTPGT
Bit 25/ 17/9/ 1
BCED BCED BCED DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST LST
POTPGT
Bit 24/ 16/8/0
BCED BCED BCED DH DH DH FSMPS FSMPS FI FI FR FR FN FN PS PS LST LST
POTPGT
Module
USB
HcDone Head
DH DH DH DH
HcFm Interval
FIT FSMPS FI
HcFm Remaining
FRT FR
HcFmNumber
FN FN
HcPeriodic Start
PS
HcLS Threshold
LST
HcRh DescriptorA
POTPGT
NDP
NDP
NDP
NOCP NDP
OCPM NDP
DT NDP
NPS NDP
PSM NDP
Rev. 1.0, 02/03, page 1157 of 1294
Abbrev.
HcRh DescriptorB
Bit 31/ 23/15/7
PPCM PPCM DR DR
Bit 30/ 22/14/6
PPCM PPCM DR DR TST6
Bit 29/ 21/13/5
PPCM PPCM DR DR TST5 MCR5 GSR5
Bit 28/ 20/12/4
PPCM PPCM DR DR PRSC PRS TST4 GSR4
Bit 27/ 19/11/3
PPCM PPCM DR DR OCIC POCI TST3 GSR3 BRP3 IRR3 IMR3
Bit 26/ 18/10/2
PPCM PPCM DR DR PSSC PSS TST2 MCR2 GSR2
Bit 25/ 17/9/ 1
PPCM PPCM DR DR OCIC OCI PESC LSDA PES TST1 MCR1 GSR1
Bit 24/ 16/8/0
PPCM PPCM DR DR LPSC LPS CSC PPS CCS TST0 MCR0 GSR0
Module
USB
HcRhStatus
CRWE DRWE
HcRhPort Status1

Shared Memory Start

Shared Memory End

CAN0MCR
TST7 MCR7
HCAN2(0)
CAN0GSR

CAN0BCR1
TSEG1_3 TSEG1_2 TSEG1_1 TSEG1_0 BRP6 IRR14 IRR6 IMR14 IMR6 SJW1 BRP5 IRR13 IRR5 IMR13 IMR5 SJW0 BRP4 IRR12 IRR4 IMR12 IMR4
TSEG2_2 TSEG2_1 TSEG2_0 BRP2 IRR2 IMR2 EG BRP1 IRR9 IRR1 IMR9 IMR1 BSP BRP0 IRR8 IRR0 IMR8 IMR0
CAN0BCR0
BRP7
CAN0IRR
IRR7
CAN0IMR
IMR7
Rev. 1.0, 02/03, page 1158 of 1294
Abbrev.
CAN0TECREC
Bit 31/ 23/15/7
TEC7 REC7
Bit 30/ 22/14/6
TEC6 REC6
Bit 29/ 21/13/5
TEC5 REC5
Bit 28/ 20/12/4
TEC4 REC4
Bit 27/ 19/11/3
TEC3 REC3
Bit 26/ 18/10/2
TEC2 REC2
Bit 25/ 17/9/ 1
TEC1 REC1
Bit 24/ 16/8/0
TEC0 REC0 TXPR1_8 TXPR1_0 TXPR0_8
Module
HCAN2(0)
CAN0TXPR1
TXPR1_15 TXPR1_14 TXPR1_13 TXPR1_12 TXPR1_11 TXPR1_10 TXPR1_9 TXPR1_7 TXPR1_6 TXPR1_5 TXPR1_4 TXPR1_3 TXPR1_2 TXPR1_1
CAN0TXPR0
TXPR0_15 TXPR0_14 TXPR0_13 TXPR0_12 TXPR0_11 TXPR0_10 TXPR0_9 TXPR0_7 TXPR0_6 TXPR0_5 TXPR0_4 TXPR0_3 TXPR0_2 TXPR0_1
CAN0TXCR1
TXCR1_15 TXCR1_14 TXCR1_13 TXCR1_12 TXCR1_11 TXCR1_10 TXCR1_9 TXCR1_8 TXCR1_7 TXCR1_6 TXCR1_5 TXCR1_4 TXCR1_3 TXCR1_2 TXCR1_1 TXCR1_0
CAN0TXCR0
TXCR0_15 TXCR0_14 TXCR0_13 TXCR0_12 TXCR0_11 TXCR0_10 TXCR0_9 TXCR0_8 TXCR0_7 TXCR0_6 TXCR0_5 TXCR0_4 TXCR0_3 TXCR0_2 TXCR0_1
CAN0TXACK1
TXACK1_15 TXACK1_14 TXACK1_13 TXACK1_12 TXACK1_11 TXACK1_10 TXACK1_9 TXACK1_8
TXACK1_7 TXACK1_6 TXACK1_5 TXACK1_4 TXACK1_3 TXACK1_2 TXACK1_1 TXACK1_0 CAN0TXACK0
TXACK0_15 TXACK0_14 TXACK0_13 TXACK0_12 TXACK0_11 TXACK0_10 TXACK0_9 TXACK0_8
TXACK0_7 TXACK0_6 TXACK0_5 TXACK0_4 TXACK0_3 TXACK0_2 TXACK0_1 CAN0ABACK1
ABACK1_15 ABACK1_14 ABACK1_13 ABACK1_12 ABACK1_11 ABACK1_10 ABACK1_9 ABACK1_8
ABACK1_7 ABACK1_6 ABACK1_5 ABACK1_4 ABACK1_3 ABACK1_2 ABACK1_1 ABACK1_0 CAN0ABACK0
ABACK0_15 ABACK0_14 ABACK0_13 ABACK0_12 ABACK0_11 ABACK0_10 ABACK0_9 ABACK0_8
ABACK0_7 ABACK0_6 ABACK0_5 ABACK0_4 ABACK0_3 ABACK0_2 ABACK0_1 CAN0RXPR1 RXPR1_15 RXPR1_14 RXPR1_13 RXPR1_12 RXPR1_11 RXPR1_10 RXPR1_9 RXPR1_8 RXPR1_7 RXPR1_6 RXPR1_5 RXPR1_4 RXPR1_3 RXPR1_2 RXPR1_1 RXPR1_0 CAN0RXPR0 RXPR0_15 RXPR0_14 RXPR0_13 RXPR0_12 RXPR0_11 RXPR0_10 RXPR0_9 RXPR0_8 RXPR0_7 RXPR0_6 RXPR0_5 RXPR0_4 RXPR0_3 RXPR0_2 RXPR0_1 RXPR0_0 CAN0RFPR1 RFPR1_15 RFPR1_14 RFPR1_13 RFPR1_12 RFPR1_11 RFPR1_10 RFPR1_9 RFPR1_8 RFPR1_7 RFPR1_6 RFPR1_5 RFPR1_4 CAN0RFPR0 RFPR1_3 RFPR1_2 RFPR1_1 RFPR1_0
RFPR0_15 RFPR0_14 RFPR0_13 RFPR0_12 RFPR0_11 RFPR0_10 RFPR0_9 RFPR0_8 RFPR0_7 RFPR0_6 RFPR0_5 RFPR0_4 RFPR0_3 RFPR0_2 RFPR0_1 RFPR0_0
CAN0MBIMR1
MBIMR1_15 MBIMR1_14 MBIMR1_13 MBIMR1_12 MBIMR1_11 MBIMR1_10 MBIMR1_9 MBIMR1_8
MBIMR1_7 MBIMR1_6 MBIMR1_5 MBIMR1_4 MBIMR1_3 MBIMR1_2 MBIMR1_1 MBIMR1_0 CAN0MBIMR0
MBIMR0_15 MBIMR0_14 MBIMR0_13 MBIMR0_12 MBIMR0_11 MBIMR0_10 MBIMR0_9 MBIMR0_8
MBIMR0_7 MBIMR0_6 MBIMR0_5 MBIMR0_4 MBIMR0_3 MBIMR0_2 MBIMR0_1 MBIMR0_0 CAN0UMSR1 UMSR1_15 UMSR1_14 UMSR1_13 UMSR1_12 UMSR1_11 UMSR1_10 UMSR1_9 UMSR1_8 UMSR1_7 UMSR1_6 UMSR1_5 UMSR1_4 UMSR1_3 UMSR1_2 UMSR1_1 UMSR1_0
Rev. 1.0, 02/03, page 1159 of 1294
Abbrev.
CAN0UMSR0
Bit 31/ 23/15/7
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
Bit 27/ 19/11/3
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
Module
UMSR0_15 UMSR0_14 UMSR0_13 UMSR0_12 UMSR0_11 UMSR0_10 UMSR0_9 UMSR0_8 HCAN2(0) UMSR0_7 UMSR0_6 UMSR0_5 UMSR0_4 UMSR0_3 UMSR0_2 UMSR0_1 UMSR0_0
CAN0TCNTR
TCNTR15 TCNTR14 TCNTR1 3 TCNTR12 TCNTR11 TCNTR10 TCNTR9 TCNTR7 TCNTR6 TCMR14 TCMR6 TCNTR5 TCR13 TCR5 TCMR13 TCMR5 TCNTR4 TCR12 TCR4 TCMR12 TCMR4 TCNTR3 TCR11 TCR3 TCMR11 TCMR3 TCNTR2 TCR2 TCMR10 TCMR2 TCNTR1 TCR1 TCMR9 TCMR1
TCNTR8 TCNTR0 TCR0 TCMR8 TCMR0
CAN0TCR
TCR15
CAN0TCMR0
TCMR15 TCMR7
CAN0MB0

CAN0MB1

CAN0MB2

CAN0MB3

CAN0MB4

CAN0MB5

CAN0MB6

CAN0MB7

CAN0MB8

CAN0MB9

CAN0MB10

CAN0MB11

Rev. 1.0, 02/03, page 1160 of 1294
Abbrev.
CAN0MB12
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1

Bit 24/ 16/8/0

Module
HCAN2(0)
CAN0MB13

CAN0MB14

CAN0MB15

CAN0MB16

CAN0MB17

CAN0MB18

CAN0MB19

CAN0MB20

CAN0MB21

CAN0MB22

CAN0MB23

CAN0MB24

CAN0MB25

CAN0MB26

CAN0MB27

Rev. 1.0, 02/03, page 1161 of 1294
Abbrev.
CAN0MB28
Bit 31/ 23/15/7

Bit 30/ 22/14/6
TST6
Bit 29/ 21/13/5
TST5 MCR5 GSR5
Bit 28/ 20/12/4
TST4 GSR4
Bit 27/ 19/11/3
TST3 GSR3 BRP3 IRR3 IMR3 TEC3 REC3
Bit 26/ 18/10/2
TST2 MCR2 GSR2
Bit 25/ 17/9/ 1
TST1 MCR1 GSR1
Bit 24/ 16/8/0
TST0 MCR0 GSR0
Module
HCAN2(0)
CAN0MB29

CAN0MB30

CAN0MB31

CAN1MCR
TST7 MCR7
HCAN2(1)
CAN1GSR

CAN1BCR1
TSEG1_3 TSEG1_2 TSEG1_1 TSEG1_0 BRP6 IRR14 IRR6 IMR14 IMR6 TEC6 REC6 SJW1 BRP5 IRR13 IRR5 IMR13 IMR5 TEC5 REC5 SJW0 BRP4 IRR12 IRR4 IMR12 IMR4 TEC4 REC4
TSEG2_2 TSEG2_1 TSEG2_0 BRP2 IRR2 IMR2 TEC2 REC2 EG BRP1 IRR9 IRR1 IMR9 IMR1 TEC1 REC1 BSP BRP0 IRR8 IRR0 IMR8 IMR0 TEC0 REC0 TXPR1_8 TXPR1_0 TXPR0_8
CAN1BCR0
BRP7
CAN1IRR
IRR7
CAN1IMR
IMR7
CAN1TECREC
TEC7 REC7
CAN1TXPR1
TXPR1_15 TXPR1_14 TXPR1_13 TXPR1_12 TXPR1_11 TXPR1_10 TXPR1_9 TXPR1_7 TXPR1_6 TXPR1_5 TXPR1_4 TXPR1_3 TXPR1_2 TXPR1_1
CAN1TXPR0
TXPR0_15 TXPR0_14 TXPR0_13 TXPR0_12 TXPR0_11 TXPR0_10 TXPR0_9 TXPR0_7 TXPR0_6 TXPR0_5 TXPR0_4 TXPR0_3 TXPR0_2 TXPR0_1
CAN1TXCR1
TXCR1_15 TXCR1_14 TXCR1_13 TXCR1_12 TXCR1_11 TXCR1_10 TXCR1_9 TXCR1_8 TXCR1_7 TXCR1_6 TXCR1_5 TXCR1_4 TXCR1_3 TXCR1_2 TXCR1_1 TXCR1_0
CAN1TXCR0
TXCR0_15 TXCR0_14 TXCR0_13 TXCR0_12 TXCR0_11 TXCR0_10 TXCR0_9 TXCR0_8 TXCR0_7 TXCR0_6 TXCR0_5 TXCR0_4 TXCR0_3 TXCR0_2 TXCR0_1
Rev. 1.0, 02/03, page 1162 of 1294
Abbrev.
CAN1TXACK1
Bit 31/ 23/15/7
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
Bit 27/ 19/11/3
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
Module
TXACK1_15 TXACK1_14 TXACK1_13 TXACK1_12 TXACK1_11 TXACK1_10 TXACK1_9 TXACK1_8 HCAN2(1)
TXACK1_7 TXACK1_6 TXACK1_5 TXACK1_4 TXACK1_3 TXACK1_2 TXACK1_1 TXACK1_0 CAN1TXACK0
TXACK0_15 TXACK0_14 TXACK0_13 TXACK0_12 TXACK0_11 TXACK0_10 TXACK0_9 TXACK0_8
TXACK0_7 TXACK0_6 TXACK0_5 TXACK0_4 TXACK0_3 TXACK0_2 TXACK0_1 CAN1ABACK1
ABACK1_15 ABACK1_14 ABACK1_13 ABACK1_12 ABACK1_11 ABACK1_10 ABACK1_9 ABACK1_8
ABACK1_7 ABACK1_6 ABACK1_5 ABACK1_4 ABACK1_3 ABACK1_2 ABACK1_1 ABACK1_0 CAN1ABACK0
ABACK0_15 ABACK0_14 ABACK0_13 ABACK0_12 ABACK0_11 ABACK0_10 ABACK0_9 ABACK0_8
ABACK0_7 ABACK0_6 ABACK0_5 ABACK0_4 ABACK0_3 ABACK0_2 ABACK0_1 CAN1RXPR1 RXPR1_15 RXPR1_14 RXPR1_13 RXPR1_12 RXPR1_11 RXPR1_10 RXPR1_9 RXPR1_8 RXPR1_7 RXPR1_6 RXPR1_5 RXPR1_4 RXPR1_3 RXPR1_2 RXPR1_1 RXPR1_0 CAN1RXPR0 RXPR0_15 RXPR0_14 RXPR0_13 RXPR0_12 RXPR0_11 RXPR0_10 RXPR0_9 RXPR0_8 RXPR0_7 RXPR0_6 RXPR0_5 RXPR0_4 RXPR0_3 RXPR0_2 RXPR0_1 RXPR0_0 CAN1RFPR1 RFPR1_15 RFPR1_14 RFPR1_13 RFPR1_12 RFPR1_11 RFPR1_10 RFPR1_9 RFPR1_8 RFPR1_7 RFPR1_6 RFPR1_5 RFPR1_4 CAN1RFPR0 RFPR1_3 RFPR1_2 RFPR1_1 RFPR1_0
RFPR0_15 RFPR0_14 RFPR0_13 RFPR0_12 RFPR0_11 RFPR0_10 RFPR0_9 RFPR0_8 RFPR0_7 RFPR0_6 RFPR0_5 RFPR0_4 RFPR0_3 RFPR0_2 RFPR0_1 RFPR0_0
CAN1MBIMR1
MBIMR1_15 MBIMR1_14 MBIMR1_13 MBIMR1_12 MBIMR1_11 MBIMR1_10 MBIMR1_9 MBIMR1_8
MBIMR1_7 MBIMR1_6 MBIMR1_5 MBIMR1_4 MBIMR1_3 MBIMR1_2 MBIMR1_1 MBIMR1_0 CAN1MBIMR0
MBIMR0_15 MBIMR0_14 MBIMR0_13 MBIMR0_12 MBIMR0_11 MBIMR0_10 MBIMR0_9 MBIMR0_8
MBIMR0_7 MBIMR0_6 MBIMR0_5 MBIMR0_4 MBIMR0_3 MBIMR0_2 MBIMR0_1 MBIMR0_0 CAN1UMSR1 UMSR1_15 UMSR1_14 UMSR1_13 UMSR1_12 UMSR1_11 UMSR1_10 UMSR1_9 UMSR1_8 UMSR1_7 UMSR1_6 UMSR1_5 UMSR1_4 UMSR1_3 UMSR1_2 UMSR1_1 UMSR1_0 CAN1UMSR0 UMSR0_15 UMSR0_14 UMSR0_13 UMSR0_12 UMSR0_11 UMSR0_10 UMSR0_9 UMSR0_8 UMSR0_7 UMSR0_6 UMSR0_5 UMSR0_4 UMSR0_3 UMSR0_2 UMSR0_1 UMSR0_0 CAN1TCNTR TCNTR15 TCNTR14 TCNTR13 TCNTR12 TCNTR11 TCNTR10 TCNTR9 TCNTR7 CAN1TCR TCR15 CAN1TCMR TCMR15 TCMR7 CAN1MB0 TCNTR6 TCMR14 TCMR6 TCNTR5 TCR13 TCR5 TCMR13 TCMR5 TCNTR4 TCR12 TCR4 TCMR12 TCMR4 TCNTR3 TCR11 TCR3 TCMR11 TCMR3 TCNTR2 TCR2 TCMR10 TCMR2 TCNTR1 TCR1 TCMR9 TCMR1 TCNTR8 TCNTR0 TCR0 TCMR8 TCMR0
Rev. 1.0, 02/03, page 1163 of 1294
Abbrev.
CAN1MB1
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1

Bit 24/ 16/8/0

Module
HCAN2(1)
CAN1MB2

CAN1MB3

CAN1MB4

CAN1MB5

CAN1MB6

CAN1MB7

CAN1MB8

CAN1MB9

CAN1MB10

CAN1MB11

CAN1MB12

CAN1MB13

CAN1MB14

CAN1MB15

CAN1MB16

Rev. 1.0, 02/03, page 1164 of 1294
Abbrev.
CAN1MB17
Bit 31/ 23/15/7

Bit 30/ 22/14/6

Bit 29/ 21/13/5

Bit 28/ 20/12/4

Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1

Bit 24/ 16/8/0

Module
HCAN2(1)
CAN1MB18

CAN1MB19

CAN1MB20

CAN1MB21

CAN1MB22

CAN1MB23

CAN1MB24

CAN1MB25

CAN1MB26

CAN1MB27

CAN1MB28

CAN1MB29

CAN1MB30

CAN1MB31

Rev. 1.0, 02/03, page 1165 of 1294
Abbrev.
SPCR
Bit 31/ 23/15/7
FBS
Bit 30/ 22/14/6
CLKP RXHA CSV TD RD PA7MD0 PA3MD0 PB7MD0 PB3MD0 PC7MD0 PC3MD0 PD7MD0 PD3MD0 PE7MD0 PE3MD0 PF3MD0
Bit 29/ 21/13/5
IDIV RXEM TEIE CSA TD RD PA6MD1 PA2MD1 PB6MD1 PB2MD1 PC6MD1 PC2MD1 PD6MD1 PD2MD1 PE6MD1 PE2MD1 PF2MD1
Bit 28/ 20/12/4
CLKC4 RXOO THIE TFIE TD RD PA6MD0 PA2MD0 PB6MD0 PB2MD0 PC6MD0 PC2MD0 PD6MD0 PD2MD0 PE6MD0 PE2MD0 PF2MD0
Bit 27/ 19/11/3
CLKC3 RXOW RNIE ROIE TD RD PA5MD1 PB5MD1 PB1MD1 PC5MD1 PC1MD1 PD5MD1 PD1MD1 PE5MD1 PE1MD1 PF1MD1
Bit 26/ 18/10/2
CLKC2 TXFU RXFL RHIE RXDE TD RD PA5MD0 PB5MD0 PB1MD0 PC5MD0 PC1MD0 PD5MD0 PD1MD0 PE5MD0 PE1MD0 PF1MD0
Bit 25/ 17/9/ 1
CLKC1 TXHA TXFN RFIE TXDE TD RD PA4MD1 PB4MD1 PC4MD1 PC0MD1 PD4MD1 PD0MD1 PE4MD1 PE0MD1 PF0MD1
Bit 24/ 16/8/0
CLKC0 TXEM TXFL FFEN MASL TD RD PA4MD0 PB4MD0 PC4MD0 PC0MD0 PD4MD0 PD0MD0 PE4MD0 PE0MD0 PF0MD0
Module
HSPI
SPSR
RXFU
SPSCR
LMSB
SPTBR
TD
SPRBR
RD
PACR
PA7MD1 PA3MD1
PFC
PBCR
PB7MD1 PB3MD1
PCCR
PC7MD1 PC3MD1
PDCR
PD7MD1 PD3MD1
PECR
PE7MD1 PE3MD1
PFCR
PF3MD1
Rev. 1.0, 02/03, page 1166 of 1294
Abbrev.
PGCR
Bit 31/ 23/15/7
PG7MD1 PG3MD1
Bit 30/ 22/14/6
PG7MD0 PG3MD0 PH7MD0 PH3MD0 PJ7MD0 PJ3MD0 PK7MD0 PK3MD0 PA6DT PB6DT PC6DT PD6DT PE6DT PG6DT PH6DT PJ6DT PK6DT RDYPUP DRAKD0 SCIRXD0 SCICTS2
Bit 29/ 21/13/5
PG6MD1 PG2MD1 PH6MD1 PH2MD1 PJ6MD1 PJ2MD1 PK6MD1 PK2MD1 PA5DT PB5DT PC5DT PD5DT PE5DT PG5DT PH5DT PJ5DT PK5DT
Bit 28/ 20/12/4
PG6MD0 PG2MD0 PH6MD0 PH2MD0 PJ6MD0 PJ2MD0 PK6MD0 PK2MD0 PA4DT PB4DT PC4DT PD4DT PE4DT PG4DT PH4DT PJ4DT PK4DT
Bit 27/ 19/11/3
PG5MD1 PG1MD1 PH5MD1 PH1MD1 PJ5MD1 PJ1MD1 PK5MD1 PA3DT PB3DT PC3DT PD3DT PE3DT PF3DT PG3DT PH3DT PJ3DT PK3DT IRL1PUP DACKP0 SCICTS1 SCITXD2
Bit 26/ 18/10/2
PG5MD0 PG1MD0 PH5MD0 PH1MD0 PJ5MD0 PJ1MD0 PK5MD0 PA2DT PB2DT PC2DT PD2DT PE2DT PF2DT PG2DT PH2DT PJ2DT PK2DT IRL2PUP DACKD0 SCIRTS1
Bit 25/ 17/9/ 1
PG4MD1 PG0MD1 PH4MD1 PH0MD1 PJ4MD1 PK4MD1 PB1DT PC1DT PD1DT PE1DT PF1DT PG1DT PH1DT PJ1DT IRL3PUP DACKP1 SCIRXD1
Bit 24/ 16/8/0
PG4MD0 PG0MD0 PH4MD0 PH0MD0 PJ4MD0 PK4MD0 PC0DT PD0DT PE0DT PF0DT PG0DT PH0DT NMIPUP DACKD1 BRGRST SCITXD1 LCDMD0
Module
PFC
PHCR
PH7MD1 PH3MD1
PJCR
PJ7MD1 PJ3MD1
PKCR
PK7MD1 PK3MD1
PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR INPUPA
PA7DT PB7DT PC7DT PD7DT PE7DT PG7DT PH7DT PJ7DT PK7DT MD6PUP
BREQPUP IRL0PUP DREQP1 DRAKP1 SCITXD0 SCIRTS2 DRAKD1 SCICLK1 SCIRXD2
DMAPCR
DREQP0 DRAKP0
SCIHZR
SCICLK0 SCICLK2
IPSELR
IPSELR15 IPSELR14 IPSELR13 IPSELR12 IPSELR11 IPSELR10 IPSELR9 LCDMD1
PAPUPR PBPUPR PCPUPR PDPUPR PEPUPR PFPUPR PGPUPR
PA7PUPR PA6PUPR PA5PUPR PA4PUPR PA3PUPR PA2PUPR
PB7PUPR PB6PUPR PB5PUPR PB4PUPR PB3PUPR PB2PUPR PB1PUPR PC7PUPR PC6PUPR PC5PUPR PC4PUPR PC3PUPR PC2PUPR PC1PUPR PC0PUPR PD7PUPR PD6PUPR PD5PUPR PD4PUPR PD3PUPR PD2PUPR PD1PUPR PD0PUPR PE7PUPR PE6PUPR PE5PUPR PE4PUPR PE3PUPR PE2PUPR PE1PUPR PE0PUPR PF3PUPR PF2PUPR PF1PUPR PF0PUPR
PG7PUPR PG6PUPR PG5PUPR PE4PUPR PG3PUPR PG2PUPR PG1PUPR PG0PUPR
Rev. 1.0, 02/03, page 1167 of 1294
Abbrev.
PHPUPR PJPUPR PKPUPR MDPUPR MODSELR GPIOIC
Bit 31/ 23/15/7
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
Bit 27/ 19/11/3
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
Module
PH7PUPR PH6PUPR PH5PUPR PH4PUPR PH3PUPR PH2PUPR PH1PUPR PH0PUPR PFC PJ7PUPR PJ6PUPR PJ5PUPR PJ4PUPR PH3PUPR PJ2PUPR PK7PUPR PK6PUPR PK5PUPR PK4PUPR PK3PUPR PK2PUPR
MDPUPR7 MDPUPR6 MDPUPR5 MDPUPR4 MDPUPR3 MDPUPR2 MDPUPR1 MDPUPR0
MODSELR7 MODSELR6 MODSELR5 MODSELR4 MODSELR3 MODSELR2 MODSELR1
PTIREN15 PTIREN14 PTIREN13 PTIREN12 PTIREN11 PTIREN10 PTIREN9 STBRT7 STBRT6 CA2/SA2 SLREQ8 STBIRQ5 ST CA1/SA1 SLREQ9 STBIRQ4 CA0/SA0 STBIRL3 CDRT RW SLREQ3 STBIRL2 WMRT CA6/SA6 SLREQ4 STBIRL1 CA5/SA5 SLREQ5
STBRT8 STBIRL0 CA4/SA4 SLREQ6 HAC(0)
HACCR0
CR
HACCSAR0
CA3/SA3 SLREQ7
SLREQ10 SLREQ11 SLREQ12 CD8/SD8 CD0/SD0 /LD12 /LD4
HACCSDR0

CD15/SD15 CD14/SD14 CD13/SD13 CD12/SD12
CD11/SD11 CD10/SD10 CD9/SD9
CD7/SD7 /LD11 D19/LD3
CD6/SD6 /LD10 D18/LD2
CD5/SD5 /LD9 D17/LD1
CD4/SD4 /LD8 D16/LD0 D8/RD8 D0/RD0 D16 D8 D0
CD3/SD3 HACPCML0 /LD15 /LD7
CD2/SD2 /LD14 /LD6
CD1/SD1 /LD13 /LD5
D15/RD15 D14/RD14 D13/RD13 D12/RD12 D11/RD11 D10/RD10 D9/RD9 D7/RD7 HACPCMR0 D15 D7 HACTIER0 D6/RD6 D14 D6 D5/RD5 D13 D5 D4/RD4 D12 D4 D3/RD3 D19 D11 D3 D2/RD2 D18 D10 D2 D1/RD1 D17 D9 D1
PLTFRQIE PRTFRQIE
PLTFUNIE PRTFUNIE
Rev. 1.0, 02/03, page 1168 of 1294
Abbrev.
HACTSR0
Bit 31/ 23/15/7
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
PRTFRQ
Bit 27/ 19/11/3

Bit 26/ 18/10/2

Bit 25/ 17/9/ 1
PLTFUN
Bit 24/ 16/8/0
PRTFUN RXDMAL_ EN
Module
HAC(0)
CMDAMT CMDDMT PLTFRQ STARYIE STARY STDRYIE
HACRIER0

PLRFRQIE PRRFRQIE TX12_ ATOMIC
PLRFOVIE PRRFOVIE STDRY PLRFOV PLRFRQ PRRFOV PRRFRQ
HACRSR0

HACACR0
DMARX16 DMATX16
TXDMAL_ RXDMAR_ TXDMAR_ EN HACCR1 CR HACCSAR1 CA3/SA3 SLREQ7 HACCSDR1 EN CA2/SA2 SLREQ8 EN ST CA1/SA1 SLREQ9 CA0/SA0

CDRT RW SLREQ3
WMRT CA6/SA6 SLREQ4
CA5/SA5 SLREQ5
CA4/SA4 SLREQ6 HAC(1)
SLREQ10 SLREQ11 SLREQ12 CD8/SD8 CD0/SD0 /LD12 /LD4
CD15/SD15 CD14/SD14 CD13/SD13 CD12/SD12
CD11/SD11 CD10/SD10 CD9/SD9
CD7/SD7 /LD11 D19/LD3
CD6/SD6 /LD10 D18/LD2
CD5/SD5 /LD9 D17/LD1
CD4/SD4 /LD8 D16/LD0 D8/RD8 D0/RD0
CD3/SD3 HACPCML1 /LD15 /LD7
CD2/SD2 /LD14 /LD6
CD1/SD1 /LD13 /LD5
D15/RD15 D14/RD14 D13/RD13 D12/RD12 D11/RD11 D10/RD10 D9/RD9 D7/RD7 D6/RD6 D5/RD5 D4/RD4 D3/RD3 D2/RD2 D1/RD1
Rev. 1.0, 02/03, page 1169 of 1294
Abbrev.
HACPCMR1
Bit 31/ 23/15/7
D15 D7
Bit 30/ 22/14/6
D14 D6
Bit 29/ 21/13/5
D13 D5
Bit 28/ 20/12/4
D12 D4
Bit 27/ 19/11/3
D19 D11 D3
Bit 26/ 18/10/2
D18 D10 D2
Bit 25/ 17/9/ 1
D17 D9 D1
Bit 24/ 16/8/0
D16 D8 D0
Module
HAC(1)
HACTIER1

PLTFRQIE PRTFRQIE PRTFRQ
PLTFUNIE PRTFUNIE PLTFUN PRTFUN RXDMAL_ EN
HACTSR1
CMDAMT CMDDMT PLTFRQ STARYIE STARY STDRYIE
HACRIER1

PLRFRQIE PRRFRQIE TX12_ ATOMIC
PLRFOVIE PRRFOVIE STDRY PLRFOV PLRFRQ PRRFOV PRRFRQ
HACRSR1

HACACR1
DMARX16 DMATX16
TXDMAL_ RXDMAR_ TXDMAR_ EN CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR Start CRC CMDOFF EN Host CRC EN INDEX CRC INDEX CRC
INDEX CRC
INDEX CRC
INDEX CRC
INDEX End START MMCIF
RD_CONTI DATAEN
Rev. 1.0, 02/03, page 1170 of 1294
Abbrev.
CSTR
Bit 31/ 23/15/7
BUSY
Bit 30/ 22/14/6
Bit 29/ 21/13/5
Bit 28/ 20/12/4
CWRE
Bit 27/ 19/11/3
DTBUSY
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
REQ
Module
MMCIF
FIFO_FULL FIFO_ EMPTY
DTBUSY_ TU
INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR TBCR MODER CMDTYR RSPTYR RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 DTOUTR
FEIE INTRQ2E FEI CLKON RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR
FFIE INTRQ1E FFI RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
DRPIE INTRQ0E DRPI RTY5 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
DTIE DTI TY4 RTY4 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
CRPIE CRPI C3 TY3 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
CMDIE
DBSYIE
CTERIE CTERI CSEL0 CTSEL0 C0 MODE TY0 RTY0 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
CRCERIE DTERIE CMDI CRCERI CSEL2 C2 TY2 RTY2 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR DBSYI DTERI CSEL1 CTSEL1 C1 TY1 RTY1 RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR RSPR DTOUTR DTOUTR DR DR
DR
DR DR
Rev. 1.0, 02/03, page 1171 of 1294
Abbrev.
FIFOCLR DMACR INTCR2 INTSTR2 RDTIMSEL MFIIDX
Bit 31/ 23/15/7
FIFOCLR DMAEN REG5
Bit 30/ 22/14/6
FIFOCLR REG4
Bit 29/ 21/13/5
FIFOCLR REG3
Bit 28/ 20/12/4
FIFOCLR REG2
Bit 27/ 19/11/3
FIFOCLR REG1
Bit 26/ 18/10/2
FIFOCLR SET2 REG0
Bit 25/ 17/9/ 1
FIFOCLR SET1
Bit 24/ 16/8/0
FIFOCLR SET0 FRDYIE
Module
MMCIF
FRDY_TU FRDYI BYTE1 RTSEL BYTE0 MFI
MFIGSR

STATUS7 STATUS6 STATUS5 STATUS4 STATUS3 STATUS2 STATUS1 STATUS0 MFISCR MFIMCR LOCK MFIIICR IIC6 MFIEICR EIC6 MFIADR A7 SCRMD2 IIC5 EIC5 A6 WT IIC4 EIC4 A5 SCRMD0 IIC3 EIC3 A4 RD IIC2 EIC2 A3 IIC1 EIC1 A10 A2 EDN IIC0 EIC0 A9 BO AI/AD IIR EIR A8
Rev. 1.0, 02/03, page 1172 of 1294
Abbrev.
MFIDATA
Bit 31/ 23/15/7
MFIDATA 31 MFIDATA 23 MFIDATA 15 MFIDATA 7
Bit 30/ 22/14/6
MFIDATA 30 MFIDATA 22 MFIDATA 14 MFIDATA 6 TI6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE CKSL0
Bit 29/ 21/13/5
MFIDATA 29 MFIDATA 21 MFIDATA 13 MFIDATA 5 TI5 AD7 AD7 AD7 AD7 ADST MDS1
Bit 28/ 20/12/4
MFIDATA 28 MFIDATA 20 MFIDATA 12 MFIDATA 4 TI4 AD6 AD6 AD6 AD6 DMASL MDS0
Bit 27/ 19/11/3
MFIDATA 27 MFIDATA 19 MFIDATA 11 MFIDATA 3 TI3 AD5 AD5 AD5 AD5 TRGE1
Bit 26/ 18/10/2
MFIDATA 26 MFIDATA 18 MFIDATA 10 MFIDATA 2 TI2 AD4 AD4 AD4 AD4 TRGE0
Bit 25/ 17/9/ 1
MFIDATA 25 MFIDATA 17 MFIDATA 9 MFIDATA 1 TI1 AD3 AD3 AD3 AD3 CH1
Bit 24/ 16/8/0
MFIDATA 24 MFIDATA 16 MFIDATA 8 MFIDATA 0 TI0 INTREQ AD2 AD2 AD2 AD2 CH0
Module
MFI
MFRAM Start

MFRAM End

SDIR
TI7
H-UDI
SDDR

SDINT

ADDRA
AD9 AD1
ADC
ADDRB
AD9 AD1
ADDRC
AD9 AD1
ADDRD
AD9 AD1
ADCSR
ADF CKSL1
Rev. 1.0, 02/03, page 1173 of 1294
Abbrev.
LDICKR
Bit 31/ 23/15/7

Bit 30/ 22/14/6
CL1POL
Bit 29/ 21/13/5
ICKSEL1 DISPPOL MIFTYP5
Bit 28/ 20/12/4
ICKSEL0 DCDR4 DPOL MIFTYP4
Bit 27/ 19/11/3
DCDR3 MIFTYP3
Bit 26/ 18/10/2
DCDR2 MCNT MIFTYP2
Bit 25/ 17/9/ 1
DCDR1 CL1CNT MIFTYP1
Bit 24/ 16/8/0
DCDR0 CL2CNT MIFTYP0 PABD
Module
LCDC
LDMTR
FLMPOL
LDDFR

DSPCOLOR6 DSPCOLOR5 DSPCOLOR4 DSPCOLOR3 DSPCOLOR2 DSPCOLOR1 DSPCOLOR0
LDSMR

SAU22 SAU14 SAU6 SAL22 SAL14 SAL6 LAO14 LAO6
ROT SAU21 SAU13 SAU5 SAL21 SAL13 SAL5 LAO13 LAO5
SAU20 SAU12 SAU4 SAL20 SAL12 SAL4 LAO12 LAO4 PALS
SAU19 SAU11 SAU3 SAL19 SAL11 SAL3 LAO11 LAO3
SAU18 SAU10 SAU2 SAL18 SAL10 SAL2 LAO10 LAO2
SAU25 SAU17 SAU9 SAU1 SAL25 SAL17 SAL9 SAL1 LAO9 LAO1
SAU24 SAU16 SAU8 SAU0 SAL24 SAL16 SAL8 SAL0 LAO8 LAO0 PALEN
LDSARU
SAU23 SAU15 SAU7
LDSARL
SAL23 SAL15 SAL7
LDLAOR
LAO15 LAO7
LDPALCR

LDPR00-FF
PALDnn_23 PALDnn_22 PALDnn_21 PALDnn_20 PALDnn_19 PALDnn_18 PALDnn_17 PALDnn_16 PALDnn_15 PALDnn_14 PALDnn_13 PALDnn_12 PALDnn_11 PALDnn_10 PALDnn_9 PALDnn_8 PALDnn_7 PALDnn_6 PALDnn_5 PALDnn_4 PALDnn_3 PALDnn_2 PALDnn_1 PALDnn_0
LDHCNR
HDCN7 HTCN7
HDCN6 HTCN6 HSYNW2 HSYNP6 VDLN6 VTLN6
HDCN5 HTCN5 HSYNW1 HSYNP5 VDLN5 VTLN5
HDCN4 HTCN4 HSYNW0 HSYNP4 VDLN4 VTLN4
HDCN3 HTCN3 HSYNP3 VDLN3 VTLN3
HDCN2 HTCN2 HSYNP2 VDLN10 VDLN2 VTLN10 VTLN2
HDCN1 HTCN1 HSYNP1 VDLN9 VDLN1 VTLN9 VTLN1
HDCN0 HTCN0 HSYNP0 VDLN8 VDLN0 VTLN8 VTLN0
LDHSYNR
HSYNW3 HSYNP7
LDVDLNR
VDLN7
LDVTLNR
VTLN7
Rev. 1.0, 02/03, page 1174 of 1294
Abbrev.
LDVSYNR
Bit 31/ 23/15/7
VSYNW3 VSYNP7
Bit 30/ 22/14/6
VSYNW2 VSYNP6 ONC2 VCPE ONA2 OFFE2 BASA6 BASB6 BAA30 BAA22 BAA14 BAA6 SZA2 BAB30 BAB22 BAB14 BAB6 SZB2 BDB30 BDB22 BDB14 BDB6
Bit 29/ 21/13/5
VSYNW1 VSYNP5 ONC1 VEPE ONA1 OFFE1 BASA5 BASB5 BAA29 BAA21 BAA13 BAA5 IDA1 BAB29 BAB21 BAB13 BAB5 IDB1 BDB29 BDB21 BDB13 BDB5
Bit 28/ 20/12/4
VSYNW0 VSYNP4 ACLN4 VINTSEL ONC0 DONE ONA0 OFFE0 DON2 BASA4 BASB4 BAA28 BAA20 BAA12 BAA4 IDA0 BAB28 BAB20 BAB12 BAB4 IDB0 BDB28 BDB20 BDB12 BDB4
Bit 27/ 19/11/3
VSYNP3 ACLN3 OFFD3 ONB3 OFFF3 BASA3 BASB3 BAA27 BAA19 BAA11 BAA3 BAMA2 RWA1 BAB27 BAB19 BAB11 BAB3 BAMB2 RWB1 BDB27 BDB19 BDB11 BDB3
Bit 26/ 18/10/2
Bit 25/ 17/9/ 1
Bit 24/ 16/8/0
VSYNP8 VSYNP0 ACLN0 VINTE VINTS OFFD0 LPS0 ONB0 OFFF0 DON BASA0 BASB0 BAA24 BAA16 BAA8 BAA0 BAMA0 SZA0 BAB24 BAB16 BAB8 BAB0 BAMB0 SZB0 BDB24 BDB16 BDB8 BDB0
Module
LCDC
VSYNP10 VSYNP9 VSYNP2 ACLN2 OFFD2 ONB2 OFFF2 BASA2 BASB2 BAA26 BAA18 BAA10 BAA2 BASMA RWA0 BAB26 BAB18 BAB10 BAB2 BASMB RWB0 BDB26 BDB18 BDB10 BDB2 VSYNP1 ACLN1 OFFD1 LPS1 ONB1 OFFF1 BASA1 BASB1 BAA25 BAA17 BAA9 BAA1 BAMA1 SZA1 BAB25 BAB17 BAB9 BAB1 BAMB1 SZB1 BDB25 BDB17 BDB9 BDB1
LDACLNR

LDINTR

LDPMMR
ONC3
LDPSPR
ONA3 OFFE3
LDCNTR

BASRA BASRB BARA
BASA7 BASB7 BAA31 BAA23 BAA15 BAA7
UBC
BAMRA BBRA

BARB
BAB31 BAB23 BAB15 BAB7
BAMRB BBRB

BDRB
BDB31 BDB23 BDB15 BDB7
Rev. 1.0, 02/03, page 1175 of 1294
Abbrev.
BDMRB
Bit 31/ 23/15/7
BDMB31 BDMB23 BDMB15 BDMB7
Bit 30/ 22/14/6
BDMB30 BDMB22 BDMB14 BDMB6 CMFB PCBB
Bit 29/ 21/13/5
BDMB29 BDMB21 BDMB13 BDMB5
Bit 28/ 20/12/4
BDMB28 BDMB20 BDMB12 BDMB4
Bit 27/ 19/11/3
BDMB27 BDMB19 BDMB11 BDMB3 SEQ
Bit 26/ 18/10/2
BDMB26 BDMB18 BDMB10 BDMB2 PCBA
Bit 25/ 17/9/ 1
BDMB25 BDMB17 BDMB9 BDMB1
Bit 24/ 16/8/0
BDMB24 BDMB16 BDMB8 BDMB0 UBDE
Module
UBC
BRCR
CMFA DBEB
Rev. 1.0, 02/03, page 1176 of 1294
32.3
Register States in Each Operating Mode
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined Undefined Retained Undefined H'0000 0000 H'0000 0000 Undefined Undefined Undefined H'0000 0020 Undefined H'0000* H'8000* H'0000 H'0000 H'0000 H'DA74 Retained Retained Retained Retained Retained Retained Retained Retained -- --
1
Standby by Software/ by Hardware Undefined Undefined Undefined Undefined Undefined H'0000 0000 H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined H'0000* H'8000* H'0000 H'0000 H'0000 H'DA74 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'F3FF 7FFF H'00FF FFFF -- --
1
Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained -- --
Module MMU
Abbrev. PTEH PTEL PTEA TTB TEA MMUCR
H-UDI Undefined Undefined Undefined Undefined Undefined H'0000 0000 H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined H'0000* H'8000*
1
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained -- --
Cache
CCR QACR0 QACR1
Exception handling
TRA EXPEVT INTEVT
INTC
ICR
2
2
2
IPRA IPRB IPRC IPRD INTPRI00 INTPRI04 INTPRI08 INTPRI0C INTREQ00 INTREQ04 INTMSK00 INTMSK04 INTMSKCLR00 INTMSKCLR04
H'0000 H'0000 H'0000 H'DA74 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'F3FF 7FFF H'00FF FFFF -- --
Rev. 1.0, 02/03, page 1177 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module BSC Abbrev. BCR1 BCR2 BCR3 BCR4 WCR1 WCR2 WCR3 WCR4 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR2 SDMR3 DMAC Channel 0 SAR0 DAR0 DMATCR0 CHCR0 DMAC Channel 1 SAR1 DAR1 DMATCR1 CHCR1 DMAC Channel 2 SAR2 DAR2 DMATCR2 CHCR2 H-UDI H'0000 0000 H'3FFC H'0001 H'0000 0000 H'7777 7777 H'FFFE EFFF H'0777 7777 H'0000 0000 H'0000 0000 H'0000 H'0000 H'0000 H'0000 H'0000 Write only Write only Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Undefined Undefined Undefined RESET Pin/WDT/ by Sleep Multiple Exception Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'0000 0000 H'3FFC H'0001 H'0000 0000 H'7777 7777 H'FFFE EFFF H'0777 7777 H'0000 0000 H'0000 0000 H'0000 H'0000 H'0000 H'0000 H'0000 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000
Rev. 1.0, 02/03, page 1178 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module DMAC Channel 3 Abbrev. SAR3 DAR3 DMATCR3 CHCR3 DMAC Channel 4 SAR4 DAR4 DMATCR4 CHCR4 DMAC Channel 5 SAR5 DAR5 DMATCR5 CHCR5 DMAC Channel 6 SAR6 DAR6 DMATCR6 CHCR6 DMAC Channel 7 SAR7 DAR7 DMATCR7 CHCR7 DMAC Common DMAOR DMARSRA DMARSRB DMAC DMABRG DMARCR DMABRGCR DMAATXSAR0 DMAARXDAR0 DMAATXTCR0 DMAARXTCR0 DMAACR0 DMAATXTCNT0 H-UDI Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined Undefined Undefined H'0000 0000 Undefined RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined Undefined Undefined H'0000 0000 Undefined Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 Undefined Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined Undefined Undefined H'0000 0000 Undefined Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1179 of 1294
Power-on Reset Manual Reset by Sleep by RESET RESET Pin/WDT/ Module DMAC DMABRG Abbrev. DMAARXTCNT0 DMAATXSAR1 DMAARXDAR1 DMAATXTCR1 DMAARXTCR1 DMAACR1 DMAATXTCNT1 DMAARXTCNT1 DMAUSAR DMAUDAR
DMAURWSZ
RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined Undefined Undefined Undefined H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Retained Retained Retained Retained Retained Retained Retained Retained H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware Undefined Undefined Undefined Undefined Undefined H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 * / Retained H'0000 0001 H'0000 0000
3
H-UDI Undefined Undefined Undefined Undefined Undefined H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 * / Retained H'0000 0001 H'0000 0000 H'00/ Retained H'00/ Retained H'00 H'00 H'0000 0000 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000
3
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
DMAUCR CPG FRQCR DCKDR MCKCR WDT WTCNT WTCSR Power-down STBCR STBCR2 CLKSTP00 CLKSTPCLR00 TMU Common TSTR TMU Channel 0 TCOR0 TCNT0 TCR0 TMU Channel 1 TCOR1 TCNT1 TCR1
H'00/ Retained Retained H'00/ Retained Retained H'00 H'00 H'0000 0000 H'00 H'FFFF FFFF H'FFFF FFFF H'0000 H'FFFF FFFF H'FFFF FFFF H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1180 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module TMU Channel 2 Abbrev. TCOR2 TCNT2 TCR2 TCPR2 CMT Common
CMTCFG CMTFRT CMTCTL CMTIRQS
RESET Pin/WDT/ by Sleep Multiple Exception H'FFFF FFFF H'FFFF FFFF H'0000 Retained H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
4
Standby by Software/ by Hardware H'FFFF FFFF H'FFFF FFFF H'0000 Retained H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*
4
H-UDI H'FFFF FFFF H'FFFF FFFF H'0000 Retained H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000*
4
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
CMT Channel 0
CMTCH0T CMTCH0ST CMTCH0C
CMT Channel 1
CMTCH1T CMTCH1ST CMTCH1C
CMT Channel 2
CMTCH2T CMTCH2ST CMTCH2C
CMT Channel 3
CMTCH3T CMTCH3ST CMTCH3C
SCIF Channel 0
SCSMR0 SCBRR0 SCSCR0 SCFTDR0 SCFSR0 SCFRDR0 SCFCR0 SCTFDR0 SCRFDR0 SCSPTR0
H'0000*
Retained
Rev. 1.0, 02/03, page 1181 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module SCIF Channel 0 SCIF Channel 1 Abbrev.
SCLSR0 SCRER0 SCSMR1 SCBRR1 SCSCR1 SCFTDR1 SCFSR1 SCFRDR1 SCFCR1 SCTFDR1 SCRFDR1 SCSPTR1 SCLSR1 SCRER1
RESET Pin/WDT/ by Sleep Multiple Exception H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
5
Standby by Software/ by Hardware H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'20 H'07 H'00 H'FF H'84
5 5
H-UDI H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'0000 H'FF H'0000 Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'20 H'07 H'00 H'FF H'84
5 5
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000* H'0000 H'0000 H'0000 H'FF H'0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
SCIF Channel 2
SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCFSR2 SCFRDR2 SCFCR2 SCTFDR2 SCRFDR2 SCSPTR2 SCLSR2 SCRER2
Undefined H'0060 Undefined H'0000 H'0000 H'0000 H'0000* H'0000 H'0000 H'20 H'07 H'00 H'FF H'84
5
Retained Retained Retained Retained Retained Retained Retained Retained
SIM
SISMR SIBRR SISCR SITDR SISSR
Rev. 1.0, 02/03, page 1182 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module SIM Abbrev. SIRDR SISCMR SISC2R SIWAIT SIGRD SISMPL IC Channel 0
2
RESET Pin/WDT/ by Sleep Multiple Exception H'00 H'01 H'00 H'0000 H'00 H'0173 H'0000 0000
6
Standby by Software/ by Hardware H'00 H'01 H'00 H'0000 H'00 H'0173 H'0000 0000 H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
6 6
Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained
6
H-UDI H'00 H'01 H'00 H'0000 H'00 H'0173 H'0000 0000 H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
6
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
ICSCR0 ICMCR0 ICSSR0 ICMSR0 ICSIER0 ICMIER0 ICCCR0 ICSAR0 ICMAR0 ICRXD0 ICTXD0 ICFCR0 ICFSR0 ICFIER0 ICRFDR0 ICTFDR0
H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000* H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
IC Channel 1
2
ICSCR1 ICMCR1 ICSSR1 ICMSR1 ICSIER1 ICMIER1 ICCCR1 ICSAR1 ICMAR1
6
Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1183 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module IC Channel 1
2
RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0010 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 2EDF H'0000 0000 H'0000 0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0010 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 2EDF H'0000 0000 H'0000 0000 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Abbrev. ICRXD1 ICTXD1 ICFCR1 ICFSR1 ICFIER1 ICRFDR1 ICTFDR1
H-UDI Undefined Undefined H'0000 0000 H'0000 0001 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0000 H0200 0003 H'0000 0000 H'0000 0000 H'0000 0010 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 2EDF H'0000 0000 H'0000 0000
SSI Channel 0
SSICR0 SSISR0 SSITDR0 SSIRDR0
SSI Channel 1
SSICR1 SSISR1 SSITDR1 SSIRDR1
USB
HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber
Rev. 1.0, 02/03, page 1184 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module USB Abbrev. HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 Shared memory Start Shared memory End HCAN2 Channel 0 CAN0MCR CAN0GSR CAN0BCR1 CAN0BCR0 CAN0IRR CAN0IMR CAN0TECREC CAN0TXPR1 CAN0TXPR0 CAN0TXCR1 CAN0TXCR0 CAN0TXACK1 CAN0TXACK0 CAN0ABACK1 CAN0ABACK0 CAN0RXPR1 CAN0RXPR0 CAN0RFPR1 CAN0RFPR0 CAN0MBIMR1 CAN0MBIMR0 CAN0UMSR1 CAN0UMSR0 H-UDI H'0000 0000 H'0000 0628 H'0200 1202 H'0000 0000 H'0000 0000 H'0000 0100 Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 RESET Pin/WDT/ by Sleep Multiple Exception H'0000 0000 H'0000 0628 H'0200 1202 H'0000 0000 H'0000 0000 H'0000 0100 Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'0000 0000 H'0000 0628 H'0200 1202 H'0000 0000 H'0000 0000 H'0000 0100 Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1185 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module HCAN2 Channel 0 Abbrev. CAN0TCNTR CAN0TCR CAN0TCMR CAN0MB0 CAN0MB1 CAN0MB2 CAN0MB3 CAN0MB4 CAN0MB5 CAN0MB6 CAN0MB7 CAN0MB8 CAN0MB9 CAN0MB10 CAN0MB11 CAN0MB12 CAN0MB13 CAN0MB14 CAN0MB15 CAN0MB16 CAN0MB17 CAN0MB18 CAN0MB19 CAN0MB20 CAN0MB21 CAN0MB22 CAN0MB23 CAN0MB24 CAN0MB25 CAN0MB26 CAN0MB27 H-UDI H'0000 H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET Pin/WDT/ by Sleep Multiple Exception H'0000 H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'0000 H'0000 H'0000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1186 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module HCAN2 Channel 0 Abbrev. CAN0MB28 CAN0MB29 CAN0MB30 CAN0MB31 HCAN2 Channel 1 CAN1MCR CAN1GSR CAN1BCR1 CAN1BCR0 CAN1IRR CAN1IMR CAN1TECREC CAN1TXPR1 CAN1TXPR0 CAN1TXCR1 CAN1TXCR0 CAN1TXACK1 CAN1TXACK0 CAN1ABACK1 CAN1ABACK0 CAN1RXPR1 CAN1RXPR0 CAN1RFPR1 CAN1RFPR0 CAN1MBIMR1 CAN1MBIMR0 CAN1UMSR1 CAN1UMSR0 CAN1TCNTR CAN1TCR CAN1TCMR H-UDI Undefined Undefined Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware Undefined Undefined Undefined Undefined H'0001 H'000C H'0000 H'0000 H'0001 H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'0000 H'0000 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1187 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module HCAN2 Channel 1 Abbrev. CAN1MB0 CAN1MB1 CAN1MB2 CAN1MB3 CAN1MB4 CAN1MB5 CAN1MB6 CAN1MB7 CAN1MB8 CAN1MB9 CAN1MB10 CAN1MB11 CAN1MB12 CAN1MB13 CAN1MB14 CAN1MB15 CAN1MB16 CAN1MB17 CAN1MB18 CAN1MB19 CAN1MB20 CAN1MB21 CAN1MB22 CAN1MB23 CAN1MB24 CAN1MB25 CAN1MB26 CAN1MB27 CAN1MB28 CAN1MB29 CAN1MB30 CAN1MB31 H-UDI Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined RESET Pin/WDT/ by Sleep Multiple Exception Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1188 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module HSPI Abbrev. SPCR SPSR SPSCR SPTBR SPRBR PFC INPUPA DMAPCR SCIHZR IPSELR PAPUPR PBPUPR PCPUPR PDPUPR PEPUPR PFPUPR PGPUPR PHPUPR PJPUPR PKPUPR MDPUPR MODSELR PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR PKCR H-UDI H'0000 0000* H'0000 0120* H'0000 0040*
7
RESET Pin/WDT/ by Sleep Multiple Exception H'0000 0000* H'0000 0120* H'0000 0040*
7
Standby by Software/ by Hardware H'0000 0000* H'0000 0120* H'0000 0040*
7
Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Each Module Retained Retained Retained
7
7
7
7
7
7
H'0000 0000*7 H'0000 0000* H'FF00 H'A550 H'0000 H'0003 H'FC H'FE H'FF H'FF H'FF H'0F H'FF H'FF H'FC H'FC H'38 H'00 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'003C H'0000 H'0000
7
H'0000 0000*7 H'0000 0000*7 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0000 0000*7 Retained H'0000 0000*7 Retained H'FF00 H'A550 H'0000 H'0003 H'FC H'FE H'FF H'FF H'FF H'0F H'FF H'FF H'FC H'FC H'38 H'00 H'0000 H'0000 H'FFFF H'FFFF H'0000 H'0000 H'0000 H'003C H'0000 H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1189 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module PFC Abbrev. PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR PKDR GPIOIC HAC Channel 0 HACCR0 HACCSAR0 HACCSDR0 HACPCML0 HACPCMR0 HACTIER0 HACTSR0 HACRIER0 HACRSR0 HACACR0 HAC Channel 1 HACCR1 HACCSAR1 HACCSDR1 HACPCML1 HACPCMR1 HACTIER1 HACTSR1 HACRIER1 HACRSR1 HACACR1 H-UDI H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 RESET Pin/WDT/ by Sleep Multiple Exception Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 H'0000 0200 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'0000 0000 H'8400 0000 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1190 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module MMCIF Abbrev. CMDR0 CMDR1 CMDR2 CMDR3 CMDR4 CMDR5 CMDSTRT OPCR CSTR INTCR0 INTCR1 INTSTR0 INTSTR1 CLKON CTOCR TBCR MODER CMDTYR RSPTYR RSPR0 RSPR1 RSPR2 RSPR3 RSPR4 RSPR5 RSPR6 RSPR7 RSPR8 RSPR9 RSPR10 RSPR11 H-UDI H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0x H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 RESET Pin/WDT/ by Sleep Multiple Exception H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0x H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'0x H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1191 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module MMCIF Abbrev. RSPR12 RSPR13 RSPR14 RSPR15 RSPR16 DTOUTR DR FIFOCLR DMACR INTCR2 INTSTR2 RDTIMSEL MFI MFIIDX MFIGSR MFISCR MFIMCR MFIIICR MFIEICR MFIADR MFIDATA MFRAM Start MFRAM End H-UDI SDIR SDDR/SDDRH SDDRL SDINT ADC ADDRA ADDRB ADDRC ADDRD ADCSR H-UDI H'00 H'00 H'00 H'00 H'00 H'FFFF H'xxxx H'00 H'00 H'00 H'0x H'00 H'0000 H'0000 H'0040/H'0050* H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined H'FFFF*
12 8
RESET Pin/WDT/ by Sleep Multiple Exception H'00 H'00 H'00 H'00 H'00 H'FFFF H'xxxx H'00 H'00 H'00 H'0x H'00 H'0000 H'0000 H'0040/H'0050* H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined Retained Retained Retained Retained H'0000 H'0000 H'0000 H'0000 H'0040
8
Standby by Software/ by Hardware H'00 H'00 H'00 H'00 H'00 H'FFFF H'xxxx H'00 H'00 H'00 H'0x H'00 H'0000 H'0000
8
Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
H'0040/H'0050* Retained H'0000 H'0000 H'0000 H'0000 H'0000 Undefined Undefined H'FFFF*
12
Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained H'0000*9 H'0000*9 H'0000*9 H'0000*9 H'0040*
9
Undefined Undefined H'0000 H'0000 H'0000 H'0000 H'0000 H'0040
Undefined Undefined H'0000 H'0000 H'0000 H'0000 H'0000 H'0040
Rev. 1.0, 02/03, page 1192 of 1294
Power-on Reset Manual Reset by Sleep by RESET Pin/WDT/ Module LCDC Abbrev. LDICKR LDMTR LDDFR LDSMR LDSARU LDSARL LDLAOR LDPALCR LDPR00 to FF* LDHCNR LDHSYNR LDVDLNR LDVTLNR LDVSYNR LDACLNR LDINTR LDPMMR LDPSPR LDCNTR UBC BARA BASRA BAMRA BBRA BARB BASRB BAMRB BBRB BDRB BDMRB BRCR
10
RESET Pin/WDT/ by Sleep Multiple Exception H'0101 H'0109 H'000C H'0000 H'0C00 0000 H'0C00 0000 H'0280 H'0000 Undefined H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000 Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Instruction/ Deep Sleep Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Standby by Software/ by Hardware H'0101 H'0109 H'000C H'0000 H'0C00 0000 H'0C00 0000 H'0280 H'0000 Undefined H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000 Undefined Undefined Undefined H'0000 Undefined Undefined Undefined H'0000 Undefined Undefined H'0000*
11
H-UDI H'0101 H'0109 H'000C H'0000 H'0C00 0000 H'0C00 0000 H'0280 H'0000 Undefined H'4F52 H'0050 H'01DF H'01DF H'01DF H'000C H'0000 H'0010 H'F60F H'0000 Undefined Undefined Undefined H'0000 Undefined Undefined Undefined H'0000 Undefined Undefined H'0000*
11
Each Module Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained
Rev. 1.0, 02/03, page 1193 of 1294
Note:
1. The NMI pin is a low level. 2. The NMI pin is a high level. 3. The initial values of bits 11 to 9 are 1 and those of bits 8 to 0 are undefined when the RESET pin resets all of them. The values of bits 11 to 0 are retained when the WDT or the H-UDI resets all of them. 4. Bits 2 and 0 are undefined. 5. Bits 6, 4, 2,and 0 are undefined. 6. Bits 6 and 5 are undefined. 7. Reserved bits are read as undefined values. 8. 80-series interface: 0040; 68-series interface: 0050 9. Before entering module standby or software standby mode, check that A/D conversion is not in progress. If standby mode is entered while A/D conversion is in progress, correct register values are not guaranteed. 10. There are 256 LDPRxx: LDPR00, LDPR01, ..., LDPRFF. 11. Bits 10, 7, 6, and 3 are undefined. 12. Reserved bit are read as undefined values, For details, see each of the register descriptions.
Rev. 1.0, 02/03, page 1194 of 1294
Section 33 Electrical Characteristics
33.1 Absolute Maximum Ratings
Table 33.1 Absolute Maximum Ratings
Item I/O, CPG, ADC, USB power supply voltage Symbol VDDQ VDD-CPG AVCC-ADC Internal power supply voltage VDD VDD-PLL1/2/3 Input voltage Operating temperature Storage temperature Vin Topr Tstg -0.3 to VDDQ+0.3, -0.5 to 5.5*1 -40 to 85 -55 to 125 V C C -0.3 to 2.1 V Value -0.3 to 4.6 Unit V
Notes: 1. The LSI may be permanently damaged if the maximum ratings are exceeded. 2. The LSI may be permanently damaged if any of the VSS pins are not connected to GND. 3. For the powering-on and powering-off sequence, see Appendix F, Power-On and Power-Off Procedures. *1 For I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA.
Rev. 1.0, 02/03, page 1195 of 1294
33.2
DC Characteristics
Table 33.2 DC Characteristics (Ta=-40 to 85C) -
Item Power supply voltage Symbol VDDQ VDD-CPG AVCC-ADC VDD VDD-PLL1/2/3 1.4 1.5 1.6 Min. 3.0 Typ. Max. 3.3 3.6 Unit V Test Conditions Normal mode, sleep mode, deep-sleep mode, standby mode Normal mode, sleep mode, deep-sleep mode, standby mode Analog power supply current During A/D conversion During idle AIcc -- -- 6.0 0.2 7.5 2.0 mA A
Current Normal operation dissipation Sleep mode Standby mode
IDD
-- -- -- --
220 90 -- -- 70 25 -- -- --
730 160 250 500 190 50 530 800 VDDQ +0.3
mA A mA A V
Ick = 200MHz
Ta = 25C Ta > 50C Ick = 200MHz Bck = 67MHz Ta = 25 C Ta > 50 C
Normal operation Sleep mode Standby mode RESET, NMI, TRST, ASEBRK/BRKACK, MRESET, CA, SCIF2_RTS, USB_PENC, VEPWC/IRQ5, VCPWC/IRQ4, IRL3, IRL2, IRL1, IRL0, Reserved/AUDATA[3] I2C1_SCL, I2C1_SDA I2C0_SCL, I2C0_SDA USB_DP, USB_DM Other input pins
IDDQ
-- -- -- --
Input voltage
VIH
VDDQ x0.9
VDDQ x0.8 VDDQ x0.7 VDDQ x0.8
-- -- --
5.5 VDDQ +0.3 VDDQ +0.3
Rev. 1.0, 02/03, page 1196 of 1294
Item Input voltage RESET, NMI, TRST, ASEBRK/BRKACK, MRESET, CA, SCIF2_RTS, USB_PENC, VEPWC/IRQ5, VCPWC/IRQ4, IRL3, IRL2, IRL1, IRL0, Reserved/AUDATA[3] I2C1_SCL, I2C1_SDA I2C0_SCL, I2C0_SDA USB_DP, USB_DM Other input pins Input leak current All input pins
Symbol Min. VIL -0.3
Typ. Max. VDDQ x0.1
Unit V
Test Conditions
-0.5 -0.3 -0.3 |lin| |lsti| VOH VOL VDDQ x0.8 0 Rpull CUSB CADC CL 20
60
VDDQ x0.1 VDDQ x0.2 VDDQ x0.2 1 1 0.4 VDDQ x0.2 180 20 20 10 k pF A A V VIN = 0.5 to VDDQ -0.5V VIN = 0.5 to VDDQ -0.5V
Three-state I/O, all output pins leak current (off condition) Output voltage All pins I2C1_SCL, I2C1_SDA I2C0_SCL, I2C0_SDA Other pins Pull-up resistance All pins
Pin USB_DP, USB_DM capacitance AN3, AN2, AN1, AN0 Other pins
Notes: 1. Regardless of whether or not the PLL is used, connect VDDQ and AVCC_ADC to VDD-CPG, VDD-PLL 1/2/3 to VDD, and VSS-CPG and VSS-PLL 1/2/3 to GND. The LSI may be damage when not filling this. 2. Regardless of whether or not the A/D converter is used, connect VDDQ and VDD-CPG to AVCC-ADC, and AVSS-ADC to GND. The LSI may be damage when not filling this. 3. The current dissipation values are for VIH min = VDDQ -0.5 V and VIL max = 0.5 V with all output pins unload. 4. IDD is the sum total value of the current of VDD and VDD-PLL 1/2/3. 5. IDDQ is the sum total value of the current of VDDQ and VDD-CPG.
Rev. 1.0, 02/03, page 1197 of 1294
Table 33.3 Permissible Output Currents
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Symbol IOL IOL -IOH |-IOH| Min. Typ. Max. 2 120 2 40 mA Unit mA
Note: To protect chip reliability, do not exceed the output current values in table 33.3.
33.3
AC Characteristics
In principle, this LSI's input should be synchronous. Unless specified otherwise, ensure that the setup time and hold times for each input signal are observed. Table 33.4 Clock Timing
Item Operating frequency CPU, FPU, cache, TLB External bus Peripheral modules Symbol f Min. 1 1 1 Typ. Max. 200 67 34 Unit MHz
Rev. 1.0, 02/03, page 1198 of 1294
33.3.1
Clock and Control Signal Timing
Table 33.5 Clock and Control Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Item EXTAL clock PLL1 6-times/PLL2 operation input PLL1 12-times/PLL2 operation frequency PLL1/PLL2 not operating DCK clock output DCK clock output cycle time DCK clock output low-level pulse width DCK clock output high-level pulse width DCK clock output rise time DCK clock output fall time DCK clock output low-level pulse width DCK clock output high-level pulse width EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width EXTAL clock input rise time EXTAL clock input fall time CKIO clock output PLL1/PLL2 operation PLL1/PLL2 not operating tCKOcyc tCKOL1 tCKOH1 tCKOr tCKOf tCKOL2 tCKOH2 tOSC1 tMDRS tMDRH tRESW Symbol Min. fEX 16 16 1 fOP2 tDCcyc tDCOL1 tDCOH1 tDCOr tDCOf tDCOL2 tDCOH2 tEXcyc tEXL tEXH tEXr tEXf fOP 22 15 1 1 3 3 30 3.5 3.5 25 1 15 1 1 3 3 10 10 3 20 20 Max. Unit 34 22 34 67 45 3 3 4 4 67 34 1000 ns 3 3 ns ns ns ns ns ns ms ms tcyc ns tcyc 33.2 33.2 33.2 33.2 33.2 33.3 33.3 33.6, 33.8 33.6, 33.8 33.14 33.6, 33.8 33.6, 33.7, 33.8, 33.9 MHz ns ns ns ns ns ns ns 33.4 33.4 33.4 33.4 33.4 33.5 33.5 33.1 33.1 33.1 33.1 33.1 MHz Figure
1000 ns ns ns ns ns MHz
CKIO clock output cycle time CKIO clock output low-level pulse width CKIO clock output high-level pulse width CKIO clock output rise time CKIO clock output fall time CKIO clock output low-level pulse width CKIO clock output high-level pulse width Power-on oscillation settling time
Power-on oscillation settling time/mode setting tOSCMD MD reset setup time MD reset hold time RESET assert time
Rev. 1.0, 02/03, page 1199 of 1294
Item PLL synchronization settling time Standby return oscillation settling time 1 Standby return oscillation settling time 2 Standby return oscillation settling time 3 Standby return oscillation settling time 1* Standby return oscillation settling time 2* Standby return oscillation settling time 3* IRL interrupt determination time (standby mode) TRST reset hold time RESET input rise time RESET input fall time
Symbol Min. tPLL tOSC2 tOSC3 tOSC4 tOSC2 tOSC3 tOSC4 tIRLSTB tTRSTRH tPRr tPRf 200 5 5 5 2 2 2 0
Max. Unit 200 1 1 s ms ms ms ms ms ms s ns s s
Figure 33.12, 33.13 33.7, 33.9 33.10 33.11 33.7, 33.9 33.10 33.11 33.13 33.6, 33.8 33.14 33.14
Notes: 1. When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34MHz. when a 3rd overtone crystal resonator is used, an external tank circuit is necessary. 2. As there is feedback from the CKIO pin when PLL2 is operating, the load copacitance connected to the CKIO pin should be a maximum of 50 pF. 3. tcyc shows 1 cycle time of a CKIO clock.
* When the oscillation settling time of the crystal resonator is 1ms or less.
tEXcyc
tEXH
tEXL
VIH 1/2VDDQ
VIH VIL tEXf VIL
VIH 1/2VDDQ
tEXr
Note: When the clock is input from the EXTAL pin.
Figure 33.1 EXTAL Clock Input Timing
Rev. 1.0, 02/03, page 1200 of 1294
tCKOcyc
tCKOH1
tCKOL1
VOH 1/2VDDQ
VOH VOL tCKOf VOL
VOH 1/2VDDQ
tCKOr
Figure 33.2 CKIO Clock Output Timing (1)
tCKOH2
tCKOL2
1.5V
1.5V
1.5V
Figure 33.3 CKIO Clock Output Timing (2)
tDCcyc
tDCOH1
tDCOL1
VOH 1/2VDDQ
VOH VOL tDCOf VOL
VOH 1/2VDDQ
tDCOr
Figure 33.4 DCK Clock Output Timing (1)
tDCOH2 tDCOL2
1.5V
1.5V
1.5V
Figure 33.5 DCK Clock Output Timing (2)
Rev. 1.0, 02/03, page 1201 of 1294
Stable oscillation CKIO internal clock
VDD min tRESW tOSC1 RESET tOSCMD MD8, MD7, MD2-MD0 tTRSTRH TRST tMDRH
CA (High)
Notes: 1. Oscillation settling time when on-chip resonator is used 2. PLL2 not operating
Figure 33.6 Power-On Oscillation Settling Time (1)
During Standby Stable oscillation
CKIO internal clock tRESW tOSC2 RESET or MRESET
Notes: 1. Oscillation settling time when on-chip resonator is used. 2. PLL2 not operating
MRESET) Figure 33.7 Standby Return Oscillation Settling Time (Return by RESET or MRESET (1)
Rev. 1.0, 02/03, page 1202 of 1294
Stable oscillation Internal clock
VDD
VDD min tRESW tOSC1
RESET tOSCMD MD8, MD7, MD2-MD0 tTRSTRH TRST tMDRH
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used. 2. PLL2 operating
Figure 33.8 Power-On Oscillation Settling Time (2)
Stable oscillation
During Standby Internal clock tRESW tOSC2 RESET or MRESET
CKIO
Notes: 1. Oscillation settling time when on-chip resonator is used. 2. PLL2 operating
Figure 33.9 Standby Return Oscillation Settling Time (Return by RESET or MRESET) (2)
Rev. 1.0, 02/03, page 1203 of 1294
During Standby CKIO internal clock tOSC3
Stable oscillation
NMI
Note: Oscillation settling time when on-chip resonator is used.
Figure 33.10 Standby Return Oscillation Settling Time (Return by NMI)
During standby CKIO internal clock Stable Oscillation
tOSC4
IRL3-IRL0
Note: Oscillation settling time when on-chip resonator is used.
IRL0) Figure 33.11 Standby Return Oscillation Settling Time (Return by IRL3 to IRL0
Reset or NMI interrupt request Stable input clock Stable input clock
EXTAL input PLL synchronization PLL output, CKIO output tPLL x 2 PLL synchronization
Internal clock
STATUS1, STATUS0
normal
standby
normal
Note: When an external clock is input from EXTAL
RESET, Figure 33.12 PLL Synchronization Settling Time in Case of RESET MRESET or NMI Interrupt
Rev. 1.0, 02/03, page 1204 of 1294
IRL3-IRL0 interrupt request Stable input clock Stable input clock
EXTAL input PLL synchronization PLL output, CKIO output tIRLSTB tPLL x 2 PLL synchronization
Internal clock
STATUS1, STATUS0
normal
standby
normal
Note: When an external clock is input from EXTAL
Figure 33.13 PLL Synchronization Settling Time in Case of IRL Interrupt
tPRf tPRr
RESET tMDRS MD6-MD3 tMDRH
Figure 33.14 MD pins Setup/Hold Timing
Rev. 1.0, 02/03, page 1205 of 1294
33.3.2
Control Signal Timing
Table 33.6 Control Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Item BREQ setup time BREQ hold time BACK delay time Bus tri-state delay time Bus tri-state delay time to standby mode Bus buffer on time Bus buffer on time from standby STATUS 0/1 delay time STATUS 0/1 delay time to standby Note: tcyc shows 1 cycle time of a CKIO clock. Symbol tBREQS tBREQH tBACKD tBOFF1 tBOFF2 tBON1 tBON2 tSTD1 tSTD2 Min. 3 1.5 Max. 6 12 2 12 2 6 2 Unit ns ns ns ns tcyc ns tcyc ns tcyc Figure 33.15 33.15 33.15 33.15 33.16 33.15 33.16 33.16 33.16
CKIO tBREQH BREQ tBACKD tBACKD tBREQS tBREQH tBREQS
BACK
A[25:0], CSn, BS, RD/WR, CE2A, CE2B, RAS, WEn, RD, CASn
tBOFF1
tBON1
Figure 33.15 Control Signal Timing
Rev. 1.0, 02/03, page 1206 of 1294
Normal operation
Standby mode
Normal operation
CKIO
STATUS1, STATUS0
normal tSTD2
standby tSTD1
normal
CSn, RD, RD/WR, WEn, BS, RAS CE2A, CE2B, CASn
tBOFF2
tBON2
A25-A0, D31-D0 DACKn, DRAKn, SCK, TXD, TXD2, CTS2, RTS2
*
Note: *
When the PHZ bit in STBCR is set to 1, these pins go to the high-impedance state (except for pins being used as port pins, which retain their port state).
Figure 33.16 Pin Drive Timing for Standby Mode
Rev. 1.0, 02/03, page 1207 of 1294
33.3.3
Bus Timing
Table 33.7 Bus Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Item Address delay time BS delay time CS delay time RW delay time RD delay time Read data setup time Read data hold time WE delay time (falling edge) WE delay time Write data delay time RDY setup time RDY hold time RAS delay time CAS delay time 2 CKE delay time DQM delay time FRAME delay time IOIS16 setup time IOIS16 hold time ICIOWR delay time (falling edge) ICIORD delay time DACK delay time DACK delay time (falling edge) Symbol Min. tAD tBSD tCSD tRWD tRSD tRDS tRDH tWEDF tWED1 tWDD tRDYS tRDYH tRASD tCASD2 tCKED tDQMD tFMD tIO16S tIO16H tICWSDF tICRSD tDACD tDACDF 1.5 1.5 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5 1.5 Max. Unit 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Relative to CKIO falling edge SDRAM SDRAM SDRAM MPX PCMCIA PCMCIA PCMCIA PCMCIA Relative to CKIO falling edge Notes
Rev. 1.0, 02/03, page 1208 of 1294
T1 CKIO
T2
tAD
A25-A0
tAD tCSD tRWD
tCSD
CSn
tRWD
RD/WR
tRSD
RD D31-D0 (read)
tRSD
tRSD
tRDS tWED1 tWEDF tWDD tWEDF tWDD
tRDH
WEn
tWDD
D31-D0 (write)
tBSD
BS
tBSD
RDY
tDACD
DACKn (SA: IO memory)
tDACD
tDACD
tDACDF
DACKn (SA: IO memory)
tDACDF
tDACD
DACKn (DA) Notes: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
tDACD
Figure 33.17 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev. 1.0, 02/03, page 1209 of 1294
T1 CKIO
Tw
T2
tAD
A25-A0
tAD
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0
tRDS tWED1
tRDH
(read)
tWEDF
tWEDF
WEn
tWDD
D31-D0
tWDD
tWDD
(write)
tBSD
BS
tBSD
tRDYS
RDY
tRDYH
tDACD
DACKn (SA: IO memory)
tDACD
tDACD
tDACDF
DACKn (SA: IO memory)
tDACDF
tDACD
DACKn (DA)
tDACD
NOTES:
IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.18 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
Rev. 1.0, 02/03, page 1210 of 1294
T1 CKIO
Tw
Twe
T2
tAD
A25-A0
tAD
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0 (read)
tRDS tWED1
tRDH
tWEDF
tWEDF
WEn
tWDD
D31-D0 (write)
tWDD
tWDD
tBSD
BS
tBSD
tRDYS
RDY
tRDYH tRDYS tRDYH tDACD
tDACD
DACKn (SA: IO memory)
tDACD
tDACDF
DACKn (SA: IO memory)
tDACDF
tDACD
DACKn (DA)
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.19 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
Rev. 1.0, 02/03, page 1211 of 1294
TS1 CKIO
T1
T2
TH1
tAD
A25-A0
tAD
CSn
tCSD
tCSD
tRWD
RD/WR
tRWD
tRSD
RD
tRSD
tRSD
D31-D0 (read)
tRDS tWED1
tRDH
WEn
tWEDF
tWEDF
tWDD
D31-D0 (write)
tWDD
tWDD
tBSD
BS
tBSD
RDY
tDACD
DACKn (SA: IO memory)
tDACD tDACD
tDACDF
DACKn (SA: IO memory)
tDACDF
DACKn (DA)
tDACD
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.20 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1)
Rev. 1.0, 02/03, page 1212 of 1294
T1 CKIO tAD A25-A5
TB2
TB1
TB2
TB1
TB2
TB1
T2
tAD tAD
A4-A0 tCSD CSn tRWD RD/WR RD D31-D0 (read) tBSD BS RDY tDACD DACKn (SA:IO memory) tDACD DACKn (DA) NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high tDACD tDACD tDACD tRDS tBSD tRDH tRDS tRDH tRSD tRWD tCSD
tRSD
tRSD
Figure 33.21 Burst ROM Bus Cycle (No Wait)
Rev. 1.0, 02/03, page 1213 of 1294
T1 CKIO tAD A25-A5 tAD A4-A0 tCSD CSn tRWD RD/WR tRSD RD D31-D0 (read) tBSD BS tRDYS RDY DACKn (SA:IO memory) tDACD DACKn (DA) NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high tDACD tRDYS tRDYH tDACD tRDYH tRDYS tRDS tRDH
Tw
Twe
TB2
TB1
Twb
TB2
TB1
Twb
TB2
TB1
Twb
T2
tAD
Rev. 1.0, 02/03, page 1214 of 1294
tCSD tRSD tRDS tRDYH tDACD
tRWD
Figure 33.22 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait ; 2nd/3rd/4th Data: One Internal Wait)
tRDH
TS1 TB1 TB1
T1
TB2
TH1
TS1
TB2
TH1
TS1
TB2
TH1
TS1
TB1
T2
TH1
CKIO
tAD tAD tCSD tRWD tRSD tRDS tBSD tBSD tRDH tRDS tRDH
tAD
A25-A5
A4-A0
tCSD tRWD tRSD
CSn
RD/WR
RD
D31-D0 (read)
BS
RDY
DACKn (SA:IO memory)
tDACD tDACD
tDACD tDACD
Figure 33.23 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1)
DACKn (DA)
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer
Rev. 1.0, 02/03, page 1215 of 1294
DACK set to active-high
T1
Tw
Twe
TB2
TB1
Twb
Twbe
TB2
TB1 Twb
Twb
Twbe
TB2
TB1
Twbe
T2
CKIO
tAD tAD
tAD
A25-A5
A4-A0
CSn
tCSD
tCSD tRWD tRSD tRDS tBSD tRDH tBSD tBSD tRDS tRSD tRDH
tRWD
Rev. 1.0, 02/03, page 1216 of 1294
tRDYH tRDYS tDACD tDACD tRDYH tRDYS tRDYH tRDYS tRDYH tDACD
RD/WR
tRSD
RD
D31-D0 (read)
tBSD
BS
tRDYS
RDY
DACKn (SA: IO
tDACD
memory
Figure 33.24 Burst ROM Bus Cycle (One Internal Wait + One External Wait)
DACKn (DA)
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high
Tr CKIO
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3
Td4
Tpc
Tpc
Tpc
tAD
Bank Row
tAD tAD
Precharge-sel Row H/L
Address Row Column
tCSD
CSn
tCSD tRWD tRASD tCASD2 tCASD2 tDQMD tDQMD tRDS tRDH
c1
tRWD
RD/WR
tRASD
RAS
CASS
DQMn
D31-D0 (read)
BS
tBSD
tBSD
CKE
tDACD
DACKn (SA: IO memory)
Figure 33.25 Synchronous DRAN Auto-Precharge Read Bus Cycle: Single (RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011)
tDACD
NOTES:O : Dack device I SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Rev. 1.0, 02/03, page 1217 of 1294
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3
Td4 Td5 Td6 Td7 Td8 Tpc Tpc Tpc
CKIO
tAD tAD tAD
Row H/L H/L Row
Bank
tAD
Precharge-sel
Addres Row c1 c5
Rev. 1.0, 02/03, page 1218 of 1294
tCSD tRWD tRASD tCASD2 tCASD2 tRASD tCSD tRWD tDQMD tRDS
c1
CSn
RD/WR
RAS
CASS
tDQMD tRDH
c2 c3 c4 c5 c6 c7 c8
DQMn
D31-D0 (read)
BS
tBSD
tBSD
CKE
tDACD
tDACD
Figure 33.26 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst (RCD[1:0]=01, CAS Latency=3, TPC[2:0]=011)
DACKn (SA: IO
memory)
NOTES: IO : Dack device
SA : Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high
Tr Td5 Td6
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3 Td4 Td7 Td8
CKIO
tAD
Row
tAD tAD tAD
H/L
Bank
Precharge-sel Row H/L
Addrell Row c1 c5
CSn
tCSD tRWD tRASD tRASD
tCSD tRWD
RD/WR
RAS
tCASD2 tCASD2 tDQMD
CASS
tDQMD
DQMn
D31-D0 (read)
tRDS
c1
tRDH
c2 c3 c4 c5 c6 c7 c8
tBSD
tBSD
BS
CKE
tDACD
memory)
tDACD
DACKn (SA: IO
Figure 33.27 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands, Burst (RCD[1:0]=01, CAS Latency=3)
SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Rev. 1.0, 02/03, page 1219 of 1294
NOTES: IO : Dack device
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
Td3 Td5 Td6
Td4
Td7
Td8
CKIO
tAD
Row
tAD tAD tAD
H/L
tAD
Bank
Precharge-sel H/L Row H/L
Address Row C1 c5
Rev. 1.0, 02/03, page 1220 of 1294
tCSD tRWD tRASD tRASD tRWD tCASD2 tDQMD tCASD2 tDQMD tRDS
c1
CSn
tCSD
RD/WR
RAS
CASS
DQMn
D31-D0 (read)
tRDH
c2 c3 c4 c5 c6 c7 c8
tBSD
tBSD
BS
CKE
DACKn (SA: IO
tDACD
tDACD
memory)
Figure 33.28 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, CAS Latency=3)
NOTES: IO : Dack device
SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Tc1 CKIO
Tc2
Tc3
Tc4/Td1
Td2
Td3
Td4
Td5
Td6
Td7
Td8
tAD
Bank
tAD
tAD
Precharge-sel H/L H/L
Address
c1
c5
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tRASD
tCASD2
CASS
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (read)
tRDS
c1
tRDH
c2 c3 c4 c5 c6 c7 c8
tBSD
BS
tBSD
CKE
tDACD
DACKn (SA: IO memory)
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.29 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst (CAS Latency=3)
Rev. 1.0, 02/03, page 1221 of 1294
Tr CKIO
Trw
Tc1
Tc2
Tc3
Tc4
Trwl
Trwl
Tpc
tAD
Bank Row
tAD tAD
Precharge-sel
Row
H/L
Address
Row
c1
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tRASD
tCASD2
CASS
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
c1
tWDD
BS
tBSD
tBSD
CKE
DACKn (SA: IO
tDACD
memory)
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.30 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1222 of 1294
Tr CKIO
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
Tpc
tAD
Bank Row
tAD tAD tAD
H/L
Precharge-sel
Row
H/L
Address
Row
c1
c5
CSn
tCSD tRWD tRWD
tCSD
RD/WR
tRASD
RAS
tRASD tCASD2 tCASD2
tCASD2
CASS
tDQMD
DQMn
tDQMD
tWDD
D31-D0 (write) c1
tWDD
c2 c3 c4 c5 c6 c7 c8
BS
tBSD
tBSD
CKE
DACKn (SA: IO
tDACD
memory)
tDACD
NOTES:
IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.31 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1223 of 1294
Tr CKIO
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
tAD
Bank Row
tAD tAD tAD
H/L
Precharge-sel
Row
H/L
Address
Row
c1
c5
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tRASD tCASD2 tCASD2
CASS
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
c1
tWDD
c2 c3 c4 c5 c6 c7 c8
BS
tBSD
tBSD
CKE
tDACD
DACKn (SA: IO memory)
tDACD
NOTES: IO : Dack device
SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.32 Synchronous DRAM Normal Write Bus Cycle: ACT+WRITE Commands, Burst (RCD[1:0]=01, TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1224 of 1294
Tpr CKIO
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
tAD
Bank
tAD
Row
tAD tAD tAD
H/L
Precharge-sel
H/L
Row
H/L
Address
Row
c1
c5
CSn
tCSD tRWD tRWD tRASD tCASD2 tCASD2
tCSD
RD/WR
tRASD
RAS
CASS
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
c1
tWDD
c2 c3 c4 c5 c6 c7 c8
BS
tBSD
tBSD
CKE
tDACD
DACKn (SA: IO memory)
tDACD
NOTES:
IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.33 Synchronous DRAM Normal Write Bus Cycle: PRE+ACT+WRITE Commands, Burst (RCD[1:0]=01, TPC[2:0]=001, TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1225 of 1294
Tnop CKIO
(Tnop)
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Trwl
Trwl
tAD
Bank
tAD
tAD
Precharge-sel H/L H/L
Address
c1
c5
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tDACD
tCASD2
CASS
tCASD2
tDQMD
DQMn
tDQMD
tWDD
D31-D0 (write) c1
tWDD
c2 c3 c4 c5 c6 c7 c8
BS
tBSD
tBSD
CKE
tDACD
DACKn (SA: IO memory)
Single address DMA
tDACD
Normal write NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the dotted line.
Figure 33.34 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst (TRWL[2:0]=010)
Rev. 1.0, 02/03, page 1226 of 1294
Tpr CKIO
Tpc
tAD
Bank Row
tAD
Precharge-sel
H/L
Address
tCSD
CSn
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tRASD
tCASD2
CASS
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
tWDD
BS
tBSD
CKE
tDACD
DACKn
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.35 Synchronous DRAM Bus Cycle: Precharge Command (TPC[2:0]=001)
Rev. 1.0, 02/03, page 1227 of 1294
TRr1 CKIO
TRr2
TRr3
TRr4
TRrw
TRr5
Trc
Trc
Trc
tAD
Bank
tAD
Precharge-sel
Address
tCSD
CSn
tCSD
tCSD
tCSD
tRWD
RD/WR
tRWD
tRASD
RAS
tRASD
tRASD
tRASD
tCASD2
CASS
tCASD2
tCASD2
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
tWDD
tBSD
BS
CKE
tDACD
DACKn
tDACD
NOTES:
IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.36 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS=1, TRC[2:0]=001)
Rev. 1.0, 02/03, page 1228 of 1294
TRs1 CKIO
TRs2
TRs3
TRs4
TRs5
Trc
Trc
Trc
tAD
Bank
tAD
Precharge-sel
Address
tCSD tCSD
CSn
tCSD
tCSD
tRWD
RD/WR
tRWD tRASD
tRASD
RAS
tRASD
tRASD
tCASD2
CASS
tCASD2
tCASD2
tCASD2
tDQMD
DQMn
tDQMD
tWDD
D31-D0 (write)
tWDD
tBSD
BS
tCKED
CKE
tCKED tDACD
tDACD
DACKn
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.37 Synchronous DRAM Bus Cycle: Self-Refresh (TRC[2:0]=001)
Rev. 1.0, 02/03, page 1229 of 1294
TRp1 CKIO
TRp2
TRp3
TRp4
TMw
TMw2
TMw3
TMw4
TMw5
tAD
Bank
tAD
tAD
Precharge-sel
Address
tCSD
CSn
tCSD tRWD tRASD
tCSD tRWD tRASD
tRWD
RD/WR
tRASD
RAS
tCASD2
CASS
tCASD2
tCASD2
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
tWDD tBSD
BS
CKE
tDACD
DACKn
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA: Dual address DMA transfer DACK set to active-high
Figure 33.38 Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)
Rev. 1.0, 02/03, page 1230 of 1294
TRp1 CKIO
TRp2
TRp3
TRp4
TMw
TMw2
TMw3
TMw4
TMw5
tAD
Bank
tAD
tAD
Precharge-sel
Address
tCSD
CSn
tCSD tRWD tRASD
tCSD tRWD tRASD
tRWD
RD/WR
tRASD
RAS
tCASD2
CASS
tCASD2
tCASD2
tCASD2
tDQMD
DQMn
tDQMD
D31-D0 (write)
tWDD
tWDD tBSD
BS
CKE
tDACD
DACKn
tDACD
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET)
Rev. 1.0, 02/03, page 1231 of 1294
Tpcm1 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w CKIO
Tpcm2
tAD
A25-A0
tAD tCSD tRWD tRWD tCSD
tAD
tAD tCSD tRWD
tCSD
CExx REG (WE0)
tRWD
RD/WR
Rev. 1.0, 02/03, page 1232 of 1294
tRSD tRSD
RD D15-D0 (read)
tRSD tRDS tRDH tWEDF tWDD tWED1 tWDD tWDD tBSD tBSD tRDYS
tRSD
tRSD tRDS tWEDF tWEDF tRDH
tRSD
tWED1 tWEDF tWDD
WE1
D15-D0 (write)
tWDD tBSD
tWDD
BS
tBSD
tRDYH tDACD tDACD tRDYS tRDYH tDACD
Figure 33.40 PCMCIA Memory Bus Cycle
RDY
tDACD
DACKn (DA)
TED (1) TED= 0, TEH= 0, No Wait NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
TEH (2) TED= 1, TEH= 1, One Internal Wait + One External Wait
Tpci1 Tpci0 Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w CKIO
Tpci2
tAD
A25-A0
tAD tCSD tRWD tRWD tCSD
tAD
tAD tCSD tRWD
tCSD
CExx REG (WE0)
tRWD
RD/WR
tICRSD tICRSD tICRSD tRDH tICWSDF tWDD tWDD tBSD
ICIORD (WE2) D15-D0 (read)
tICRSD tRDS tICWSDF
tICRSD
tRDS tICWSDF tICWSDF
tRDH tICWSDF tWDD tBSD tRDYS tRDYH
ICIOWR (WE3)
tWDD tWDD
D15-D0 (write)
tBSD
BS RDY
tBSD
Figure 33.41 PCMCIA I/O Bus Cycle
tIO16S
IOIS16
tIO16H tDACD tDACD
tRDYS tIO16S
tRDYH tIO16H tDACD
tDACD
DACKn (DA)
(1) TE= 0, TEH= 0, No Wait
(2) TED= 1, TEH= 1, One Internal Wait + One External Wait
Rev. 1.0, 02/03, page 1233 of 1294
NOTES:
IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Tpci0 Tpci2w Tpci2w CKIO
Tpci1
Tpci1w
Tpci2
Tpci0
Tpci1
Tpci1w
Tpci2
tAD
A25-A1
tAD tAD
A0 CExx REG (WE0)
tCSD tRWD
tCSD
tCSD tRWD
Rev. 1.0, 02/03, page 1234 of 1294
RD/WR
tICRSD tICRSD tRDS tICWSDF tICWSDF
ICIOWR (WE3)
tICRSD tRDH tICWSDF tWDD tWDD tICWSDF
ICIORD (WE2) D15-D0 (read)
tICWSDF
D15-D0 (write)
tWDD tBSD tBSD
tWDD
tWDD
BS
tRDYS tRDYH
tRDYS tRDYH
RDY IOIS16
tIO16S tIO16H
Figure 33.42 PCMCIA I/O Bus Cycle (TED=1, TEH=1, One Internal Wait, Bus Sizing)
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Tm1 Tm0 Tmd1w Tmd1w Tmd1 CKIO
Tmd1w
Tmd1
tFMD
RD/FRAME
tFMD tWDD tRDH
A
tFMD tRDS tWDD tWDD
D0
tFMD tRDS
D0
tWDD
D31-D0 A
tRDH
tCSD
CSn
tCSD tRWD tRWD
tCSD
tCSD tRWD
tRWD
RD/WR WEn
tWED1 tRDYS tRDYH
tWED1
tWED1 tRDYS tRDYH tRDYS tBSD tBSD tRDYH
tWED1
RDY
tBSD tBSD
BS
tDACD
DACKn (DA)
Figure 33.43 MPX Basic Bus Cycle: Read
tDACD tDACD
(1) 1st Data : One Internal Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
tDACD
(2) 1st Data : One Internal Wait + One External Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Rev. 1.0, 02/03, page 1235 of 1294
Tm1 CKIO
Tmd1
Tm1
Tmd1w
Tmd1
Tm1
Tmd1w
Tmd1w
Tmd1
tFMD
RD/FRAME
tFMD tWDD
D0 A D0 A D0
tFMD tFMD tWDD tCSD tRWD tWED1 tRDYH tBSD tRWD tCSD tWDD tWDD tFMD tWDD tCSD tRWD tWED1 tWED1 tRDYS tBSD tBSD tDACD tRWD tCSD tWDD tWDD
tFMD
tWDD
D31-D0 A
tWDD tCSD tRWD
tCSD
CSn
tRWD
RD/WR WEn
Rev. 1.0, 02/03, page 1236 of 1294
tWED1 tRDYS
RDY
tWED1 tRDYS tRDYH tRDYH
tWED1
tRDYH tBSD tDACD tDACD
tBSD
tRDYS tBSD tDACD
BS
tDACD
DACKn (DA)
tDACD
(1) 1st Data : No Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
(2) 1st Data : One Internal Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
(3) 1st Data : One Internal Wait + One External Wait 1st data bus cycle information D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Figure 33.44 MPX Basic Bus Cycle: Write
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Tm1
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
Tm1
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
CKIO
tFMD tRDH
D1 A D2 D3 D4 D5 D6 D7 D8 D1 D2
tFMD tWDD tWDD tRDS tRDH
D3
tFMD
tFMD
RD/FRAME
tWDD tCSD tRWD tRWD tRDYS tBSD tDACD tDACD tBSD tRDYH tRDYH tCSD
D31-D0
tWDD tRDS
A
D7
D8
tCSD
tCSD tRWD tRDYS tRDYH
CSn
tRWD
RD/WR
tRDYS
RDY
tBSD
tBSD
BS
tDACD
tDACD
DACKn (DA)
(1) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait 1st data bus cycle information
(2) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait + External Wait Control 1st data bus cycle information
Figure 33.45 MPX Bus Cycle: Burst Read
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
Rev. 1.0, 02/03, page 1237 of 1294
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Tm1
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
Tm1
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
CKIO
tFMD tFMD tWDD
D2 A D3 D4 D5 D6 D7 D8 D1 D2 D3
tFMD tWDD tWDD tCSD tRWD
tFMD tWDD
D7 D8
RD/FRAME
tWDD tCSD tRWD tRDYS tBSD tBSD tRDYH
tWDD
D31-D0
A
D1
tCSD
tCSD tRWD tRDYS tRDYH
Rev. 1.0, 02/03, page 1238 of 1294
tDACD tDACD
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
CSn
tRWD
RD/WR
tRDYS
tRDYH
RDY
tBSD
tBSD
BS
tDACD
tDACD
DACKn (DA)
(1) No Internal Wait
Figure 33.46 MPX Bus Cycle: Burst Write
1st data bus cycle information
(2) 1st Data : One Internal Wait, 2nd to 8th Data : No Internal Wait + External Wait Control 1st data bus cycle information
D31-D29: Access size 000: Byte 001: Word (2 bytes) 010: Long (4 bytes) 011: Quad (8 bytes) 1xx: Burst (32 bytes) D25-D0: Address
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
T1
T2
T1
Tw
T2
T1
Tw
Twe
T2
CKIO
tAD tAD tAD tAD tCSD tCSD tRWD tRSD tRSD tRWD tRSD tRDS tWED1 tWEDF tWED1 tRDH tWED1 tWEDF tBSD tRSD tCSD tRWD tRSD tAD tCSD tRWD tRSD tRDS tWED1 tWEDF tBSD tBSD tBSD tRDYS tDACD tDACD tDACD tDACD tRDYH tDACD tDACD tBSD tWED1 tRDH tRSD tCSD tRWD tRSD
tAD tCSD tRWD tRSD tRDS tRDH tWED1
A25-A0
CSn
RD/WR
RD
D31-D0 (read)
WEn
tBSD tRDYS tRDYH tRDYH tDACD tDACD tRDYS tDACD
BS
RDY
DACKn (SA: IO
memory)
tDACD
tDACD
tDACD
tDACD
tDACD
tDACD
Figure 33.47 Memory Byte Control SRAM Bus Cycle
(1) Basic Read Cycle : No Wait (2) Basic Read Cycle : One Internal Wait
DACKn (DA)
(3) Basic Read Cycle : One Internal Wait + One External Wait
Rev. 1.0, 02/03, page 1239 of 1294
NOTES: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
TS1 CKIO
T1
T2
TH1
tAD
A25-A0
tAD tCSD
tCSD
CSn
tRWD
RD/WR
tRWD tRSD tRDS tRDH tWED1 tRSD
tRSD
RD D31-D0 (read)
tWED1
tWEDF
WEn
tBSD
BS
tBSD
RDY
tDACD
DACKn (SA: IO memory)
tDACD
tDACD
DACKn (DA)
tDACD
Notes: IO : Dack device SA : Single address DMA transfer DA : Dual address DMA transfer DACK set to active-high
Figure 33.48 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, Address Setup/Hold Time Insertion, AnS=1, AnH=1)
Rev. 1.0, 02/03, page 1240 of 1294
33.3.4
INTC Module Signal Timing
Table 33.8 INTC Module Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Module INTC Item NMI pulse width (High) Symbol tNMIH Min. 5 Max. -- Unit tcyc ns tcyc ns Figure 33.49 Notes normal mode sleep mode 30 NMI pulse width (Low) tNMIL 5 -- -- 33.49 33.49 standby mode normal mode sleep mode 30 Note: tcyc : one CKIO cycle time
tNMIH tNMIL
--
33.49
standby mode
NMI
Figure 33.49 NMI Input Timing 33.3.5 DMAC Module Signal Timing
Table 33.9 DMAC Module Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Module DMAC Item DREQn setup time DREQn hold time DRAKn delay time Symbol tDRQS tDRQH tDRAKD Min. 3 1.5 1.5 Max. -- -- 6 Unit ns ns ns Figure 33.50 33.50 33.50 Notes
Rev. 1.0, 02/03, page 1241 of 1294
CKIO
tDRQH
DREQn
tDRQH tDRQS
tDRQS
DRAKn
tDRAKD
DREQ Figure 33.50 DREQ/DRAK Timing 33.3.6 TMU Module Signal Timing
Table 33.10 TMU Module Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Module TMU Item Timer clock pulse width (High) Timer clock pulse width (Low) Timer clock rise time Timer clock fall time Note: tPcyc : one Pck cycle time Symbol tTCLKWH tTCLKWL tTCLKr tTCLKf Min. 4 4 -- -- Max. -- -- 0.8 0.8 Unit tPcyc tPcyc tPcyc tPcyc Figure 33.51 33.51 33.51 33.51 Notes
TCLK
tTCLKWH
tTCLKWL
tTCLKf
tTCLKr
Figure 33.51 TCLK Input Timing
Rev. 1.0, 02/03, page 1242 of 1294
33.3.7
SCIF Module Signal Timing
Table 33.11 SCIF Module Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Module Item SCIFn Input clock cycle (asynchronous) Input clock cycle (synchronous) Input clock pulse width Input clock rise time Input clock fall time Transfer data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) Note: tPcyc : one Pck cycle time tSCKW tSCKr tSCKf tTXD tRXS tRXH Symbol Min. tScyc 4 10 0.4 -- -- -- 3 1 Max. Unit -- -- 0.6 0.8 0.8 3 -- -- tPcyc tPcyc tScyc tPcyc tPcyc tPcyc tPcyc tPcyc Figure Notes 33.52 33.52 33.52 33.52 33.52 33.53 33.53 33.53
tSCKW SCIFn_CLK tScyc tSCKf tSCKr
Figure 33.52 SCIFn_CLK Input Clock Timing
tScyc SCIFn_CLK tTXD SCIFn_TXD tTXD
SCIFn_RXD tRXS tRXH
Figure 33.53 SCIF I/O Synchronous Mode Clock Timing
Rev. 1.0, 02/03, page 1243 of 1294
33.3.8
H-UDI Module Signal Timing
Table 33.12 H-UDI Module Signal Timing (VDDQ= 3.0 to 3.6V, VDD= 1.5V, Ta= -40 to 85C, CL= 30pF, PLL2 on)
Module Item H-UDI Input clock cycle Input clock pulse width (High) Input clock pulse width (Low) Input clock rise time Input clock fall time ASEBRK setup time ASEBRK hold time TDI/TMS setup time TDI/TMS hold time TDO data delay time ASE-PINBRK pulse width Notes: 1. tcyc : one CKIO cycle time 2. tPcyc : one Pck cycle time
tTCKcyc tTCKH tTCKL VIH 1/2VDDQ tTCKr
Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tASEBRKS tASEBRKH tTDIS tTDIH tTDO tPINBRK
Min. 50 15 15 -- -- 10 10 15 15 0 2
Max. -- -- -- 10 10 -- -- -- -- 10 --
Unit ns ns ns ns ns tcyc tcyc ns ns ns tPcyc
Figure 33.54, 33.56 33.54 33.54 33.54 33.54 33.55 33.55 33.56 33.56 33.56 33.57
Notes
1/2VDDQ
VIH
VIH VIL tTCKf VIL
Note: When clock is input from TCK pin.
Figure 33.54 TCK Input Timing
RESET
tASEBRKS ASEBRK/ BRKACK
tASEBRKH
Figure 33.55 RESET Hold Timing
Rev. 1.0, 02/03, page 1244 of 1294
TCK
tTCKcyc
TDI TMS
tTDIS
tTDIH
TDO
tTDO
Figure 33.56 H-UDI Data Transfer Timing
tPINBRK ASEBRK
Figure 33.57 Pin Break Timing
Rev. 1.0, 02/03, page 1245 of 1294
33.3.9
CMT Module Signal Timing
Table 33.13 CMT Module Signal Timing
Item CMT_CTR output delay time CMT_CTR input setup time CMT_CTR input hold time Timer clock low level width Timer clock high level width Note: tcyc : one CKIO cycle time
CKIO tTMD CMT_CTR tTMS CMT_CTR tTMH
Symbol tTMD tTMS tTMH tTMLOW tTMHIGH
Min. -- 20 20 1.5 1.5
Max. 36 -- -- -- --
Unit ns ns ns tcyc tcyc
Figure 33.58 33.58 33.58 33.59 33.59
Figure 33.58 CMT Timing (1)
CKIO tTMS tTMHIGH CMT_CTR tTMLOW
Figure 33.59 CMT Timing (2)
Rev. 1.0, 02/03, page 1246 of 1294
33.3.10 HCAN2 Module Signal Timing Table 33.14 HCAN2 Module Signal Timing
Item CAN_TX output delay time CAN_RX input setup time CAN_RX input hold time Symbol tCAND tCANS tCANH Min. -- 100 100 Max. 100 -- -- Unit ns ns ns Figure 33.60 33.60 33.60
CKIO tCAND CAN_TX tCANS CAN_RX tCANH
Figure 33.60 HCAN2 Timing 33.3.11 GPIO Signal Timing Table 33.15 GPIO Signal Timing
Item GPIO output delay time GPIO input setup time GPIO input hold time Symbol tIOPD tIOPS tIOPH Min. -- 20 20 Max. 20 -- -- Unit ns ns ns Figure 33.61 33.61 33.61
CKIO tIOPD GPIO[n] tIOPS GPIO[n] tIOPH
Figure 33.61 GPIO Timing
Rev. 1.0, 02/03, page 1247 of 1294
33.3.12 I C Electrical Characteristics 1. I C block diagram and truth table
2 2
2
Figure 33.62 shows a block diagram of I C I/O buffer and Table 33.16 shows a truth table.
scl_out/sda_out I2Cn_SCL/I2Cn_SDA scl_in/sda_in (*) Note : * schmit input
Figure 33.62 Block Diagram of I C I/O Buffer Table 33.16 Truth Table of I C I/O Buffer
scl_out/sda_out 1 0 I2Cn_SCL/ I2Cn_SDA Z 0 scl_in/sda_in H/L level of I2Cn_SCL/ I2Cn_SDA H/L level of I2Cn_SCL/ I2Cn_SDA
2
2
Notes: 1. The Output voltages from I2Cn_SCL/ I2Cn_SDA are undefined until the internal logic will be stable after power on. 2. If a external pull down resistance is connected to a 5V tolerant buffer, the value of the resistance must be less than 15k.
2. I C DC characteristics Table 33.17 I C DC Characteristics
Item Input Voltage symbol VIH VIL Output Voltage VOL Input Current Ii Min. -0.5 0 -10 Max. Unit V Test Condition VDDQ x0.8 5.5 0.4 10
2
2
VDDQ x0.1 V V A IOL =3 mA Input Voltage = 0.1xVDDQ to 0.9xVDDQ (max.)
Rev. 1.0, 02/03, page 1248 of 1294
3. I C AC Characteristics Table 33.18 I C Bus Interface Module Signal Timing
Item I2Cn_SCL frequency I2Cn_SCL low level pulse width I2Cn_SCL high level pulse width I2Cn_SCL/I2Cn_SDA rise time I2Cn_SCL/I2Cn_SDA fall time I2Cn_SDA bus free time I2Cn_SCL start condition hold time I2Cn_SCL resend start condition setup time I2Cn_SDA stop condition setup time I2Cn_SDA setup time I2Cn_SDA hold time Note: tPcyc : one Pck cycle time Symbol tIcyc tICWL tICWH tICr tICf tICBF tICH tICS tICST tDAS tICDH Min. 0 1.3 0.6 -- -- 1.3 0.6 0.6 0.6 100 0 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. 400 -- -- 300 300 -- -- -- -- -- 0.9 Unit kHz s s ns ns s s s s ns s
2
2
4. I C Schmitt characteristics Table 33.19 I C Schmitt characteristics
Item Symbol Min. -- Max. Unit Notes Threshold voltage : L H Threshold voltage : H L reference value between VTT+ and VTT-
2
2
Threshold voltage VTT+ VTT- VTT
VDDQ x0.8 V V V
VDDQ x0.1 -- VDDQ x0.05 --
Rev. 1.0, 02/03, page 1249 of 1294
P
S tICBF
Sr
P
I2Cn_SDA tICST tICWL tICWH tICH tICS
I2Cn_SCL tIcyc tICDH
tICf S : start condition P : stop condition Sr : resend start condition
tICr
tDAS
Figure 33.63 I C Bus Interface Module Signal Timing 5. Notes on Usage of I C * While 5V interface signal is input to this LSI, the power must be supplied to this LSI. If the power supply to SH-4 is switched off, the power supply to the bus pull-up resistance must be switched off. The I/O buffer for I C is 5V tolerant, if the power is supplied to this LSI. The I/O buffer may be destroyed, if the 5V interface signal is input while the power supply to this LSI is switched off. * If an external pull-down resistance is connected to the 5V tolerant buffer, the value of the resistance must be less than 15k.
2 2
2
Rev. 1.0, 02/03, page 1250 of 1294
33.3.13 HSPI Module Signal Timing Table 33.20 HSPI Module Signal Timing
Item HSPI_CLK frequency HSPI clock high level width HSPI clock low level width HSPI_TX setup time HSPI_TX delay time HSPI_RX setup time HSPI_RX hold time HSPI_CS read time Note: Pck : Peripheral clock frequency
HSPI_CS tSPIcyc tSPILW (CLKP= 0) HSPI_CLK tSPIHW
Symbol tSPIcyc tSPIHW tSPILW tSUSPITX tDSPITX tSUSPIRX tHLSPIRX tCSLEAD
Min. -- 60 60 -- -- 20 20 100
Max. Pck/8 -- -- 20 20 -- -- --
Unit Hz ns ns ns ns ns ns ns
Figure 33.64 33.64 33.64 33.64 33.64 33.64 33.64 33.64
(CLKP= 1) HSPI_CLK
tCSLEAD tSUSPITX tDSPITX MSB MSB-1
(LMSB= 0) HSPI_TX
tSUSPIRX tHLSPIRX HSPI_RX MSB tSUSPITX (LMSB= 1) HSPI_TX MSB tSUSPIRX tHLSPIRX HSPI_RX MSB MSB-1 MSB-1 tDSPITX MSB-1 MSB-2
Figure 33.64 HSPI Data Output/Input Timing
Rev. 1.0, 02/03, page 1251 of 1294
33.3.14 USB Electrical Characteristics 1. USB DC characteristics Table 33.21 USB DC characteristics
Item Input Voltage Symbol Min. VIH VIL Output Voltage VOH VOL Differential input sensitivity Differential common mode range Output resistance* Notes: * VDI VCM ZDRV -0.3 -- 0.2 0.8 28 Max. VDDQx0.2 VDDQx0.2 -- 2.5 44 Unit V V V V V V 14.25k-GND 1.425k-VDDQ Test condition Figure 33.65 33.65 33.66 33.66
VDDQ x0.7 VDDQ+0.3 VDDQ x0.8 --
|USB_DP-USB_DM| 33.67 33.67 33.68
It includes the external resistance value. The recommended external resistance value is 27 1%.
VIH USB_DP, USB_DM VIL
Figure 33.65 Input Voltage (VIH, VIL)
VOH USB_DP, USB_DM VOL
Figure 33.66 Output (VOH, VOL)
VCM (Max.) USB_DP, USB_DM VDI
VCM (Min.)
Figure 33.67 Differential Input Sensitivity (VDI), Differential common mode range (VCM)
Rev. 1.0, 02/03, page 1252 of 1294
2.
USB AC characteristics
Table 33.22 USB AC characteristics
Item Symbol Full speed*1 Min. Transition Time Rise* Fall* Rise/Fall time matching D+D- crossover voltage tr tf tRFM VCRS 4 4 80 1.3 Max. 20 20 111.1 2.4 Low speed*2 Min. 75 75 80 1.1 Max. 300 300 125 2.0 ns ns % V tr/ tf Unit Notes
Notes: * Transition time from 10% level to 90% level (Figure 33.70). *1 Please refer Figure 33.68 about the test condition. *2 Please refer Figure 33.69 about the test condition.
SH7760 ZDRV External resistance 271% USB_DP 50pF ZDRV External resistance 271% USB_DM 50pF Measurement point Measurement point
Figure 33.68 Load Condition of AC Characteristics (Full speed)
Rev. 1.0, 02/03, page 1253 of 1294
SH7760 ZDRV External resistance 271% USB_DP CL 15k Measurement point
ZDRV External resistance 271% USB_DM
3.6V 1.5k Measurement point
CL
15k CL = 200-600pF
Figure 33.69 Load Condition of AC Characteristics (Low speed)
VOH USB_DP, USB_DM 90% VOL 10% 90% 10%
tr
tf
Figure 33.70 tr, tf
USB_DP, USB_DM
VCRS
Figure 33.71 VCRS
33.3.15 MFI Electrical Characteristics 1. MFI AC characteristics Figure 33.72 shows the AC characteristics of 68 series bus. Figure 33.73 and 33.74 show the AC characteristics of 80 series bus.
Rev. 1.0, 02/03, page 1254 of 1294
Table 33.23 AC Characteristics of 68 Series Bus
Item Read bus cycle time Write bus cycle time Address setup time (MFI-RS) (MFI-RW/RD) Address hold time (MFI-RS) (MFI-RW/RD) Enable high width (Read) Enable low width (Write) Enable low width Read data delay time Read data hold time Write data setup time Write data hold time Symbol tMFICYCR tMFICYCW tMFIAS tMFIAS tMFIAH tMFIAH tMFIWRH tMFIWEH tMFIWEL tMFIRDD tMFIRDH tMFIWDS tMFIWDH Min. 4x tPcyc+10 3x tPcyc+10 0 10 0 10 2.5x tPcyc 1.5x tPcyc 2.0x tPcyc+5 -- 0 tPcyc+10 10 Max. -- -- -- -- -- -- -- -- -- 2x tPcyc+10 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 33.72
Notes: 1. tPcyc : one Pck cycle time 2. tMFIWEH is the time where the low level of MFI-CS and the high level of MFI-E/WR are overlapped.
tMFICYCR MFI-RW/RD MFI-RS tMFIWRH tMFIWEH tMFICYCW
MFI-CS tMFIAS tMFIAH tMFIAS tMFIAH
MFI-E/WR tMFIRDD MFI-D15MFI-D0 tMFIRDH Read data
tMFIWEL tMFIWDS tMFIWDH Write data
Figure 33.72 AC Characteristics of 68 Series Bus
Rev. 1.0, 02/03, page 1255 of 1294
Table 33.24 AC Characteristics of 80 Series Bus
Item Read bus cycle time Write bus cycle time Address setup time Address hold time Read low width (Read) Write low width (Write) Read/Write high width Read data delay time Read data hold time Write data setup time Write data hold time Symbol tMFICYCR tMFICYCW tMFIAS tMFIAH tMFIWRL tMFIWWL tMFIWRWH tMFIRDD tMFIRDH tMFIWDS tMFIWDH Min. 4x tPcyc 3x tPcyc 0 0 2.5x tPcyc 1.5x tPcyc 2.0x tPcyc+5 -- 0 tPcyc+10 10 Max. -- -- -- -- -- -- -- 2x tPcyc+10 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns Figure 33.73, 33.74
Notes: 1. tPcyc : one Pck cycle time 2. tMFIWRL is the time where the low level of MFI-CS and the low level of MFI-RW/RD are overlapped. 3. tMFIWWL is the time where the low level of MFI-CS and the low level of MFI-E/WR are overlapped.
tMFICYCR MFI-RS tMFIWRL MFI-CS tMFIAS tMFIAH tMFIAS tMFIWWL tMFICYCW
tMFIAH
MFI-RW/RD tMFIRDD MFI-D15MFI-D0 tMFIRDH Read data
tMFIWRWH tMFIRDD tMFIRDH Read data
Figure 33.73 AC Characteristics of 80 Series Bus (Read)
Rev. 1.0, 02/03, page 1256 of 1294
tMFICYCR MFI-RS tMFIWRL MFI-CS tMFIAS tMFIAH tMFIAS
tMFICYCW
tMFIWWL
tMFIAH
MFI-E/WR tMFIWDS tMFIWDH MFI-D15MFI-D0 Write data
tMFIWRWH tMFIWDS tMFIRDH Write data
Figure 33.74 AC Characteristics of 80 Series Bus (Write)
Rev. 1.0, 02/03, page 1257 of 1294
33.3.16 SIM Module Signal Timing Table 33.25 SIM Module Signal Timing
Item SIM_CLK clock cycle time SIM_CLK clock high level width SIM_CLK clock low level width SIM_RST reset output delay time Note: tPcyc : one Pck cycle time
tSMCWH SIM_CLK tSMCWL tSMRD SIM_RST tSMRD tSMcyc
Symbol tSMcyc tSMCWH tSMCWL tSMRD
Min. tPcyc/16 0.4 tSMcyc 0.4 tSMcyc 0
Max. tPcyc/2 -- -- 20
Unit ns ns ns ns
Figure 33.75
Figure 33.75 SIM Module Signal Timing 33.3.17 MMCIF Module Signal Timing Table 33.26 MMCIF Module Signal Timing
Item MCCLK clock cycle time MCCLK clock high level width MCCLK clock low level width MCCMD output data delay time MCCMD input data setup time MCCMD input data hold time MCDAT output data delay time MCDAT input data setup time MCDAT input data hold time Symbol tMMcyc tMMWH tMMWL tMMTCD tMMRCS tMMRCH tMMTDD tMMRDS tMMRDH Min. 50 0.4x tMMcyc 0.4x tMMcyc -- 10 10 -- 10 10 Max. -- -- -- 10 -- -- 10 -- -- Unit ns ns ns ns ns ns ns ns ns Figure 33.76 33.76 33.76 33.76 33.77, 33.78 33.77, 33.78 33.76 33.77, 33.78 33.77, 33.78
Rev. 1.0, 02/03, page 1258 of 1294
tMMcyc tMMWH tMMWL MCCLK tMMTCD MCCMD (output) tMMTDD MCDAT (output) tMMTDD tMMTCD
Figure 33.76 MMCIF Transmit Timing
MCCLK tMMRCS tMMRCH MCCMD (input) tMMRDS MCDAT (input) tMMRDH
Figure 33.77 MMCIF Receive Timing (rising edge sampling)
MCCLK tMMRCS tMMRCH MCCMD (input) tMMRDS MCDAT (input) tMMRDH
Figure 33.78 MMCIF Receive Timing (falling edge sampling)
Rev. 1.0, 02/03, page 1259 of 1294
33.3.18 LCDC Module Signal Timing Table 33.27 LCDC Module Signal Timing
Item LCD_CLK input clock frequency LCD_CLK input clock rise time LCD_CLK input clock fall time LCD_CLK input clock duty Clock (LCD_CL2) cycle time Clock (LCD_CL2) High level pulse width Clock (LCD_CL2) Low level pulse width Clock (LCD_CL2) transition time (rise/fall) Data (LCD_DATA) delay time Display Enable (LCD_M_DISP) delay time Horizontal sync signal (LCD_CL1) delay time Vertical sync signal (LCD_FLM) delay time Symbol tFREQ tr tf tDUTY tCC tCHW tCLW tCT tDDdo tIDdo tHDdo tVDdo Min. -- -- -- 90 25 7 7 -- -3.5 -3.5 -3.5 -3.5 Max. 50 3 3 110 -- -- -- 3 3 3 3 3 Unit MHz ns ns % ns ns ns ns ns ns ns ns 33.79 Figure
tCHW
LCD_CL2
0.8Vcc 0.2Vcc
tCLW
tCT
tCT
tCC
tDD
LCD_DATA0-15
tDT
0.8Vcc 0.2Vcc
tDT
tID
LCD_M_DISP
tIT
0.8Vcc 0.2Vcc
tIT
tHD
LCD_CL1
tHT
0.8Vcc 0.2Vcc
tHT
tVD
LCD_FLM
tVT
0.8Vcc 0.2Vcc
tVT
Figure 33.79 LCDC Module Signal Timing
Rev. 1.0, 02/03, page 1260 of 1294
33.3.19 HAC Interface Module Signal Timing Table 33.28 HAC Interface Module Signal Timing
Item HAC_RES active low pulse width HAC_SYNC active high pulse width HAC_SYNC delay time 1 HAC_SYNC delay time 2 HAC_SD_OUT delay time HAC_SD_IN setup time HAC_SD_IN hold time HAC_BIT_CLK input high level width HAC_BIT_CLK input low level width Note: tPcyc : one Pck cycle time
tRST_LOW
Symbol tRST_LOW tSYN_HIGH tSYNCD1 tSYNCD2 tSDOUTD tSDINS tSDINH tICL_HIGH tICL_LOW
Min. 1000 1000 -- -- -- 10 10 tPcyc/2 tPcyc/2
Max. -- -- 15 15 15 -- -- -- --
Unit ns ns ns ns ns ns ns ns ns
Figure 33.80 33.81 33.83 33.83 33.83 33.83 33.83 33.82 33.82
HAC_RES
Figure 33.80 HAC Cold Reset Timing
tSYN_HIGH
HAC_SYNC
Figure 33.81 HAC Cold Reset Timing
tICL_HIGH
HAC_BIT_CLK tICL_LOW
Figure 33.82 HAC Clock Input Timing
Rev. 1.0, 02/03, page 1261 of 1294
tSDINS HAC_BIT_CLK
HAC_SD_IN tSDINH HAC_SD_OUT tSYNCD1 HAC_SYNC tSYNCD2 tSDOUTD
Figure 33.83 HAC Interface Module Signal Timing 33.3.20 SSI Interface Module Signal Timing Table 33.29 SSI Interface Module Signal Timing
Item Output cycle time Input cycle time Input high level width/Output high level width Symbol Min. tOSCK tISCK tIHC/tOHC Max. Unit Notes output input input, output input, output output transmit receive receive Figure 33.84 33.84 33.84 33.84 33.84 33.85, 33.86 33.87, 33.88 33.87, 33.88
T.B.D T.B.D ns T.B.D T.B.D ns T.B.D -- T.B.D -- -- -- 10 10 60 50 -- -- ns ns ns ns ns ns
Input low level width/Output low level tILC/tOLC width SCK Output rise time SDATA Output delay time SDATA/WS Input setup time SDATA/WS Input hold time tRC tDTR tSR tHTR
tOHC tIHC VIH, VOH VIH, VOH VIL, VOL tOLC tILC
tRC VIH, VOH VIL, VOL tISCK, tOSCK VIL, VOH
SSI_SCK
Figure 33.84 SSI Clock Input/Output Timing
Rev. 1.0, 02/03, page 1262 of 1294
SSI_SCK tDTR SSI_WS, SSI_SDATA
Figure 33.85 SSI Transmit Timing (1)
SSI_SCK tDTR SSI_WS, SSI_SDATA
Figure 33.86 SSI Transmit Timing
SSI_SCK tSR SSI_WS, SSI_SDATA tHTR
Figure 33.87 SSI Receive Timing (1)
SSI_SCK tHTR SSI_WS, SSI_SDATA tSR
Figure 33.88 SSI Receive Timing (2)
Rev. 1.0, 02/03, page 1263 of 1294
33.4
A/D Converter Characteristics
Table 33.30 shows A/D converter characteristics. Table 33.30 A/D Converter Characteristics
Item Resolution Conversion time (single mode) Permitted analog signal source impedance Non-linear error Offset error Full-scale error Quantization error Absolute error Note: The input voltage to A/D converter is as follows. AVSS_ADC ANn AVCC_ADC 1. ANn: A/D converter 2. AVSS_ADC = GND 3. AVCC_ADC = 3.0V (Min.), 3.3V (Typ.), 3.6V (Max.) 4. n = 0 to 3 Min. 10 8 -- -- -- -- -- -- Max. 10 -- 5 4.0 2.0 2.0 0.5 4.0 Unit bits s k LSB LSB LSB LSB LSB
Rev. 1.0, 02/03, page 1264 of 1294
33.5
AC Characteristic Test Conditions
The AC characteristic test conditions are as follows : * Input/output signal reference level: 1.5V (VDDQ = 3.3 0.3V) * Input pulse level: VSSQ to 3.0V (VSSQ to VDDQ for (RESET, TRST, NMI, ASEBRK/BRKACK, MRESET, CA, SCIF2_RTS, USB_PENC, VEPWC/IRQ5, VCPWC/IRQ4, IRL3, IRL2, IRL1, IRL0, Reserved/AUDATA[3]) * Input rise/fall time: 1 ns The output load circuit is shown in figure 33.89
IOL
LSI output pin CL
DUT output VREF
IOH Notes: 1. CL is the total value, including the capacitance of the test jig,etc. The capacitance of each pin is set to 30 pF. 2. IOL and IOH values are as shown in table 33.3, Permissible Output Currents.
Figure 33.89 Output Load Circuit
Rev. 1.0, 02/03, page 1265 of 1294
33.6
Change in Delay Time Based on Load Capacitance
Figure 33.90 is a chart showing the changes in the delay time (reference data) when a load capacitance equal to or larger than the stipulated value (30 pF) is connected to the LSI pins. When connecting an external device with a load capacitance exceeding the regulation, use the chart in figure 33.90 as reference for system design. Note that if the load capacitance to be connected exceeds the range shown in figure 33.90 the graph will not be a straight line.
+4.0 ns
+3.0 ns
Delay time
+2.0 ns
+1.0 ns
+0.0 ns +0 pF
+25 pF Load capacitance
+50 pF
Figure 33.90 Load Capacitance-Delay Time
Rev. 1.0, 02/03, page 1266 of 1294
Appendix
A. Package Dimensions
0.30 C B
Unit : mm
21.00
0.30 C A
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1.00
B
1.00
A B C D E F G H J K L M N P R T U V W Y
21.00
4x
0.20 1.00
1.00 A 256x0.60 0.10
0.35 C C
0.10 M C A B
0.15 C
Figure A.1 Package Dimensions (BGA 256 Pin)
0.500.10
1.70max
Rev. 1.0, 02/03, page 1267 of 1294
B.
Mode Pin Settings
The MD8-MD0 pin values are input in the event of a power-on reset via the RESET pin. Table B.1 Clock Operating Modes (SH7760)
External Pin Combination MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 PLL1 On (x12) On (x12) On (x6) On (x12) On (x6) On (x12) Off (x6) PLL2 On On On On On On Off CPU Clock 12 12 6 12 6 12 1 Frequency (vs. Input Clock) Bus Clock 3 3/2 2 4 3 6 1/2 Peripheral Module Clock 3 3/2 1 2 3/2 3 1/2 FRQCR Initial Value H'0E1A H'0E2C H'0E13 H'0E13 H'0E0A H'0E0A H'0808
Clock Operating Mode 0 1 2 3 4 5 6
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode. 2. For the ranges input clock frequency, see the description of the EXTAL clock input frequency (fEX) and the CKIO clock output (fOP) in section 33.3.1, Clock and Control Signal Timing.
Table B.2
Area 0 Memory Map and Bus Width
Pin Value
MD6 0
MD4 0
MD3 0 1
Memory Type Setting prohibited Setting prohibited Setting prohibited MPX interface Setting prohibited SRAM interface SRAM interface SRAM interface
Bus Width Setting prohibited Setting prohibited Setting prohibited 32 bits Setting prohibited 8 bits 16 bits 32 bits
1
0 1
1
0
0 1
1
0 1
Rev. 1.0, 02/03, page 1268 of 1294
Table B.3
Pin Value MD5 0 1
Endian
Endian Big endian Little endian
Table B.4
Pin Value MD7 0 1
MFI Mode/LCD Mode
MFI Mode/LCD Mode MFI mode LCD mode
Table B.5
Pin Value MD8 0 1
Clock Input
Clock Input External input clock Crystal resonator
Rev. 1.0, 02/03, page 1269 of 1294
C.
C.1
Pin Functions
Pin States Pin States in Reset, Power-Down State, and Bus-Released State
Reset Standby Sleep I O*
15
Table C.1
Bus Release I Z*5 Z*5 Z Z*5 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5 O I I O O I I PI PI PI PI O PI/O I I
Signal Name RDY*
9
Pin Name
I/O I O O I/O O O O O O O O O O
Power-on PI H H Z PZ H H H H H H H H PI PI L L PI PI PI PI PI PI O PI/O I I
Manual I H H Z*6 Z* /O* O* O*
2 5 4
Software Z Z*5/H*3 Z*5/H*3 Z*6 Z* /O*
5 3
Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
CS0 - CS6 BS D0 - D31 A0 - A25 WE3/DQM3/ICIOWR WE2/DQM2/ICIORD WE1/DQM1 WE0/DQM0/REG RAS RD/CASS/FRAME RD/WR BACK BREQ*
9
O*
15
Z*6 O O*15 O*15 O*15 O*15 O*15 O*
15
Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z*5/O*1 Z* /O*
5 1
2
O* O*
2
2
O*
2
O* H H I I L L I I PI PI PI PI O
2
O*15 O I I O* O* I I PI PI PI PI O PI/O I I
15
Z*5/H*3 H Z Z Z* /O* Z* /O* Z Z PZ PZ PZ PZ O PZ/O Z Z
9 9 10
I
9
DREQ0 - DREQ1* DACK0 - DACK1 DRAK0 - DRAK1 IRL0 - IRL3* NMI*
9 9
I O O I I I I I I O I/O I I
Z Z Z Z Z Z Z Z Z Z Z Z
15
10
TRST TCK TMS TDI TDO ASEBRK/BRKACK MD0*9 MD1*
9
PI/O I I
Rev. 1.0, 02/03, page 1270 of 1294
Reset Signal Name MD2*
9
Standby Sleep I I/O* I/O* I I I I I PI O
16 15
Bus Release I I I I I I I I PI
8
Pin Name
I/O I
Power-on I PI* PI*
7
Manual I I I I I I I I PI O PZ/O* O*2 I I O I/O I O I/O O O I/O I O I/O I O I/O O O I/O
Software Z Z/H* Z/H* Z Z Z Z I PI O
16 10
Hardware Z Z Z Z Z Z Z I I Z/O*
MD3/CE2A* MD4/CE2B* MD5*9
9
I/O I/O I
9
9
7
15
10
PI*7 PI* I I I PI O O H I PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ
7
MD6/IOIS16* MD7* MD8*
9
I I I I I O O O I CAN0_NERR AUDCK PA7 I O I/O I O I/O O O I/O I O I/O I O I/O O O I/O
9
RESET MRESET STATUS0 - STATUS1 CKIO CKE CA CAN0_NERR/ AUDCK*
11
O PZ/O*16 O*2 I I O I/O I O I/O O O I/O I O I/O I O I/O O O I/O
PZ/O* O*2 I I O I/O I O I/O O O I/O I O I/O I O I/O O O I/O
PZ/O* L I I O I/O Z O Z/O O O I/O I O I/O Z O Z/O O O I/O
16
Z Z I Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
CAN0_RX/ AUDATA[2]*
11
CAN0_RX AUDATA[2] PA6
CAN0_TX/ AUDATA[0]*
11
CAN0_TX AUDATA[0] PA5
CAN1_NERR/ AUDSYNC*
11
CAN1_NERR AUDSYNC PA4
CAN1_RX/ AUDATA[3]*
11
CAN1_RX AUDATA[3] PA3
CAN1_TX/ AUDATA[1]*
11
CAN1_TX AUDATA[1] PA2
Rev. 1.0, 02/03, page 1271 of 1294
Reset Signal Name SSI0_SCK/ HAC_SD_IN0/ BS2*
11
Standby Sleep I/O I O I/O I/O O I/O I/O O I/O I/O I I/O I/O O I/O I/O O I/O I/O I/O O I/O I/O O I/O I/O O I I/O I/O O I Software Z/O Z O Z/O Z/O O Z/O Z/O O Z/O Z/O Z Z/O Z/O O Z/O Z/O O Z/O I/O I/O O I/O I/O O I/O I/O O I I/O I/O O I Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I/O I O I/O I/O O I/O I/O O I/O I/O I I/O I/O O I/O I/O O I/O I/O I/O O I/O I/O O I/O I/O O I I/O I/O O I
Pin Name SSI0_SCK HAC_SD_IN0 BS2 PB7
I/O I/O I O I/O I/O O I/O I/O O I/O I/O I I/O I/O O I/O I/O O I/O I/O I/O O I/O I/O O I/O I/O O I I/O I/O O I
Power-on PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ
Manual I I O I/O I O I/O I O I/O I I I/O I O I/O I O I/O I/O I/O O I/O I/O O I/O I/O O I I/O I/O O I
SSI0_WS/ HAC_SYNC0*
11
SSI0_WS HAC_SYNC0 PB6
SSI0_SDATA/ HAC_SD_OUT0*
11
SSI0_SDATA HAC_SD_OUT0 PB5
SSI1_SCK/ HAC_SD_IN1*11
SSI1_SCK HAC_SD_IN1 PJ4
SSI1_SDATA/ HAC_SD_OUT1*
11
SSI1_SDATA HAC_SD_OUT1 PJ3
SSI1_WS/ HAC_SYNC1*
11
SSI1_WS HAC_SYNC1 PJ5
MFI-D0/ LCD_DATA0*
11
PC7 MFI-D0 LCD_DATA0
MFI-D1/ LCD_DATA1*
11
PC6 MFI-D1 LCD_DATA1
MFI-D2/ LCD_DATA2/ IRQ6*
11
PC5 MFI-D2 LCD_DATA2 IRQ6
MFI-D3/ LCD_DATA3/ IRQ7*
11
PC4 MFI-D3 LCD_DATA3 IRQ7
Rev. 1.0, 02/03, page 1272 of 1294
Reset Signal Name MFI-D4/ LCD_DATA4/ DREQ2*
11
Standby Sleep I/O I/O O I I/O I/O O O I/O I/O O I I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O Software Z/O Z/O O Z I/O I/O O O Z/O Z/O O Z I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I/O I/O O I I/O I/O O O I/O I/O O I I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O
Pin Name PC3 MFI-D4 LCD_DATA4 DREQ2
I/O I/O I/O O I I/O I/O O O I/O I/O O I I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O
Power-on PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ
Manual I/O I/O O I I/O I/O O O I/O I/O O I I/O I/O O O I/O I/O O I/O I/O O I/O I/O O I/O I/O O
MFI-D5/ LCD_DATA5/ DRAK2/DACK2*
11
PC2 MFI-D5 LCD_DATA5 DRAK2/DACK2
MFI-D6/ LCD_DATA6/ DREQ3*
11
PC1 MFI-D6 LCD_DATA6 DREQ3
MFI-D7/ LCD_DATA7/ DRAK3/DACK3*
11
PC0 MFI-D7 LCD_DATA7 DRAK3/DACK3
MFI-D8/ LCD_DATA8*
11
PD7 MFI-D8 LCD_DATA8
MFI-D9/ LCD_DATA9*
11
PD6 MFI-D9 LCD_DATA9
MFI-D10/ LCD_DATA10*
11
PD5 MFI-D10 LCD_DATA10
MFI-D11/ LCD_DATA11*
11
PD4 MFI-D11 LCD_DATA11
Rev. 1.0, 02/03, page 1273 of 1294
Reset Signal Name MFI-D12/ LCD_DATA12*
11
Standby Sleep I/O I/O O I/O I/O O I/O I/O O I/O I/O O O I I/O I O I/O I O I/O I O I/O I O I/O Software I/O I/O O I/O I/O O I/O I/O O I/O I/O O O Z Z/O I O I/O Z O Z/O Z O Z/O I O I/O Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I/O I/O O I/O I/O O I/O I/O O I/O I/O O O I I/O I O I/O I O I/O I O I/O I O I/O
Pin Name PD3 MFI-D12 LCD_DATA12
I/O I/O I/O O I/O I/O O I/O I/O O I/O I/O O O I I/O I O I/O I O I/O I O I/O I O I/O
Power-on PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ
Manual I/O I/O O I/O I/O O I/O I/O O I/O I/O O O I I/O I O I/O I O I/O I O I/O I O I/O
MFI-D13/ LCD_DATA13*
11
PD2 MFI-D13 LCD_DATA13
MFI-D14/ LCD_DATA14*
11
PD1 MFI-D14 LCD_DATA14
MFI-D15/ LCD_DATA15*
11
PD0 MFI-D15 LCD_DATA15
MFI-INT/ LCD_CLK*
11
MFI-INT LCD_CLK PE7
MFI-CS/ LCD_DON*
11
MFI-CS LCD_DON PE6
MFI-E/ LCD_CL1*
11
MFI-E LCD_CL1 PE5
MFI-MD/ LCD_CL2*
11
MFI-MD LCD_CL2 PE4
MFI-RS/ LCD_M_DISP*
11
MFI-RS LCD_M_DISP PE3
Rev. 1.0, 02/03, page 1274 of 1294
Reset Signal Name MFI-RW/ LCD_FLM*
11
Standby Sleep I O I/O O I/O I I/O I O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O O O I/O I/O O I/O I/O Software Z O Z/O O I/O Z Z/O I O I/O I O I/O I/O I/O I/O I/O Z/O Z/O Z/O Z/O Z Z/O Z/O O O Z/O Z/O O Z/O Z/O Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z I/O I/O I/O I/O Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I O I/O O I/O I I/O I O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O O O I/O I/O O I/O I/O
Pin Name MFI-RW LCD_FLM PE2
I/O I O I/O O I/O I I/O I O I/O I O I/O I/O I/O I/O I/O
Power-on PZ PZ PZ PZ PZ PZ PZ PZ L PZ PZ L PZ I I I I PI PI PI PI PI PI PI PZ PZ PI PI PZ PI PI
Manual I O I/O O I/O I I/O I L I/O I L I/O I I I I I I I I/O I I/O I O O I/O I O I I/O
HAC_RES*
11
HAC_RES PJ6
HAC_BIT_CLK0*
11
HAC_BIT_CLK0 PJ7
VCPWC/IRQ4*
11
IRQ4 VCPWC PE1
VEPWC/IRQ5*
11
IRQ5 VEPWC PE0
I2C0_SCL(O/D)*
14
I2C0_SDA(O/D)* I2C1_SCL(O/D)*
14
14
I2C1_SDA(O/D)* HSPI_TX/ SIM_D/ MCDAT*
11
14
HSPI_TX SIM_D MCDAT PF3
I/O I/O I/O I/O I I/O I/O O O I/O I/O O I/O I/O
HSPI_RX*
11
HSPI_RX PF2
HSPI_CLK/ SIM_CLK/ MCCLK*
11
HSPI_CLK SIM_CLK MCCLK PF1
HSPI_CS/ SIM_RST/ MCCMD*
11
HSPI_CS SIM_RST MCCMD PF0
Rev. 1.0, 02/03, page 1275 of 1294
Reset Signal Name CMT_CTR0/ TCLK*
11
Standby Sleep I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O Z/O I/O I/O I/O I/O I/O I/O I/O I I/O Z/O I/O I/O I/O I/O I/O I/O I/O Software Z/O Z Z/O Z/O Z/O Z/O Z/O Z/O Z/O Z/O I/O Z I/O Z/O I/O Z/O I/O Z/O I/O Z/O I/O Z I/O Z/O I/O Z/O I/O Z/O I/O Z/O I/O Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O Z/O I/O I/O I/O I/O I/O I/O I/O I I/O Z/O I/O I/O I/O I/O I/O I/O I/O
Pin Name CMT_CTR0 TCLK PB4
I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I/O I/O I/O I/O I/O I/O I/O I I/O O I/O I/O I/O I/O I/O I/O I/O
Power-on PI PI PI PI PI PI PI PI PI PI PI PI PI PZ PI PI PI PI PI PI PI PI PI PZ PI PI PI PI PI PI PI
Manual I I I/O I I/O I I/O I I/O I I/O I I/O Z I/O I I/O I I/O I I/O I I/O Z I/O I I/O I I/O I I/O
CMT_CTR1*11
CMT_CTR1 PB3
CMT_CTR2*
11
CMT_CTR2 PB2
CMT_CTR3*
11
CMT_CTR3 PB1
SCIF0_CLK*
11
SCIF0_CLK PG7
SCIF0_RXD*11
SCIF0_RXD PG6
SCIF0_TXD*
11
SCIF0_TXD PG5
SCIF1_CLK*
11
SCIF1_CLK PG4
SCIF1_CTS*
11
SCIF1_CTS PG3
SCIF1_RTS*
11
SCIF1_RTS PG2
SCIF1_RXD*
11
SCIF1_RXD PG1
SCIF1_TXD*
11
SCIF1_TXD PG0
SCIF2_CLK*
11
SCIF2_CLK PH7
SCIF2_CTS*
11
SCIF2_CTS PH6
SCIF2_RTS*
11
SCIF2_RTS PH5
Rev. 1.0, 02/03, page 1276 of 1294
Reset Signal Name SCIF2_RXD*
11
Standby Sleep I I/O Z/O I/O O I/O O I/O O I/O O I/O O I/O I O I/O I/Z I/Z I/Z I/Z I I/O O I/O I I/O Software Z I/O Z/O I/O O I/O O I/O O I/O O I/O O I/O Z O Z/O Z Z Z Z Z Z/O O I/O Z Z/O Hardware Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bus Release I I/O Z/O I/O O I/O O I/O O I/O O I/O O I/O I O I/O I/Z I/Z I/Z I/Z I I/O O I/O I I/O
Pin Name SCIF2_RXD PH4
I/O I I/O O I/O O I/O O I/O O I/O O I/O O I/O I O I/O I I I I
Power-on PI PI PZ PI PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ Z Z Z Z PI PI PZ PZ PI PI
Manual I I/O Z I/O O I/O O I/O O I/O O I/O O I/O I O I/O Z Z Z Z I I/O O I/O I I/O
SCIF2_TXD*
11
SCIF2_TXD PH3
Reserved /AUDATA[3]*11 AUDATA[3] PK7 Reserved/AUDATA[2]*
11
AUDATA[2] PK6
Reserved /AUDATA[1]*
11
AUDATA[1] PK5
Reserved /AUDCK*
11
AUDCK PK4
Reserved /AUDSYNC*
11
AUDSYNC PK3
ADTRG/AUDATA[0]*
11
ADTRG AUDATA[0] PK2
AN0* AN1*
12
12
AN2*12 AN3*
12
UCLK*
11
UCLK PH2
I I/O O I/O I I/O
USB_PENC*
11
USB_PENC PH1
USB_OVC*
11
USB_OVC PH0
Rev. 1.0, 02/03, page 1277 of 1294
Reset Signal Name USB_DP*
13
Standby Sleep I/O I/O I I/O PZ/O O Software I I Z Z/O PZ/O O Hardware O O Z Z Z Z
Bus Release I/O I/O I I/O PZ/O O
Pin Name
I/O I/O I/O
Power-on O O PZ PZ PZ PZ
Manual I I I I/O PZ/O O
USB_DM*
13
HAC_BIT_CLK1*
11
HAC_BIT_CLK1 PJ2
I I/O O O
DCK*
11
DCK PJ1
I: Input O: Output H: High level output L: Low level output Z: Hi-z state PI: Input pulled up with a built-in pull-up resistance. PZ: Output pulled up with a built-in pull-up resistance. Notes: 1. Z (I) or O (refresh) according to the register contents (BCR1.HIZCNT). 2. Depends on the refresh operation. 3. Z (I) or H (retained) according to the register contents (BCR1.HIZMEM). 4. Output when the auto-refresh is selected. 5. Pulled up or not according to the register contents (BCR1.OPUP). 6. Pulled up or not according to the register contents (BCR1.DPUP). 7. Pulled up using the pull-up MOSs. However, the pull-up MOSs cannot be used to pullup the mode pins at a power-on reset. For this purpose, pull-up or pull-down outside the LSI. 8. Z or O according to the register contents (STBCR2.STHZ). 9. Pulled up or not according to the PFC register settings (see section 24, Pin Function Controller (PFC)). However, the PFC register settings are invalid in hardware standby mode. 10. Hi-z or not according to the PFC register settings (see section 24, Pin Function Controller (PFC)). 11. Pulled up or not, and the multiplexed functions for IP modules are selected by the PFC register settings (see section 24, Pin Function Controller (PFC)). However, the PFC register settings are invalid in hardware standby mode. For details of the I/O control for the selected IP modules, see the corresponding section. Selection of the GPIO functions and the I/O control of the GPIO are determined according to the GPIO register settings (see section 24, Pin Function Controller (PFC)). 12. According to the ADC register settings. Hi-z at initialization. 13. Pull-down for USB pins while not used. 2 14. Only low level output since these pins are open-drain pins. Pulled up when the I C is not in use. 15. Depends on the refresh and DMAC operations. 16. Z or O according to the register contents (FRQCR.CKOEN).
Legend:
Rev. 1.0, 02/03, page 1278 of 1294
C.2
Handling of Unused Pins
* When PLL1 is not used VDD_PLL1: Power supply VSS_PLL1: Power supply * When PLL2 is not used VDD_PLL2: Power supply VSS_PLL2: Power supply * When PLL3 is not used VDD_PLL3: Power supply VSS_PLL3: Power supply * When on-chip crystal oscillator is not used XTAL: Leave unconnected VDD_CPG: Power supply VSS_CPG: Power supply * When I C is not used
2
I2C0_SCL: Pull-up outside the LSI. I2C0_SDA: Pull-up outside the LSI. I2C1_SCL: Pull-up outside the LSI. I2C1_SDA: Pull-up outside the LSI. * When USB is not used USB_DP: Pull-down outside the LSI. USB_DM: Pull-down outside the LSI.
Rev. 1.0, 02/03, page 1279 of 1294
D.
(1)
Synchronous DRAM Address Multiplexing Tables
BUS 32 AMX 0 (16M: 512k x 16b x 2) x 2 * AMXEXT 0 16M, column-addr-8bit
Synchronous DRAM Address Pins
4MB
Function
SH7760 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1280 of 1294
(2)
BUS 32 AMX 0
(16M: 512k x 16b x 2) x 2 * AMXEXT 1 16M, column-addr-8bit
Synchronous DRAM Address Pins
4MB
Function
SH7760 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A21 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1281 of 1294
(3)
BUS 32 AMX 1
(16M: 1M x 8b x 2) x 4 * AMXEXT 0 16M, column-addr-9bit
Synchronous DRAM Address Pins
8MB
Function
SH7760 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A22 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1282 of 1294
(4)
BUS 32 AMX 1
(16M: 1M x 8b x 2) x 4 * AMXEXT 1 16M, column-addr-9bit
Synchronous DRAM Address Pins
8MB
Function
SH7760 Series Address Pins RAS Cycle A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A21 A22 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A21 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1283 of 1294
(5)
BUS 32 AMX 2
(64M: 1M x 16b x 4) x 2 * 64M, column-addr-8bit
16MB
Function
SH7760 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A23 A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
Synchronous DRAM Address Pins
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1284 of 1294
(6)
BUS 32 AMX 3
(64M: 2M x 8b x 4) x 4 * 64M, column-addr-9bit
32MB
Synchronous DRAM Address Pins Function
SH7760 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used A24 A23 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1285 of 1294
(7)
BUS 32 AMX 4
(64M: 512k x 32b x 4) x 1 * 64M, column-addr-8bit
8MB
Function
SH7760 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 A21 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
Synchronous DRAM Address Pins
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1286 of 1294
(8)
BUS 32 AMX 5
(64M: 1M x 32b x 2) x 1 * 64M, column-addr-8bit
8MB
Function
SH7760 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A22 0 H/L 0 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
Synchronous DRAM Address Pins
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Rev. 1.0, 02/03, page 1287 of 1294
(9)
BUS 32 AMX 6
(64M: 4M x 4b x 4) x 8 * (128M: 4M x 8b x 4) x 4 AMXEXT0 64M, column-addr-10bit
64MB
SH7760 Series Address Pins RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Not used Not used
Synchronous DRAM Function CAS Cycle Address Pins A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address precharge setting Address BANK selects bank address
A25 A24 0 H/L A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
Rev. 1.0, 02/03, page 1288 of 1294
(10) BUS 32 AMX 6
(256M: 4M x 16b x 4) x 2 * AMXEXT1 256M, column-addr-9bit
Synchronous DRAM Address Pins A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
64MB
Function BANK selects bank address
SH7760 Series Address Pins RAS Cycle A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 Not used Not used CAS Cycle A25 A24 0 0 H/L 0 A10 A9 A8 A7 A6 A5 A4 A3 A2
Address precharge setting Address
Rev. 1.0, 02/03, page 1289 of 1294
(11) BUS 32 AMX 7
(16M: 256k x 32b x 2) x 1 * 16M, column-addr-8bit
2MB
Function
SH7760 Series Address Pins RAS Cycle A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Not used Not used A20 H/L 0 A9 A8 A7 A6 A5 A4 A3 A2 CAS Cycle
Synchronous DRAM Address Pins
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BANK selects bank address Address precharge setting Address
Note: * Example configurations of synchronous DRAM
Rev. 1.0, 02/03, page 1290 of 1294
E.
Instruction Prefetching and Its Side Effects
This LSI is provided with an internal buffer for holding pre-read instructions, and always performs pre-reading. Therefore, program code must not be located in the last 20-byte area of any memory space. If program code is located in these areas, the memory area will be exceeded and a bus access for instruction pre-reading may be initiated. A case in which this is a problem is shown below.
. . . . . ADD R1,R4 JMP @R2 NOP NOP
Address H'03FF FFF8 H'03FF FFFA Area 0 H'03FF FFFC H'03FF FFFE Area 1 H'0400 0000 H'0400 0002
PC (program counter)
Instruction prefetch address
Figure E.1 Instruction Prefetch Figure E.1 presupposes a case in which the instruction (ADD) indicated by the program counter (PC) and the address H'0400 0002 instruction prefetch are executed simultaneously. It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction. In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1 may be initiated. Instruction Prefetch Side Effects 1. It is possible that an external bus access caused by an instruction prefetch may result in misoperation of an external device, such as a FIFO, connected to the area concerned. 2. If there is no device to reply to an external bus request caused by an instruction prefetch, hangup will occur. Remedies 1. These illegal instruction fetches can be avoided by using the MMU. 2. The problem can be avoided by not locating program code in the last 20 bytes of any area.
Rev. 1.0, 02/03, page 1291 of 1294
F.
Power-On and Power-Off Procedures
Supply the internal power after supplying power to the I/O and CPG. Supply power to VDDQ and VDD-CPG simultaneously. At power-on, the RESET signal is low. Normally, supply power to the I/O and CPG before (or at the same time as) entering the signal lines (RESET, MRESET, MD0 to MD8, and external clock). If the signal lines are entered first, the LSI may be damaged. Input high level to MRESET in compliance with the voltage level of the I/O and CPG power supply voltage.
* Power-on
* Power-off When turning off the power, there are no restrictions for the timing of RESET and MRESET. Turn off the I/O and CPG power supply voltage after (or at the same time as) turning off the internal power supply voltage. However, note that the internal power supply voltage may exceed the I/O and CPG power supply voltage by a maximum of 0.3 V only when the system is being turned off. The power supply level must be lowered in compliance with the I/O and CPG power supply voltage. * The ratings and procedures for power-on and power-off are given below. VDDQ = VDD-CPG = 0 V The LSI may be damaged if -0.3 V < Vin < VDDQ + 0.3 V -0.3 V < VDD, VDD-PLL1/2/3 < VDDQ + 0.3 V are not satisfied when VDDQ = VDD-CPG.
Power-on VDDQ 2.0V 1.2V GND ton 0ton<10ms toff 0toff<10ms VDD, VDD-PLL1/2/3 Power-off
Figure F.1 Power-On and Power-Off Procedures
Rev. 1.0, 02/03, page 1292 of 1294
G.
Version registers
The registers related to the version registers are shown below. Table G.1 Register Configuration
Abbrev. PVR PRR R/W R R Initial value H'0405 01xx H'0000 05xx P4 Address H'FF00 0030 H'FF00 0044 Area 7 Address H'1F00 0030 H'1F00 0044 Size 32 32
Register Name Processor version register Product register
Legend x: Undefined
(1) Processor Version Register (PVR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
version information 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 1 R 10 0 R 9 0 R 8 0 R 7 0 R 0 R 1 R 0 R 6 0 R 5 0 R 4 0 R 3 1 R 2 0 R 1 1 R 0 -
version information 0 R 0 R 0 R 0 R 0 R
(2) Product Register (PRR)
Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
version information 0 R 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 1 R 0 R 1 R 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 -
version information 0 R 0 R 0 R 0 R 0 R
Rev. 1.0, 02/03, page 1293 of 1294
Rev. 1.0, 02/03, page 1294 of 1294
SH7760 Hardware Manual
Publication Date: 1st Edition, February 2003 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2003. All rights reserved. Printed in Japan.

▲Up To Search▲

Price & Availability of SH7760

	To Download SH7760 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .